An ultra-low energy analog and RF circuit technology for emerging applications

Transcription

1 超低エネルギーアナログ RF 回路技術と新規分野への展開 An ultra-low energy analog and RF circuit technology for emerging applications Akira Dept. of Physical Electronics Graduate School of Science and Engineering 2009/11/30

2 Lab. members 1 Professor: Akira Assoc. Prof.: Kenichi Okada (RF) Assist. Prof.: Masaya Miyahara (ADC/DAC) 2 technical staff, 3 secretaries Founded in doctor students (3 from corp.) 20 master students 6 undergraduate students some researchers from corp. 50 people 20 Japanese students and 20 foreign students

3 Focus of Laboratory 2 Ultra-high frequency Core circuit tech. RF-CMOS For mm-wave Ultra-fast ADC/DAC SDR Re-config. RF Applied LSIs and systems Transceiver for 60GHz several Gbps 64QAM 1Gbps Baseband Broadband CMOS-radios Particle detector for nuclear physics Ultra-low power Ultra-low Pd ADC/DAC Sensor capsule for health-care

4 SoCs for mm-wave systems 3 We now developing SoCs for mm-wave systems 1.Long range: 4km Fixed point :38GHz, Gbps with JRC and NEC 2.Short range: a few meter :60GHz, 3-10 Gbps with Sony Provided by Sony

5 Long range mm-wave: Fixed point 38GHz,1Gbps 4 System Campus mm wave network Equipment with plane Antenna Networks durability against rain

6 Developing 60GHz mm-wave circuits 5 We now developing 60GHz CMOS Transceiver.

7 6 An ultra-low energy analog and RF circuit technology for emerging applications

8 Flash ADC architecture Expecting highest speed Comparator determines the ADC performance 7 Low offset mismatch and noise are preferable Flash ADC Comparator Array 6b: 63 V q V 2 FS N V q =16mV, Mismatch <3mV Offset mismatch

9 Degradation of ENOB 8 Degradation of ENOB in flash ADC is basically determined by offset mismatch and thermal noise of comparators. For example; 6bit ADC, ENOB=5.7bit V q =16mV, V off <3mV 5.7bit ENOB 2 Voff V 1 2 log q 2 Vn Vq 3mV V V off n : : Distribution Distribution of offset of noise

10 FoM of Flash ADC 9 FoM of flash ADC is determined by energy consumption of unit comparator and the degradation of effective bit. Reduction of consumed energy and increase of ENOB are very important FoM P E N d c s ENOB E ENOB N ENOB c 2 f s 2 f s 2 f 2 E 2 c CV DD E c : Energy/Comparator E c is basically proportional to the capacitance

11 Tradeoff: mismatch and energy consumption 10 There is a serious tradeoff between mismatch of transistor and gate area. Larger transistor is required to reduce mismatch voltage and results in increase of gate area and consumed power. Offset mismatch (mv) mV 0 Mismatch compensation E c =50fJ Transistor size (um 2 ) オフセット消費電力 E c (fj) 1 V o ffset ( ) LW E C LW c E c Example 6bit ADC: V off <3mV E C <50fJ0.1um 2 V off =20mV Needs mismatch compensation 20mV 3mV c V 1 2 offset

12 Mismatch compensation of dynamic comparator 11 The mismatch can be compensated by capacitance and current. FN INP V i 2 V DD CLK FP INN I V i D I D 2 C CLK L Equivalent circuit of the first stage. V i g m V i I D V L C L V DD C L CLK V DD V L SN SP FP or FN t d CLK dt dv d i t t Delay time dt di d d d D di dv V V eff D i i t d VDDC 2I t t d d VDDC 2I D L g I m D C CL L D L t I I D d D V eff I g D m g I m D V gs di V D eff V V eff T I V V D eff eff V DD /2 t d t td time d V V eff i V i V eff C CL L I I D D

13 Digital calibration method 12 Resistor ladder type Capacitor array type Binary weighted capacitor array 2009/11/30 Y. Asada, Tokyo Tokyo TechTech.

14 Effect of analog mismatch compensation 13 We can reduce the mismatch voltage form 14mV to 1.7mV at sigma. Measured result V offset Voffset V offset M. Miyahara, Y. Asada, D. Paik, and A., "A Low- Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," A-SSCC, Nov

15 Match with noise simulation 14 The deduced equation has a good match with simulation. P (out=high) [%] Noise in comparator V 2 in ktv C δvin(σ) [mv] L V eff DD We deduced this noise equation Estimation(α=2) Estimation(α=1) Simulation ΔVin [mv] CL [ff]

16 Comparison of comparators 15 Double clock Single clock NMOS+PMOS Double gm NMOS Single gm FN INP CLK INN FP CLK SN SP CLK CLK Conventional Our proposed M. van Elzakker, Ed van Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge- Redistribution ADC, IEEE ISSCC 2008, Dig. of Tech. Papers, pp , Feb M. Miyahara, Y. Asada, D. Paik, and A., "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," A-SSCC, Nov

17 Noise reduction of comparator 16 Proposed double-tail latch comparator can reduce noise down to 1/3. V DD = 1.0 V, Fc = 4 GHz, Transient-Noise simulations. (Offset calibration is not used.) P (out=high) [%] Proposed V n ( ) = 0.66 mv cm = 0.6 V Conventional V n ( ) = 2.1 mv Vn( ) [mv] M. Miyahara, Y. Asada, D. Paik, and A., "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," A- SSCC, Nov / V in V offset [mv]

18 6bit, 7mW, 250fJ, 700MS/s Sub-ranging ADC 17 Compensation of offset variation with good efficiency A1. Double-tail latched comparator A2. Digital calibration by capacitance adjusting Reference voltage generation of sub-range B1. Capacitive DAC (C-DAC) B2. Gate-weighted interpolation Proposed circuits consume no static power. Y. Asada, K. Yoshihara,T. Urano, M. Miyahara and A., A 6bit, 7mW, 250fJ, 700MS/s Subranging ADC A-SSCC, pp , Nov GW interpolation DTL comparator PMOS varactor + CAL register Encode & Error Correction

19 Issue of reference voltage generation 18 IN T/H Coarse scale Fine scale Upper bit 7 7 Lower bit 7 Previous fine scale 7 15 Resistor ladder + SW MUX: Static power consumption in resistor ladder Trade-off between settling time and power consumption Many SW for fine reference t LATCH Coarse conversion t DAC t CLK Fine conversion Power consumption is inevitable with high speed operation.

20 C-DAC 19 CAD can realize fast operation with low Pd 19 D<n>=1V REFP D<n>=0V REFN Advantage : Operating as S/H circuit No static power consumption ( 360W@1GHz ) Smaller C u realize faster settling time (t DAC = 3.4 r on C U < r ON = 1k, C U = 15fF)

21 Interpolation comparator 20 Interpolation can match upper and lower conversion ranges self-consistently. FADC composed of interpolation comparator Threshold voltage of i th comparator is the cross-point of V Pi, V Ni. V Pi, V Ni : interpolated signal of CDAC outputs. V Pi ( 8 iv ) iv ( 8 ), V iv iv 8 8 INPa INPb INNa INNb Ni V OUT V INPa i i V Ni V INNb V IN V Pi V INNa V INPb OUT V IN

22 Comparator Circuits 21 Comparator with offset CAL realizes small area and high accuracy. Offset CAL V dd CLK V outp W Pa W Pb W Nb W Na V outn V INP_a V INP_b V INN_b V INN_a Gate weighted interpolation

23 22 Chip photo & Layout 22 6 bit ADC has been realized in a 90 nm 10M1P CMOS technology with a chip area of 0.13mm 2

24 Performance Summary 23 World lowest FoM ADC!! Proposed circuits has realized the best power efficiency. [1] [2] [3] [4] [6] This Work Resolution(bit) fs(gs/s) SNDR(DC/Nyq.) 35/32 34/33 31/30 34/28 35/33 35/34 Pd (mw) Active area(mm VDD(V) / FoM(pJ) CMOS Tech.(nm Architecture Flash Flash Pipeline 2b-SAR Subrange Subrange [1] C-Y. Chen, VLSI Circuits [2] B-W. Chen, A-SSCC [3] F. C. Hsieh, A-SSCC [4] Z. Cao, ISSCC [6] Y. C. Lien, A-SSCC 2008.

25 Circuit technology for emerging applications 24 Micro medical systems Ultra-low power Capacitance to Digital converter Can be applied to micro-sensor networks Tire pressure sensor Nuclear particle detector Pixels has an A/D converter in each Can be applied to medical imaging devices Full digital DC/DC converter Low power and high speed and resolution ADC Every power supply systems On-chip power supply

26 Capsule to measure bladder pressure 25 Measure the bladder pressure and send the data in short range (15 cm) Due to battery life 4 days with total current of 100uA All analog and RF circuits consumes only 30uA

27 SAR Capacitance to Digital Converter 26 SAR ADC + Capacitive pressure sensor Low power Can compensate the offset capacitance Small area Insensitive to operating voltage Kota Tanaka, Yasuhide Kuramochi, Takashi Kurashina, Kenichi Okada, and Akira V cm V x A 0.026mm2 Capacitance-to-Digital Converter for Biotelemetry Applications Using a Charge Redistribution Technique ASSCC 2007 V y C s C R1 C C C C C RN C x V DD kv DD

28 Ultra-low power CDC 27 Improved Capacitance to Digital Converter b SAR like architecture 2. Self-clocking 3. Single to differential 30 times/sec Tuan Minh Vo,Yasuhide Kuramochi, Masaya Miyahara,Takashi Kurashina, and Akira A 10-bit, 290 fj/conv. Steps, 0.13mm22, Zero-Static Power, Self-Timed Capacitance to Digital Converter. SSDM 2009, OCT

29 Accuracy 28 Same accuracy as an impedance meter E E E-11 CDC からの出力コード CDC impedance analizer 9.80E E E E-12 測定器による計測結果容量値 [F] E E 入力圧力 [ kpa] 6.80E-12

30 New particle detector for nuclear physics 29 Developing new particle detector for nuclear physics QPIX A., Vu Minh Khoa, M. Miyahara, T. Kurashina, A. Sugiyama, K. Miuchi, and S. Tanaka, A new particle detector LSI Qpix: integrating high speed ADC for each pixel, The 1st international conference on Technology and Instrumentation in Particle Physics, March m 0.18um CMOS 100 m Further optimization m m

31 Basic functions of QPIX 30 A world first particle detector having an ADC in each pixels. Readout Pixels time Cathode E field TOT QPIX can measure the total charge Q, as well as TOF and TOT. Ionized electron Q track TOF MUX 6b10b in next step

32 Experimental setup and measured result 31 We could detect and measure the nuclear particles 16 pixels Trajectory of particle Measuring board

33 Low voltage LC VCO 32 Developed 0.2V LC VCO Class C with start-up circuit K. Okada, Y. Nomiyama, R. Murakami, and A., A 0.114mW Dual-Conduction Class-C CMOS VCO with 0.2V Power Supply, Dig. Symp. VLSI Circuits, pp , June, 2009.

34 Performance of 0.2V VCO 33 Low power of 110uW at 4.5GHz generation 0.2V FoM=187dBc/Hz

35 Development of full digital power supply 34 DC/DC converter uses analog control method. We have started to develop full digital power supply.

36 ADC and PWM for full digital power supply 35 We have started to develop ADC and PWM for the first step ADC: 12bit, 80MSps, 5mW has low power mode and high speed mode Out In 3) PWM 2) Digital Filter 1) ADC 09 年に開発開始 10 年に開発開始 09 年に開発開始

37 Micro-power systems: PVT issues in digital LSIs 36 Fluctuation of device parameter, stabilization of power supply voltage, and reduction of local heating become serious issues in digital LSIs. Courtesy Dr. Vivek De, Intel

38 Adaptive Power supply voltage 37 Sakiyama et al., Symp. On VLSI Circuits 97 Adaptive supply voltage control circuits 0.35umCMOS 2.2M Tr 20MIPS 12mW (1.2V, internal) Ieak current 500uA: active 1uA: standby

39 High efficiency and low noise embedded DC/DC 38 High efficiency of 94% and low noise of 15mVpp. S.Sakiyama et al., ISSCC99 High Noise Chip Inductor Conventional Improved Low Noise Choke Coil Low Noise Chip Inductor 300mV 15mV