Silicon Photonics : Towards Heterogeneous and Multi-layer Integration for High Density Circuits

Transcription

1 Silicon Photonics : Towards Heterogeneous and Multi-layer Integration for High Density Circuits Stéphane Bernabé, Ségolène Olivier, Bertrand Szelag, Daivid Fowler, Christophe Kopp OPTICS, Dresden,

2 PACKAGING FOR PHOTONICS Silicon Photonics at Leti History Devices library & process flow Examples of circuits and modules Next challenges III-V integration Process development Achievements Advanced multilayer platforms Process developments Achievements Other platform evolution TSV Copper pillar for self alignment of microoptics Conclusion 2

3 PHOTONICS AT LETI French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Budget 318 M. 1,900 collaborators (250 PhDs) 2800 patents (>300 /yr) 680 publications /yr, 64 stratups 8,500 m² clean rooms For 200 and 300 mm wafers fab, operated 24/7 Photonic Department Est. 1978, 300 researchers, 60M budget Dedicated Silicon Photonics Lab 3

4 SILICON PHOTONICS STORY 1985 Soref s paper on Si optical properties for modulation Bookham ASOC devices 2001 Luxtera creation 2016 : Intel, ST, Acacia, launch SiPho products 2002 J.M. Fedeli Pioneered SiPho at Leti HELIOS project III-V Lab IRT Nanoelec 2017 O-Band MPW offer SiO2 Si SiO 2 DFB@1310nm + 32G EAM + SOA 4

5 BUILDING BLOCKS FOR OPTICAL DATA TRANSMISSION 5

6 TECHNOLOGY KEY PROCESS FEATURES 200 mm Si photonics platform Substrates : 8 SOI 310nm, compatible with ST foundry (300mm) 190 steps 24 litho levels 40 metrology/control steps 300mm Si photonics platform (dev) Process building blocks Multilevel silicon patterning PN Silicon junctions PiN Germanium junctions Integrated resistance (heater) Planarized BEOL : 2 AlCu routing levels UBM for flip-chip assembly 6

7 BASELINE TECHNOLOGY INTEGRATION SCHEME o Modulator junction formation & activation o Define all the photonic devices o Several silicon thicknesses and waveguide architectures o Photodetector patterning o Germanium selective epitaxy CMOS-based process with photonic dedicated optimizations o Photodetector contact formation o Si Modulator contact silicidation o Metal interconnection o Metal heater definition for wave length tuning CMOS standard process 7

8 TECHNOLOGY PASSIVE DEVICE LIBRARY O-Band, 1310nm Width Prop. loss Width 400 nm 1.5dB/cm 1.8µm Ins. Loss < 2.5dB 1dB BW 30 nm Loss < 0.5dB balance 3% Prop. loss 0.15dB/cm Width Prop. loss 320nm 3.5dB/cm Ins. Loss 1dB BW < 4dB 30 nm Loss Xtalk < 0.25dB >35dB Width Prop. loss 350nm 3.5 db/cm Ins. Loss Xtalk 1dB BW 2-3dB >20dB 1.5nm Szelag et al., "Multiple wavelength silicon photonic 200mm R&D platform for 25Gb/s and above applications, Photonics Europe 2016 Szelag et al., CMOS compatible 200mm silicon photonic platform suitable for high bandwidth applications SSDM,

9 FIBER COUPLERS O BAND 200mm process line 1D single pol. 1D 2D PDL < 0,5 db (2D grating) 2D Dual pol. Kopp et al., Silicon photonic circuits: on CMOS integration, fiber optical coupling and packaging, IEEE-JSTQE, 2010 S. Plantier, D. Fowler, K. Hassan, O. Lemonnier and R. Orobtchouk, "Impact of scattering element shape on polarisation dependent loss in two dimensional grating couplers," 2016 IEEE 13th International Conference on Group IV Photonics (GFP), Shanghai, 2016, pp

10 INTEGRATED PN JUNCTION MODULATOR Electro-optical characteristics MZM Length Vpi.Lpi RF BW 3dB Popt OUT MZM 4mm 1.9 V.cm 25GHz -11.8dBm 3mm 1.9 V.cm 28GHz -9.5dBm 2mm 1.9 V.cm 35GHz -8.5dBm Losses 0.55 db/mm Modulation characteristics B. Szelag, SSDM

11 BUTT-COUPLED SIGESI PHOTODIODE W=0.8µm O-Band, 1310nm Width 0.8µm Length 15µm Responsivity > 1.05A/W B. Szelag, SSDM 2017 W=0.8µm - 30Gb/s NRZ Dark -2V -2V 5 na > 40GHz 11

12 HIGH DATA RATE MODULES Low power 25Gbps photoreceiver 50µm pitch microbump 170 fj/bit -15 dbm sensitivity TIA design : Caltech Saaedi et al.. J. Lightwave Tech., 2015 EIC 0.8 x 1.3 mm² Reflective Tx for FTTH (EU FABULOUS project) QAM16 transmission on a single fiber Dedicated MZM segmented CMOS driver Straullu et al., ECOC PDP, 2016 Menezo et al., JLT, 34,10, Gbps receiver module WDM and SDM versions < -12dBm sensitivity at 10-9 BER EIC with 4pJ/bit consumption TIA design : ST microelectronics Bernabé et al., OIC 2016, Paper MB3 Castany et al., ESTC

13 NEXT CHALLENGES Silicon Photonics address circuits of increasing complexity Hundreds of optical functions on a chip Requires dedicated PDK in EDA tools Broadband coupling required for WDM modules Ease routing using multilayer photonics Laser source integration Several competing technologies Direct bonding approach : require CMOS compatibility Co-integration with complex «host chips» FPGA or switches with optical IOs Manycore computers architectures 13

14 HETEROGENEOUS III-V INTEGRATION Growth of the III-V wafers 2, 3, 4 III-V die or wafer bonding on processed SOI InP substrate removal Processing of SOI wafers 8 or 12 (modulators, detectors, passive waveguides, etc.) Processing of III-V dies/wafer 4 or 8 Heterostructure 3µm- thick Metallization of lasers, modulators and detec tors 14

15 INTEGRATED TRANSMITTER Co-integration of hybrid III-V/Si DBR laser + Si Mach-Zehnder modulator MZM length : 4 mm Voltage sweep : 2.5 V pp in push-pull Laser drive current : 100 ma Laser wavelength : nm 25 Gb/s Transmission over 10 km ER=4.7 db T. Ferrotti et al., «Co-integrated 1.3 µm hybrid III-V/Silicon tunable laser and silicon Mach-Zehnder modulator operating at 25 Gb/s», Opt. Exp., (2016) 15

16 HYBRID III-V/SI LASER TARGETED PROCESS Final objectives: o o o o o o CMOS compatible process for silicon part III-V die bonding on silicon 200 or 300mm Si wafers Compatible with mature silicon photonic platform Laser process steps cmos compatible process: No noble metals Conventional patterning steps Planarized multi-metal level BEOL 16

17 PRELIMINARY STUDIES: CMOS COMPATIBLE CONTACTS ON III-V o Best choice: Ni2P wo annealing for n-inp and Ni with 350 C annealing for P-InGaAs o Integration constraint & process cost => use the same contact for n-inp and P-InGaAs E. Ghegin, Ph. Rodriguez, M. Pasquali, I. Sagnes, J. L. Labar, V. Delaye, T. Card, J. Da Fonseca, C. Jany, F. Nemouchi, CMOS-Compatible Contacts to n-in, IEEE Trans. Electron Devices 64 (2017)

18 OPTICAL CHARACTERIZATION B. Szelag, IEDM

19 MULTIPLE PHOTONIC LAYERS Silicon on silicon Switching matrix, Silicon Nitride on silicon circuits Low loss platform (<1dB/cm) Reduced optical confinement Low thermal sensitivity [1] C; Kopp, Mature 25Gb/s silicon photonic platform towards multi-layer circuits for high integration level applications, Photoptics

20 ADVANCED GRATING COUPLERS O-BAND CWDM GRATING COUPLERS Leveraging Si/SiN multilayer Stack Hybrid SiN/Si fibre grating couplers allow a better IL/BW compromise for cwdm Wavelength (nm) Si std: (black line) IL median: 2dB -1dB BW median: ~25nm SiN/Si: (green line) IL median: 2,9dB -1dB BW median: >50nm Q. Wilmart et al, unreleased paper (c) (c) Wavelength (nm) SiN/Si SPGC Min. IL (db) SiN/Si SPGC Max. cwdm IL (db) Nom événement Nom Prénom 20

21 SIN MUX/DEMUX: ECHELLE GRATING DEMUX sensitivity to temperature DEMUX transmission (DUV litho) DEMUX transmission (e-beam litho) DUV IL (db) ebeam dB 10nm 10nm X-talk 10 db >20 db C. Sciancalepore, SSDM

22 ADVANCED PACKAGING THROUGH SILICON VIAS / PHOTONIC INTERPOSER Standalone System-in-package TL ~ 20 mm TL ~ 50 mm Abs(S12) TSV WB S. Bernabé, K. Rida, S. Menezo, IEEE Trans. Comp. Mfg and Pkg, 2016 L. Fourneaud, Internal report 22

23 OPTICAL NETWORK ON CHIP Photonic assisted processor Multi-cores bottlenecks Y. Thonnart, ISSCC

24 TAKE AWAY Standard SiPho platforms need to be upgraded to adress future applications (CWDM, ONoC ) Multilayer Photonics Definitely needed for WDM applications Laser source integration Full flow integration validated 3D Advanced packaging for photonics Enabler for System In Package and ONoC architectures 24

25 Thank you for your attention