Dries Van Thourhout IPRM 08, Paris

Transcription

1 III-V silicon heterogeneous integration ti Dries Van Thourhout IPRM 08, Paris InP/InGaAsP epitaxial layer stack Si WG DVS- BCB SiO 2 200nm

2 III-V silicon heterogeneous integration ti Dries Van Thourhout IPRM 08, Paris InP/InGaAsP epitaxial layer stack Si WG DVS- BCB SiO 2 200nm 1. Silicon photonics is great!!! 2. But we still need InP 3. III-V silicon integration 4. Devices

3 Acknowledgements Photonics Research Group III-V silicon integration: G. Roelkens, J. Van Campenhout, J. Brouckaert, L. Liu Silicon Processing W. Bogaerts, P. Dumon, S. Selvarajan, R. Baets EU IST-PICMOS team J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing) C. Seassal, P. Rojo-Romeo, P. Regreny, P. Viktorovitch (INL) (processing, epitaxy) R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy) C. Lagahe, B. Aspar (TRACIT) (planarization)

4 III-V silicon heterogeneous integration ti InP/InGaAsP epitaxial layer stack Si WG DVS- BCB SiO 2 200nm 1. Silicon photonics is great!!! 2. But we still need InP 3. III-V silicon integration 4. Devices

5 Silicon photonics Width (500nm) x Height (220nm) the solution to all our problems? Transparent at telecom wavelengths (1.3 µm, 1.55 µm) High refractive index contrast ultra-compact circuits SiO 2 (1-2 µm) ) Compatible with CMOS-processing Highest Silicon quality processes High yield, high repeatability Integration with electronics Pattern definition: DUV litho`?

6 Photonic wiring Low loss bends <0.3dB excess loss for splitters Excess bend loss [db/90 0 ] dB/ dB/ dB/ dB/ Radius [um] 97% transmission in crossings (b)

7 Wavelength dependent devices 0 FSR -5 transm mission [db] wavelength [nm]

8 Increasing Index Contrast Glass based devices Bend Radius ~ 5 mm 5 mm 5 cm 200 µm Silicon photonic ICs Bend Radius < 5µm InP/InGaAsP (bend radius ~ 500um)

9 Silicon Photonics Intel 40GHz Detector Fiber cable plugs here Luxtera Ethernet Tranceiver Ceramic Package IBM Modulator

10 Silicon Photonics Silicon photonics comes in many flavors Large rib type waveguides Small core devices Optimized for nanophotonics Small device size Easy coupling with fiber This work and many others Large device size e.g. Full CMOS integration Fabricated in CMOS process Directly integrated with electronics e.g.

11 III-V on silicon? Silicon photonics gives us: Excellent passives Fast modulators, fast photodetectors t t But: (almost) no light Need for integration ti with III-Vs Requirements High density (~10-20um device pitch) High alignment accuracy (~100nm) Waferscale processes

12 III-V silicon heterogeneous integration ti InP/InGaAsP epitaxial layer stack Si WG DVS- BCB SiO 2 200nm 1. Silicon photonics is great!!! 2. But we still need InP 3. III-V silicon integration 4. Devices

13 III-V on silicon There are several ways to integrate III-V VonSOI Flip-chip integration of opto-electronic components most rugged technology testing of opto-electronic components in advance slow sequential process (alignment accuracy) low density of integration Hetero-epitaxial growth of III-V on silicon collective process, high density of integration See other talks at this conference mismatch in lattice constant, CTE, polar/non-polar contamination and temperature budget Bonding of III-V epitaxial layers sequential but fast integration process high density of integration, collective processing high quality epitaxial III-V layers

14 Proposed integration process Starting point: Processed SOI-waveguide wafer 193nm or 248nm DUV lithography Fabricated in pilot CMOS-line

15 Proposed integration process Planarization Planarization Using BCB (50nm to 2um) (UGent/IMEC) Using SiO 2 (TRACIT - CEA-LETI)

16 Proposed integration process Die-to-wafer bonding Bonding InP-dies on top of planarized SOI-wafer Low alignment accuracy required Fast pick-and-place place

17 Proposed integration process Substrate removal Remove InP-substrate down to etch stop layer Remove etch stop Thin membrane remains (200nm ~ 2 µm)

18 Proposed integration process Hardmask deposition Micro-disk sources Detectors DBR sources Decontamination ti and hardmask deposition Alignment of waveguides and devices through lithographic methods

19 Proposed integration process Processing of InP-optoelectronic devices Mesa etching and Metallization Waferscale processing!!! on 2cm 2 pieces (UGent, INL) on 200mm wafers (CEA-LETI)

20 III-V/Silicon photonics Bonding of III-V epitaxial i layers Molecular die-to-wafer bonding Based on van der Waals attraction act between ee wafer surfaces Requires atomic contact between both surfaces - very sensitive to particles - very sensitive to roughness Adhesive die-to-wafer bonding - very sensitive to contamination of surfaces Uses an adhesive layer as a glue to stick both surfaces Requirements are more relaxed compared to Molecular - glue compensates for particles (some) - glue compensates for roughness (all) - glue allows (some) contamination of surfaces

21 Bonding Technology Requirements for the adhesive for bonding Optically transparent <0.1dB/cm High thermal stability (post-bonding thermal budget) 400C Low curing temperature (low thermal stress) No outgassing upon curing (void formation) Resistant to all kinds of chemicals 250C OK HCl,H 2 SO 4,H 2 O 2, DVS-BCB satisfies these requirements CH 3 CH 3 Si O Si CH 3 CH 3 1,3-divinyl-1,1,3,3-tetramethyldisiloxane-bisbenzocyclobutene

22 Bonding Technology Cross-sectional image of III-V/Silicon substrate InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack DVS-BCB Si Si WG SiO 2 DVS-BCB 200nm Si SiO 2 200nm 300nm bonding layer routinely and reliably obtained

23 Bonding Technology Cross-sectional image of III-V/Silicon substrate InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack DVS-BCB Si Si WG SiO 2 DVS-BCB 200nm Si SiO 2 200nm 300nm bonding layer routinely and reliably obtained Recently also sub-100nm layers demonstrated

24 III-V silicon heterogeneous integration ti InP/InGaAsP epitaxial layer stack Si WG DVS- BCB SiO 2 200nm 1. Silicon photonics is great!!! 2. But we still need InP 3. III-V silicon integration 4. Devices

25 Integrated Devices: laser diode Integrated t laser diodes d First only pulsed operation due to high thermal resistivity DVS-BCB Integration of a heat sink to improve heat dissipation Continuous wave operation achieved this way

26 Other groups Intel / UCSB Hybrid laser CEA-LETI / III-V Vlab p-type contact 5 µm n-type contact III-V etched facet Output t power (mw) C 15 C 20 C 25 C 30 C 35 C 40 C Voltage (V V) Current (ma) (IPRM 08, paper MoA4.2) 0

27 MSM detectors Etching of detectors in III-V Spinning insulation layer of polyimide Opening contact window Metallization 25µm long detector InGaAs/ InAlAs polyimide R = 1.0A/W (1550nm), IQE = 80% (5V bias) I dark = 3nA (5V bias) contact window SOI waveguides (30µm pitch) L=30µm, d=400nm no absorption 40µm contact window Ti/Au contact IN InGaAs absorption 40µm IN

28 Wavelength selective filter V_bias = -10V 1 ) 1x4 demux, λ=20nm, 280µm x 150µm Photo o current (ma

29 Integrated microdisk laser Microdisk laser design Whispering-gallery modes Central top contact Bottom contact on thin lateral contact layer (t s ) Hole injection through a reverse-biased tunnel-junction bottom contact Si waveguide w Si d ox 2R disk top contact tunnel junction SiO 2 Si substrate active layer InP t s t Microdisk thickness 0.5 < t < 1µm Evanescent coupling to SOI wire waveguide (500x220nm 2 )

30 On-chip optical interconnect? Integrate t photonic interconnect t on CMOS? III-V material microlaser SOI waveguide microdetector SOI Optical Interconnect layer Electrical Interconnect layer Silicon transistor layer Need integrated interconnect layer on top of CMOS Silicon wiring for interconnect III-V microdevices for sources and detectors

31 PICMOS 25 µm A collaborative project InP island SOI waveguide microdisk IMEC: metallization III-V processing TU/e: detector etching IMEC: SOI-wafer fabrication INL: substrate removal INL: source etching SiO 2 BCB InP - InGaAsP TRACIT: planarization Si wire LETI: bonding LETI: hard mask 130-nm bonding layer Si substrate Six cleanrooms but still working devices

32 Output pow wer (µw) Continuous-wave lasing 1-µm thick, µm devices exhibit continuous-wave lasing CW power Pulsed peak power CW Voltage Voltage (V) Spectral pow wer (dbm) mA Current (ma) Wavelength (nm) Threshold current I th = 0.5mA, voltage V th = V BCB slope efficiency = 30µW/mA, up to 10µW InP - InGaAsP (Pulsed regime: up to 100µW peak power) SiO 2 Si wire J. Van Campenhout et al., "Electrically pumped inp-based microdisk lasers Si integrated substrate with a nanophotonic silicon-on-insulator waveguide circuit" Optics intec 2007 Express, nm Photonics May Research 2007 Group - b di

33 Temperature dependence Laser emission up to 70 C (pulsed operation) pow wer [a.u.] D = 6µm T=10 C T=20 C T=30 C T=40 C T=50 C peak wave elength [nm] T=60 C current [ua] T=70 C dλ 86 pmk dt Tamb [ C] dn ( InP) 210 dt dn dt ( BCB) K 3 1 K

34 Fit to experimental data 30 3 Optic cal Power (µw) pulsed data CW data ) Voltage (V Current (ma) Model can be fitted to pulsed experimental data, assuming: uniform injection: injection efficiency =0.36x0.7=0.25 coupling loss = 3cm -1 (simulation) tunnel-junction p-doping N a = 2x10 18 cm -3 (design target N a = 2x10 19 cm -3, SIMS analysis: N a ~ 8x10 18 cm -3 ) fitted scatter loss = 8cm -1 (passive ring resonators: 7-13cm -1 ) Consistent fit, except for tunnel-junction p-doping and saturation effect

35 Ultra-low-power Wavelength conversion tunable laser oscilloscope detector pattern generator polarization controller high-speed detector modulator band-pass filter variable attentuator EDFA polarization controller SOI wg. MDL mod de intensity (db Bm/0.1nm) dominant lasing wavelength of MDL w/o injection with injection λ FSR =32nm injected laser wavelength wavelength (µm) power (a.u.) ns time (ns) No control power needed. Wavelength conversion with only 6.4uW control power. 5Gbps dynamic results.

36 Full Link D Demonstrator t t di die (contains ( t i 256 optical ti l links) li k ) 7mm 264 Micro detectors (TU Ei Eindhoven dh / Cobra) C b ) FIBRE G GRATING C COUPLERS S Point-to--point links s 120 DBR microlasers Broadc cast links s Point-to--point links s FIBRE G GRATING C COUPLERS S 120 Microdisk lasers laser III-V die detector III-V die 9mm 200mm SOI wafer

37 Pulsed operation of the link monitor grating Duty cycle = 8% Period = 1 µs on-chip detector Detector not biased (0V), negligible gbedark current Performance under pulsed operation: Threshold current < 700 µa & Slope efficiency ~ 1.1 µw/ma Detector t efficiency i of f023029a/w A/W.

38 Outlook & conclusion We demonstrated: t d Ultra-dense waveguiding < 2 µm pitch (waveguide-to-waveguide) waveguide) A powerfull III-V on Silicon integration technology Several proof-of-principle of principle demonstrators Electrically pumped micro-disk sources on silicon platform 500 µa threshold current Micro-detectors on silicon platform 1.0A/W Fabrication using waferscale processes

39 Single wavelength Outlook & conclusion We still need to: Multi-wavelength sources Improve source performance Towards 50 µa threshold current 10GHz modulation speed 30% internal efficiency λ Through improved processing λ λ Through improved device design λ Improved high temperature operation Full fabrication in CMOS pilot-line 1 2line λ 1 λ 2 λ 3 N λ λ λ λ λ Integration with CMOS electronic driving circuit Implement WDM-functionality 3 N N λ 1,λ 2... λ N-1,λ N λ 1,λ 2... λ N-1,λ N

40 Multi-wavelength Laser 4-wavelength laser D1 D2 D3 D4 SM fiber grating coupler powe er (db) (a) λ = 23nm FSR biased at: 4mA D2 10µm diameter 7.5µm diameter -10 (b) D1 D4 D3 D2 D1 powe er (db) λ = 32nm FSR biased at: 3mA D2 D1 D4 D3 D2 D wavelength (µm) wavelength (µm)

41 Outlook & conclusion We still need to: Improve source performance Towards 50 µa threshold current 10GHz modulation speed 30% internal efficiency Through improved processing Through improved device design Improved high temperature operation Full fabrication in CMOS pilot-line line Integration with CMOS electronic driving circuit Implement WDM-functionality Simplify overall processing

42 Outlook & conclusion Simplify processing Avoid critical patterning in the III-V layer Silicon racetrack III-V film

43 Acknowledgements Photonics Research Group III-V silicon integration: G. Roelkens, J. Van Campenhout, J. Brouckaert, L. Liu Silicon Processing W. Bogaerts, P. Dumon, S. Selvarajan, R. Baets PICMOS team J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing) C. Lagahe, B. Aspar (TRACIT) (planarization) C. Seassal, P. Rojo-Romeo, P. Regreny, P. Viktorovitch (INL) (processing, epitaxy) R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy)

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45 Fiber-chip coupling Important: 1µm Low loss coupling Large bandwidth Coupling tolerance Fabrication Limited extra processing Tolerant to fabrication SOI wire Low reflection Polarization? Single-mode fiber

46 Coupling to fiber Grating coupler Alternative: Grating couplers Waferscale testing Waferscale packaging High alignment tolerance From Fibre Single mode fiber core shallow fibre coupler 70% efficiency measured deep trench Towards optical circuit

47 Increase effieciency? Top view Improving performance Add bottom mirror grating coupler Apodize Other With mirror Without mirror BCB FIB cross-section 1dB bandwidth > 40nm

48 Main Challenges 1. Coupling of light between III-V and Silicon Option 1: evanescent Guiding in silicon Requires thin bonding layer Requires III-V thinner than <250nm Option 2: other (adiabatic, grating coupler ) Guiding in III-V Thicker III-V layer Sometimes thicker bonding

49 Main Challenges 1. Coupling of light between III-V and Silicon Option 1: evanescent Guiding in silicon Requires thin bonding layer Requires III-V thinner than <250nm Loss at metal contact Option 2: other (adiabatic, grating coupler ) Guiding in III-V Thicker III-V layer Sometimes thicker bonding 2. Electrical injection Metal contact on membrane devices without inducing additional loss 3. Thermal management Overcome thermal barrier of bonding layer and BOX

50 Integrated Devices: laser diode Integrated laser diodes Fabry-Perot laser cavity by etching InP/InGaAsP laser facets Inverted adiabatic taper coupling approach