Acknowledgements. Outline. Outline. III-V Silicon heterogeneous integration for integrated transmitters and receivers. Sources Detectors Bonding

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1 Acknowledgements III-V licon heterogeneous integration for integrated transmitters and receivers Dries Van Thourhout, J. Van Campenhout*, G. Roelkens, J. Brouckaert, R. Baets Ghent University / IMEC, Belgium (*Currently with IBM Research) Passives Sources Detectors Bonding The photonics research group at INTEC/IMEC P. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, F. Vanlaere, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, G. Priem, D. Taillaert, S. Scheerlinck, P. Debackere, S. Selvarajan D. Van Thourhout, P. Bienstman, R. Baets The licon Process division at IMEC Vincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven, Rudi De Ruyter, Johan Mees PICMOS partners J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing) C. Lagahe, B. Aspar (TRACIT) (planarization) C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy) R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy) European Union, Belgian and Flemish government Outline Passive licon Photonics III-V on licon Why? Bonding technology Devices FP-sources, Detectors, micro-disk sources Conclusion Outline Passive licon Photonics III-V on licon Why? Bonding technology Devices FP-sources, Detectors, micro-disk sources Conclusion 1

2 Basic Width structures (500nm) x Height (220nm) Low Lowloss lossbends bends Complex filters 9x16 AWG <0.3dB <0.3dBexcess excessloss lossfor forsplitters splitters 16 channels, 200GHz channel spacing 36 arrayed waveguides O2 (1-2um) 0.1mm2 footprint 5µm FSR 800nm 0 500nm 0.09dB/ dB/ dB/ dB/ Radius [um] µm µm 100µm % 97%transmission transmissionin incrossings crossings wavelength [nm] shallow etch deep etch 2.2dB insertion loss (on-chip) 18dB crosstalk suppression (b) 2µm waveguide Planar concave grating demux Planar concave grating demux top view Without DBR facets: -6.5dB loss With DBR facets: -2.6dB loss O2 0 5µm -5 Transmission (db ) 0.04 transmission [db] Excess bend loss [db/90 ] licon Wavelength (nm) High noise floor (limited bandwidth of fiber couplers) 2

3 Transmission(dB) 30 channel PCG demultiplexer 0 DBR-PCG demux: 3.2nm channel spacing Wavelength(nm) On-chip loss: 2.5dB 6.5dB Crosstalk: -15dB -25dB Channels spacing: 3.2nm Amorphous as waveguide material Low temperature PECVD deposition backend compatible Tunable refractive index and film thickness Highly uniform thickness over the wafer (200mm) 3.0% (46 point measurement) Low loss 3.5dB/cm and 1.4dB/cm for wire (450X220nm) and shallow etched waveguides * Ring resonators with high Q of 20,000 demonstrated Transmitted power [dbm] Wavelength [nm] λ 3dB =0.07nm * S. K. Selvaraja et al in Proc. Conf. ECOC, Berlin, 2007, PDS Fiber - Fiber Transmited power[dbm] Wire loss α = db/cm Photonic wire length [cm] Bulk loss α = db/cm Coupling to fiber Grating coupler Grating couplers Waferscale testing Waferscale packaging High alignment tolerance Results 69% measured / 85% designed Outline Passive licon Photonics III-V on licon Why? How? Bonding technology Devices FP-sources, Detectors, micro-disk sources Conclusion From Fibre ngle mode fiber core Towards optical circuit 3

4 III-V on silicon Why combine silicon with III-V? silicon fall back on CMOS technology high index contrast no emission nor amplification, yet III-V superb emission, amplification and detection full active-passive integration is complex and expensive, still III-V on silicon combine the best of two worlds price: integration technology does it work? can it turn into a manufacturing technology? Introduction There are several ways to integrate III-V on SOI Flip-chip integration of opto-electronic components most rugged technology testing of opto-electronic components in advance slow sequential process (alignment accuracy) low density of integration Hetero-epitaxial growth of III-V on silicon collective process, high density of integration mismatch in lattice constant, CTE, polar/non-polar contamination and temperature budget Bonding of III-V epitaxial layers sequential but fast integration process high density of integration, collective processing high quality epitaxial III-V layers Proposed integration process Starting point: Processed SOI-waveguide wafer Proposed integration process Planarization DUV lithography Fabricated in IMEC pilot CMOS-line Planarization BCB spin-on-layer (IMEC) Or: O 2 -deposition and CMP (Collaboration LETI/TRACIT) 4

5 Proposed integration process Die-to-wafer bonding Proposed integration process Substrate removal Bonding InP-dies on top of planarized SOI-wafer Low alignment accuracy required Fast pick-and-place Remove InP-substrate down to etch stop layer Remove etch stop Thin membrane remains (200nm ~ 2um) Proposed integration process Hardmask deposition Proposed integration process Processing of InP-optoelectronic devices Micro-disk sources Detectors DBR sources Decontamination and hardmask deposition Alignment of waveguides and devices through lithographic methods Mesa etching and Metallization Waferscale processing!!! but on 2cm 2 pieces (for the moment) 5

6 III-V/licon photonics Bonding of III-V epitaxial layers Molecular die-to-wafer bonding Based on van der Waals attraction between wafer surfaces Requires atomic contact between both surfaces - very sensitive to particles - very sensitive to roughness - very sensitive to contamination of surfaces Adhesive die-to-wafer bonding Uses an adhesive layer as a glue to stick both surfaces Requirements are more relaxed compared to Molecular - glue compensates for particles (some) - glue compensates for roughness (all) - glue allows (some) contamination of surfaces While established technology for SOI, III-Vs often do not meet the requirements for molecular bonding Bonding Technology Requirements for the adhesive for bonding Optically transparent High thermal stability (post-bonding thermal budget) 400C Low curing temperature (low thermal stress) 250C No outgassing upon curing (void formation) OK Resistant to all kinds of chemicals HCl,H 2 SO 4,H 2 O 2, DVS-BCB satisfies these requirements CH 3 CH 3 O CH 3 CH 3 1,3-divinyl-1,1,3,3-tetramethyldisiloxane-bisbenzocyclobutene <0.1dB/cm Bonding Technology Bonding Technology Cross-sectional image of III-V/licon substrate InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack DVS-BCB O 2 WG O 2 DVS-BCB 200nm 200nm 300nm bonding layer routinely and reliably obtained 6

7 Bonding Technology Cross-sectional image of III-V/licon substrate InP-InGaAsP epitaxial layer stack DVS-BCB O 2 WG InP/InGaAsP epitaxial layer stack O 2 DVS-BCB 200nm 200nm Outline Passive licon Photonics III-V on licon Why? Bonding technology Devices FP-sources, Detectors, micro-disk sources Conclusion 300nm bonding layer routinely and reliably obtained Recently also sub-100nm layers demonstrated Coupling mechanisms Evanscent coupling Other coupling Integrated Devices: laser diode Integrated laser diodes Fabry-Perot laser cavity by etching InP/InGaAsP laser facets Inverted adiabatic taper coupling approach Guiding in silicon Requires thin bonding layer Requires III-V thinner than <250nm Guiding in III-V Thicker III-V layer Sometimes thicker bonding 7

8 Integrated Devices: laser diode Integrated laser diodes Only pulsed operation due to high thermal resistivity DVS-BCB Integration of a heat sink to improve heat dissipation Continuous wave operation achieved this way Integrated Devices: detectors Integrated photodetectors Vertical incidence p-i-n photodetector Coupling using a diffraction grating Low experimental responsivity (0.02A/W) but due to design Smaller number of processing steps more compact design DVS- BCB layer Oxide buffer layer MSM detectors InGaAs/ InAlAs Measurements I/V polyimide Etching of detectors in III-V Spinning insulation layer of polyimide Opening contact window Metallization SOI waveguides (30µm pitch) contact window L=30µm, d=400nm no absorption 40µm I(A) 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E uW 1.26uW 126nW 12.8nW dark contact window Ti/Au contact IN 1.E V(V) InGaAs absorption 25µm long detector R = 1.0A/W (1550nm), IQE = 80% (5V bias) 40µm IN I dark = 3nA (5V bias) 8

9 PCG with MSM-detectors Integrated with array of MSM-detectors Integrated microdisk laser Microdisk laser design IN OUT Photocurrent (ma) 1 50 µm V_bias = -10V Whispering-gallery modes Central top contact Bottom contact on thin lateral contact layer (t s ) Hole injection through a reverse-biased tunnel-junction bottom contact waveguide Microdisk thickness 0.5 < t < 1µm Evanescent coupling to SOI wire waveguide (500x220nm 2 ) w d ox 2R disk top contact tunnel junction O 2 substrate active layer InP t s t European research programme PICMOS (Photonic Interconnect Layer on CMOS by Waferscale Integration, FP602-IST ) Measurement setup camera BCB InP - InGaAsP ngle-mode fiber O 2 wire substrate 130-nm bonding layer probe needles fiber couplers SM fiber microdisks camera image Output power (µw) Continuous-wave lasing CW power Pulsed peak power CW Voltage 1-µm thick, 7.5-µm devices exhibit continuous-wave lasing Current (ma) Voltage (V) Spectral power (dbm) mA Wavelength (nm) Threshold current I th = 0.5mA, voltage V th = V slope efficiency = 30µW/mA, up to 10µW (Pulsed regime: up to 100µW peak power) J. Van Campenhout et al., "Electrically pumped inp-based microdisk lasers integrated with a nanophotonic silicon-on-insulator waveguide circuit" Optics intec Express, Photonics May Research 2007 Group - 9

10 Full Link Pulsed operation of the link Demonstrator die (contains 256 optical links) Duty cycle = 8% Period = 1 µs monitor grating 7mm 264 Micro detectors (TU Eindhoven / Cobra) FIBRE GRATING COUPLERS Point-to-point links 120 DBR microlasers Broadcast links Point-to-point links FIBRE GRATING COUPLERS 120 Microdisk lasers laser III-V die detector III-V die on-chip detector 9mm 200mm SOI wafer Detector not biased (0V), negligible dark current Performance under pulsed operation: Threshold current < 700 µa & Slope efficiency ~ 1.1 µw/ma Detector efficiency of A/W. CW operation of the link Multi-wavelength Laser Cascaded several (4) microdisks on one bus SOI waveguide with different diameters SM fiber D1 D2 D3 D4 Detector not biased (0V), negligible dark current CW laser performance:threshold current ~ 600 µa & Slope efficiency ~ 1 µw/ma grating coupler Detector efficiency of A/W. Unstable output power above 1.5mA Micro-disk is lasing in two directions Output direction varies in time + as functon of applieed voltage 10

11 power (db) -10 (a) Multi-wavelength Laser λ = FSR biased at: 4mA 10µm diameter 7.5µm diameter -10 (b) λ = 32nm FSR 23nm D2 D1 D2 D1 D3 D4 D3 biased at: D4 3mA -40 D1 D wavelength (µm) power (db) D wavelength (µm) D1 Outline Passive licon Photonics III-V on licon Why? Bonding technology Devices FP-sources, Detectors, micro-disk sources Conclusion Equally distributed laser peaks in one FSR. Low thermal and optical crosstalk (avoid high order mode resonance). Non-uniformity: ~8dB. L. Liu e.a., Compact multiwavelength source based on cascaded microdisks, OFC 2008 Conclusion licon nanophotonic circuits A great platform for passive PIC s Require integration with III-Vs if sources and amplifiers are needed III-V/licon die-to-wafer bonding process Provides a reliable integration process Without compromising epitaxial integrity Waferscale processing compatible BCB adhesive bonding is a manufacturable process High-performance devices demonstrated Micro-disk lasers, FP-lasers, detectors Acknowledgements The photonics research group at INTEC/IMEC P. Dumon, W. Bogaerts, G. Roelkens, J. Van Campenhout, J. Schrauwen, S. Verstuyft, L. Van Landschoot, J. Brouckaert, D. Taillaert, S. Scheerlinck, S. Selvaraja, K. De Vos, D. Van Thourhout, P. Bienstman, R. Baets The licon Process division at IMEC Vincent Wiaux, Stephan Beckx, Johan Wouters, Diziana Vangoidsenhoven, Rudi De Ruyter, Johan Mees PICMOS partners J.M. Fedeli, L. Di Cioccio (LETI) (molecular bonding, processing) C. Lagahe, B. Aspar (TRACIT) (planarization) C. Seassal, P. Rojo-Romeo, P. Regreny (CNRS-Lyon) (processing, epitaxy) R. Notzel, X.J.M. Leijtens (TU/e) (epitaxy) epixnet licon Photonics Platform (IMEC+LETI) for organizing MPW runs on a a cost-sharing basis Also for you! See See for presentation and papers 11

12 Integration with CMOS Next step: integrate photonic interconnect on CMOS III-V material microlaser SOI waveguide microdetector Polarization diversity 2D-grating PDL measurement SOI Optical Interconnect layer Electrical Interconnect layer licon transistor layer detector Through wafer-to-wafer bonding Or: Above IC processing using amorphous silicon 12