A Review of Low-Power and High-Density System LSI

Transcription

1 MEMOIRS OF SHONAN INSTITUTE OF TECHNOLOGY Vol. 41, No. 1, 2007 LSI * A Review of Low-Power and High-Density System LSI Shigeyoshi WATANABE* Low-power design of system LSI in the presence of leakage current has been described. And also the novel design technique for realizing high density system LSI featured by the 3-dimensional transistor has been presented. By using parallel processing architecture the active power of embedded processor with the sub-threshold leakage current can be reduced to 1/2 for 2 parallel, 1/5 for 3 parallel case. The dual-supply voltage scheme enables to reduce the active power of embedded processor with the gate leakage current to 35 50%. By using FinFET the pattern area of system LSI can be reduced to 35 50% without sacrificing the performance. These technologies are promising candidates for realizing the breakthrough the 3-limitation of system LSI, power dissipation, scaling of MOS transistor and time to market of system LSI. 1 LSI ) LSI LSI DVD LSI 1 LSI LSI MOS Metal Oxide Semiconductor 1 MOS MOS * ) MOS LSI 3 4 3) LSI 2 2 4) 3 LSI 3 Cell 5) 4 GHz GFlops 6,7) 90 nm CMOS 2 MOS MOS 1 LSI LSI 3 8,9,10) 3 53

2 (%) LSI TI DSP NAND LSI ST LSI LSI LSI LSI AMD Spansion NEC LSI LSI 3 LSI 3 4 LSI MOS MOS LSI LSI PC 11) 2 LSI MOS Metal Oxide Semiconductor MOSFET 3 12) LSI 54

3 LSI L, W, Tox 1/S S 1/S 1 1/S 1/S 1 1/S 2 S 2 1/S 3 Cell (PowerPC 8 SPE s) Power PC 8SPE 4 GHz 256 GFlops 90 nm CMOS SOl 221 mm V 2 LSI 3 LSI LSI MOS LSI 1 MOS 6 58% 21% 13) 1 MOS 3 LSI LSI MOS 4 14) 15) 16) 17) 2 18) 2 LSI MOS 55

4 LSI 6 7 MOSFET MOS 7 MOS MOS MOS 19) MOS MOS MOS 3.1 MOS 20) 70 nm 50 nm 50 mm 2 24 M 0.25 um 21)

5 LSI 0.25 mm 0.07 mm 70 nm 50 mm 2 50 mm 2 3M 24 M 0.18 mm 0.05 mm 50 nm f 250 MHz 1 GHz V cc 1.8 V 0.5 V 3.6 mm 1.6 nm GHz GHz, 3 GHz N MOS 2 GHz GHz (V H ) (V L ) MOS 50 nm MOS 4 GHz 22) (V L /V H ) (V L /V H

6 41 1 V L /V H % 52% V L /V H % 34% V L /V H V L /V H 4 3 MOSFET ) 24) FinFET Fin type Field Effect Transistor TIS 25) SGT Surrounding Gate Transistor 4 26) FinFET/TIS SGT

7 LSI 14 4NAND FinFET/TIS MOS SGT 3 4 NAND 14 3 LSI 27,28) FinFET/TIS 29) 15 FinFET/TIS 4.1 FinFET LSI 15 FinFET FinFET 59

8 FinFET W P D W P 2D FinFET LSI D LSI 30) FinFET D 17 FinFET FinFET D 2 35% D Fin- FET ASIC 35% 50% FinFET LSI FinFET 3 18 FinFET FinFET 31,32) FinFET FinFET MOS 5 LSI 3 3 FinFET MOS % 2 MOS 35 50% 3 FinFET LSI 35 50% LSI C LSI VHDL HDL 60

9 LSI Hardware Description Language VHDL C C VHDL HDL LSI 1) 2) R. Dennard et al., Design of Ion-Implanted MOSFETS with very small physical dimensions, IEEE JSSC, vol. SC-9, pp , ) Moore s Law, mooreslaw.htm 4) vol. 81, no. 11, pp , ) Cell STARC 2005 pp , ) D. Pham et al., The design and implementation of a first-generation Cell processor, ISSCC Dig. Tech. Papers, pp , ) D. Pham et al., Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor, IEEE JSSC, vol. 41, no. 1, pp , ) International Technology Roadmap for Semicondoctors, 2003 edition. 9) SEMATIC Road Map. 10) STARC ) J. Rabaey and M. Pedram, Low power design methodologies, Kluwer Academic, ) T. Sakurai and R. A. Newton., Alpha-power law MOS- FET model and its application to CMOS inverter and other formulas, IEEE JSSC, vol. 25, no. 4, pp , ) K. Kanda et al., Design impact of positive temperature dependence on drain current in sub-1-v CMOS LSIs, IEEE JSSC vol. 36, no. 10, pp , ) A. Chandrakasan, S. Sheng and R. Broderson, Lowpower CMOS digital design, IEEE JSSC vol. 27, no. 4, pp , ) LSI ) G. Almasi and A. Gottlieb, Highly parallel computing, Benjamin/Cummings, ) K. Usami et al., Proc. CICC, pp , ) M. Pedram and J. Rabaey, Low power design methodologies, Kluwer Academic, ) S. Lo et al., IEEE Trans. EDL. vol. 18, no. 5, pp , ), MOSFET LSI C, vol. J86-C, no. 9, pp , ), MOSFET LSI 68 3A , ), MOSFET 2 C, vol. J86-C, no. 6, pp , ) S. Watanabe, Impact of three-dimentional transistor on the pattern area reduction for ULSI, IEEE Trans. Electron Devices, vol. 50, no. 10, pp , ) K. Guarini et al., Triple-self-aligned, planar double-gate MOSFETs: Devices and Circuit, in IEDM Tech. Dig., pp , ) K. Hieda, F. Horiguchi, H. Watanabe, K. Sunouchi, and H. Hamamoto, Effects of a new trench-isolated transistor using side wall gates, IEEE Trans. Electron Devices, vol. 36, no. 9 pp , ) H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi and F. Masuoka, Impact of SGT for ultra-high-density LSIs, IEEE Trans. Electron Devices, vol. 38, no. 5, pp , ) S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka and H. Hara, A novel circuit technology with Surrounding Gate Transistors (SGTs) for ultra high density DRAMs, IEEE Journal of Solid-State Circuits, vol. 30, no. 9 pp , ) TIS DRAM C, vol. J86-C, no. 3, pp , ) TIS LSI C, vol. J88-C, no. 12, pp , ) H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, D. Nguyen and F. Hatori, A single-chip CMOS bluetooth transceiver with 1.5 MHz IF and direct modulation transmitter, ISSCC Dig. Tech. Papers, pp , ) L. Chang, M. Ieong and M. Yang, CMOS circuit performance enhancement by surface orientation optimization, IEEE Trans. Electron Devices, vol. 51, no. 10, pp , ) T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai and S. Takagi, (110)-surface strained-soi CMOS device, IEEE Trans. Electron Devices, vol. 52, no. 3, pp ,