Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)

Transcription

1 Jpn. J. Appl. Phys. Vol. 4 (21) pp Part 1, No. 4B, April 21 c 21 The Japan Society of Applied Physics Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS) Toshiro HIRAMOTO 1,2,, Makoto TAKAMIYA 1, Hiroshi KOURA 1, Takashi INUKAI 1, Hiroyuki GOMYO 1, Hiroshi KAWAGUCHI 1 and Takayasu SAKURAI 1,3 1 Institute of Industrial Science, the University of Tokyo, Komaba, Meguro-ku, Tokyo , Japan 2 VLSI Design and Education Center, the University of Tokyo, Hongo, Bunkyo-ku, Tokyo , Japan 3 Center for Collaborative Research, the University of Tokyo, Komaba, Meguro-ku, Tokyo , Japan (Received September 19, 2; accepted for publication December 13, 2) The optimum device parameters of variable threshold voltage complementary metal oxide semiconductor (VTCMOS) have been investigated by means of device simulation and its scalability has been discussed. The optimum body effect factor depends on the relationship between the substrate bias and the supply voltage. It is shown that the VTCMOS scheme aiming at extremely low stand-by power will fail as the device size and the supply voltage are scaled. The advantage of VTCMOS will be its high speed, and the VTCMOS will be essential in high-speed circuits operating at a low supply voltage in combination with another low stand-by power scheme such as the insertion of leak cut-off switches. KEYWORDS: variable threshold voltage complementary metal oxide semiconductor (VTCMOS), body effect factor, substrate bias, lowpower, high-speed, scalability, metal oxide semiconductor fieldeffect transistor (MOSFET) 1. Introduction Strong demands for high-speed and low-power very large scale integrations (VLSIs) are rapidly growing for portable product applications. It is well known that there is a severe trade-off between high-speed and low-power in metal-oxidesemiconductor field-effect transistors (MOSFETs). In order to suppress the active power, the supply voltage (V dd ) should be suppressed. The threshold voltage (V th ) should also be reduced to maintain the high speed. Then, the stand-by power will increase exponentially due to the increased subthreshold current. One of the solutions to this problem is the variable threshold voltage complementary metal oxide semiconductor (VTCMOS) scheme. 1 3) In the VTCMOS scheme, V th of MOSFETs is controlled by substrate bias (V bs ) using the body effect. V th is set to a high value in the stand-by mode and is set to a low value in the active mode to attain high speed and low stand-by power at the same time. The characteristics of VTCMOS are strongly related to the V th shift ( V th ), which depends on the body effect factor γ and the substrate bias change V bs. Therefore, γ and V bs are the most important device parameters in VTCMOS. However, the optimum device design for VTCMOS has not been generally recognized and the scalability of VTCMOS is an issue of great concern for future applications. In this study, the optimum device design for VTCMOS is systematically investigated by device simulation and the scalability of VTCMOS is discussed. It is suggested that, while VTCMOS aiming at ultra-low stand-by current does not maintain its advantage as the device and the supply voltage are scaled, VTCMOS will be an essential device/circuit scheme aiming at high-speed applications. 2. Optimum Device Parameters 2.1 Definition of body effect factor 4, 5) In this study, the body effect factor γ is defined by γ V th V bs, (1) instead of the usual definition in device textbooks which is applicable only to the MOSFET with uniformly doped channel profile. The definition of eq. (1) can be applied to all MOS structures with any channel impurity profile, including retrograde MOSFET, delta-doped MOSFET, counter-doped MOSFET, and silicon-on-insulator (SOI) MOSFET. Then, the threshold voltage shift V th is given by V th = γ V bs, (2) and is directly related to the body effect factor and substrate bias change. Therefore, a larger body effect factor results in a larger threshold voltage shift. On the other hand, the subthreshold factor S is also related to γ, and a MOSFET with a larger body effect factor has a degraded subthreshold 4, 5) swing. Therefore, these two effects would determine the optimum condition of γ once V bs is determined. 2.2 Two modes in VTCMOS The main target of VTCMOS has been considered as the reduction of the stand-by off-current (I off ) while maintaining the circuit speed. Figure 1 illustrates the characteristics of VTCMOS aiming at a low stand-by current. While maintaining a high drive current by low threshold voltage in the active mode, the substrate bias is changed in the negative direction to raise the threshold voltage resulting in the decrease in the subthreshold current at stand-by mode. We call this configuration the low-power mode. In addition, there is another advantage of VTCMOS: speed enhancement. When the stand-by current is fixed, the on-current (I on ) can be largely enhanced by the body effect in VTCMOS. This configuration is illustrated in Fig. 1. In the active mode, the substrate bias is changed in the positive direction to reduce the threshold voltage resulting in the enhancement of on-current. This is called the high-speed mode. Therefore, VTCMOS has two modes with different objectives. 2.3 Simulation results In order to investigate the VTCMOS performances in the two modes, two-dimensional device simulation 6) was per- address: hiramoto@nano.iis.u-tokyo.ac.jp 2854

2 Jpn. J. Appl. Phys. Vol. 4 (21) Pt. 1, No. 4B T. HIRAMOTO et al log I ds log I ds active acti ve V th = V bs stand-by stand-by V dd V th = V bs V dd V gs V gs Fig. 1. Schematics of VTCMOS characteristics in the two modes. Low-power mode where I off is reduced while maintaining I on. I off in the stand-by mode ( ) is suppressed compared with that in the active mode ( ) using body effect. V bs in the active mode (V bs,active )isv in this study. High-speed mode where I on is enhanced while maintaining I off. I on in the active mode ( ) can be enhanced compared with that in stand-by mode ( ). formed assuming uniformly doped, delta-doped, and counter doped MOSFETs. 5) The device parameters are based on the International Technology Roadmap for Semiconductors (ITRS). 7) Figure 2 shows the dependences of VTCMOS characteristics on γ and V bs at the 18 nm technology node. The supply voltage is 1.8 V. The characteristics of the lowpower mode are shown in Fig. 2 where the on-current is fixed and the stand-by off-current is derived as a function of γ and V bs. The high-speed mode is shown in Fig. 2 where the off-current is fixed and on-current is derived as a function of γ and V bs. In the devices with V bs = V, which are normal MOS- FETs, the stand-by off-current increases (Fig. 2) or the active on-current decreases (Fig. 2) as γ increases, because subthreshold factor S is degraded. However, by applying V bs, lower stand-by off-current or higher active on-current can be achieved. It is suggested in both modes that V bs should be set as large as the junction leakage permits. It is also shown that when the values of γ and V th can be designed at a fixed V bs, the optimum γ depends on the relationship between a certain voltage V o and V bs, where V o is about 5 7% of the supply voltage V dd. 5) As shown in Figs. 2 and 2, Ioff,standby(A/ m) Ion,active A/ m) V V V 1.5 V Vbs =5V 3V 12 2V V 9 Tech. Node: 18 nm =1mA/ m (const.) Vbs =V.3 V.5 V.7 V 1.2 V 1V.7 V 7.5 V 6 Tech. Node: 18 nm I V off,standby =.1pA m(const.).3 V Fig. 2. VTCMOS characteristics as a function of γ and V bs at the 18 nm technology node. Low-power mode. is fixed at a constant value (1 ma/µm). V bs,active = V. There is a critical voltage V o, where the optimum γ changes. V o is about.7 1. V in this case. When V bs is larger than V o, a device with larger γ gives smaller, which is similar to the result in the high-speed mode. High-speed mode. is fixed at a constant value (.1 pa/µm). V bs,active = V in this case. When V bs is smaller than V o, a device with smaller γ gives larger than that with larger γ. In contrast, when V bs is larger than V o, a device with larger γ gives larger although also increases. smaller off-current and larger on-current can be attained in a device with larger γ when V bs is larger than V o (about.7 1 V in both modes) in the low-power mode and in the high-speed mode, respectively. V o is an important parameter in VTCMOS. VTCMOS can take full advantage when applied V bs is larger than V o. At the 18 nm technology node, V dd is sufficiently high. Therefore, both low-power mode and high-speed mode are applicable. The optimum guidelines for γ and V bs are the same for both the modes. 3. Scalability of VTCMOS 3.1 Scaling scenarios In this section, the scalability of VTCMOS is discussed. When the device size and V dd are scaled, the VTCMOS characteristics significantly differ from those of the 18 nm technology node. Three scaling scenarios are assumed and discussed in the following subsections. The scaling scenarios assumed are summarized in Fig. 3. In all Scenarios, is set constant (75 µa/µm) with V bs,active = V. Consequently, rapidly increases as technology advances. Scenario A is based on the low-power mode. In order to attain extremely low stand-by power, the low off-current of.1 pa/µm is targeted. Scenarios B and C are based on the high-speed mode. In Scenario B, the reduction ratio of offcurrent is set to a constant value of two orders of magnitude,

3 2856 Jpn. J. Appl. Phys. Vol. 4 (21) Pt. 1, No. 4B T. HIRAMOTO et al Scenari o A =.1pA/ m (const.) (18 nm) (13 nm) (1 nm) (7 nm) (5 nm) (35 nm) Scenario B / =.1 (const.) (18 nm) (13 nm) (1 nm) (7 nm) (5 nm) (35 nm) I on / I on = 2% (const. ) Ioff,active (18 nm) (13 nm) (1 nm) (7 nm) (5 nm) (35 nm) (c) Fig. 3. Three scaling scenarios of VTCMOS. Scenario A: is constant (=.1 pa/µm) (low-power mode). Scenario B: / is constant (=.1) (high-speed mode). (c) Scenario C: current enhancement I on /I on is constant (=.2) (high-speed mode). is set to 75 µa/µm and V bs,active = V in all cases. Uniformly doped MOSFETs are assumed. Device parameters at each technology node are based on ITRS. The simulation results ( in Scenarios A and B, and in ) derived under the assumption in each Scenario are also shown by a broken line. in which the threshold voltage shift V th is roughly constant. In, the enhancement ratio of on-current is set to a constant value of 2%. The required V th and V bs are simulated at each technology node, assuming uniformly doped channel MOSFETs. MOSFETs with a constant value of γ (γ =.2) are also assumed when the required V bs is discussed. 3.2 Low-power mode In the battery-operated portable system, the stand-by current required is less than.1 pa/µm. Then, V th in the stand-by mode should be higher than.5 V. The low-power mode of VTCMOS aims at this kind of low stand-by current. Figures 4 and 5 show the required V th and V bs at each technology node. In Scenario A, V th becomes larger as V dd is scaled, Vth(V) Scenario A Scenario B (18 nm) (13 nm) (1 nm) (7 nm) (5 nm) (35 nm) Fig. 4. Relationship between V dd and V th. V th rapidly increases in Scenario A. V th is roughly constant in Scenario B. V th decreases in proportion to V dd in. Required Vbs (V) Scenario A Scenario B Constant ( =.2) (18 nm) (13 nm) (1 nm) Year (7 nm) (5 nm) (Technology Node) Vdd(V) (35 nm) Fig. 5. Required V bs in three scenarios at each technology node. Broken lines show the simulation results for uniformly doped MOSFETs, where γ decreases as the device is scaled. Solid lines show devices with a constant body effect factor (γ =.2), which roughly corresponds to constant short channel effect. Even in the latter case, Scenarios A and B will fail due to large V bs compared with V dd. and V bs increases rapidly and would exceed breakdown voltage. Therefore, the scaling scenario of low-power mode will fail in the future. One of the reasons for this failure is the reduction of the body effect factor in the uniformly doped channel MOSFETs 5) as the device is scaled. When γ is degraded, the short channel effect immunity is also degraded. 4) In the ideal device scaling, γ should be kept constant in order to suppress the short channel effect. Therefore, a channel engineered MOSFET with a larger γ is strongly required in normal MOSFETs as well as in VTCMOS in the future. 5) However, even when γ can be kept constant (.2), the required V bs will increase due to the increase of V th, as shown in Fig. 5, and Scenario A will fail. 3.3 High-speed mode The high-speed mode of VTCMOS gives up the suppression of off-current but aims at a high on-current in the active mode. Scenario B has almost constant V th and Scenarios C has V th proportional to V dd, as shown in Fig. 4. Since the enhancement of on-current is roughly determined by V th /V dd, Scenario B has a rapidly growing enhancement ratio and Scenario C maintains a constant enhancement ratio of on-current. However, the required V bs should be also scaled with V dd, considering the breakdown voltage. Therefore, Scenario B will fail due to constant V bs, as shown in Fig. 5, even when γ can be kept constant (.2). On the other hand, in

4 Jpn. J. Appl. Phys. Vol. 4 (21) Pt. 1, No. 4B T. HIRAMOTO et al Ion,enhance( A/ m) I off,enhance(a/ m) V.5 V.4 V.3 V.2 V.1 V 2 Tech. Node: 35 nm Vbs= V Ioff,normal = 16 na/ m Tech. Node: 35 nm I off,normal = 16 na/ m.6 V.5 V.4 V.3 V.2 V.1 V Vbs= V Fig. 6. VTCMOS characteristics in the high-speed mode as a function of γ and V bs at the 35 nm technology node. Here, the two modes are denoted by enhancement and normal modes, instead of active and stand-by modes. Positive V bs is applied in the enhancement mode and V bs in the normal mode (V bs,normal ) is set to V. I off in the normal mode (I off,normal ) is fixed at 16 na/µm. When V bs is sufficiently large compared with V o (V o is about.2 V in this case), I on in the enhancement mode (I on,enhance ) increases markedly, although I off,enhance also increases., since the required V th decreases, the explosion of the required V bs in the uniformly doped channel MOS- FETs is greatly suppressed. Furthermore, the required V bs in a MOSFET with constant γ decreases in proportion to V dd as the device is scaled. Considering the scaling of breakdown voltage, with a channel engineered MOSFET will maintain the advantage of VTCMOS. The above results suggest that will be the only way in which the VTCMOS can survive as device and supply voltage are scaled. It is also suggested that γ should be kept at a high value by utilizing a steep channel profile. Although the stand-by off-current cannot be suppressed, VTCMOS can enhance the circuit speed and the enhancement ratio of the speed can be maintained even if the device is scaled. 4. Device/circuit Scheme in the Future Figure 6 shows the dependences of VTCMOS characteristics on γ and V bs at the 35 nm technology node in Scenario C. The supply voltage is assumed to be.4 V. In the highspeed mode, stand-by and active are not suitable mode names. We rename the modes as normal and enhancement modes, respectively. To reduce the junction leakage current by back-bias, V bs is V in the normal mode and the positive V bs is applied in enhancement mode. 8, 9) The positive V bs will become highly effective when V dd is scaled down to VDD GNDV GND VTCMOS circuits - high speed Leak cut-off Switch (BGMOS,SCCMOS) -highv th - thick T ox Fig. 7. A device/circuit scheme in the future, where the high-speed VTC- MOS and a leak cut-off switch such as BGMOS 1) or SCCMOS 11) are combined. VTCMOS enhances I on and leak cut-off switch reduces I off. lower than.6 V. Forwarded pn-junction current is negligible because it flows in the enhancement mode. The highspeed mode can attain high on-current in the enhancement mode when γ is high and applied V bs is larger than V o, which is about.2 V in the present case. Although the offcurrent is also enhanced in the enhancement mode as shown in Fig. 6, the off-current can be reduced in the normal mode by switching V th. However, in the high-speed mode (), the standby power will be huge even in the normal mode. We certainly need another method to suppress the stand-by current. Figure 7 shows a schematic of the device/circuit scheme where high-speed mode VTCMOS is combined with a leak cut-off switch such as boosted gate MOS (BGMOS) 1) and super cutoff CMOS (SCCMOS). 11) The high-speed VTCMOS in combination with a low stand-by scheme would be one of the most promising device/circuit schemes that can attain high-speed and low stand-by power at the same time in the future. 5. Conclusions The optimum device parameters and scalability of VTC- MOS are discussed. The optimum body effect factor depends on the relationship between the substrate bias and the supply voltage. Although the scaling scenario of low stand-by power VTCMOS will fail, high-speed VTCMOS will take advantage in the combination with another low stand-by scheme. Acknowledgements This work was partly supported by the Japan Society for the Promotion of Science (JSPS) Research for the Future Program. 1) T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu and T. Sakurai: IEEE J. Solid-State Circuits 31 (1996) ) Y. Oowaki, M. Noguchi, S. Takagi, D. Takashima, M. Ono, Y. Matsunaga, K. Sunouchi, H. Kawaguchiya, S. Matsuda, M. Kamoshida, T. Fuse, S. Watanabe, A. Toriumi, S. Manabe and A. Hojo: ISSCC Dig. Tech. Papers (1998) p ) H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda and K. Uchiyama: ISSCC Dig. Tech. Papers (1999) p ) T. Hiramoto and M. Takamiya: IEICE Trans. Electronics, E83-C (2) 161.

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