CHAPTER 2 LITERATURE REVIEW

Transcription

1 8 CHAPTER 2 LITERATURE REVIEW 2.1. INTRODUCTION In order to meet the need for low Off current while keeping power consumption under control, the semiconductor industry is working to introduce high-k gate dielectrics in double gate transistor manufacturing process. The fundamental device parameters for different dielectric material in the Double gate MOSFET (FinFET), Gate Engineered MOSFET and Channel Engineered MOSFET devices are discussed in this thesis. Also a detailed discussion has been made in the device level parameters and the circuit level implementations in this thesis. Unlike conventional SiO 2 dielectric, where electronic polarization plays a major role in determining the dielectric constant, the most important contribution to the value of the dielectric constant materials come from the dipole movement generated by appropriate ion displacements. The features of the high-k materials present serious challenges for their integration into the mainstream transistor manufacturing process. In summary, the presence of the transition metals, which facilitate high-k dielectric materials, is also responsible for intrinsic material limitations. Many issues with high-k dielectric materials are thus related to intrinsic fundamental properties. Successful integration of high-k materials must limit these undesirable features while retaining the material advantages. Here different gate oxide high-k dielectric materials are replaced in DG MOSFETs instead of conventional SiO 2 dielectric material and the various low power related parameter for future cutting edge technology is analysed in nano regime. This chapter presents a detailed discussion on the background works carried out in the above mentioned areas.

2 NANO SIZE HIGH K DIELECTRIC Scaling Limits for Current Gate Dielectrics Now days, the world is becoming smaller by the move clearly states that the dimensions of the transistors would be compressed to twice the number of transistors in every 18 months (Moore 1965; Huff et al 2003). The 2010 ITRS (International Technology Roadmap for Semiconductor) update clearly explained that we are progressing towards high-k dielectric materials that will soon replace the SiO 2 in the MOSFET. The ITRS (2003 Edition), states that dielectric has emerged as one of the most difficult challenges for future device in the device modelling. So here we have made an attempt to find the alternative dielectric material for MOSFET. Indeed, the conventional gate dielectric SiO 2 obviously cannot survive the challenge of an EOT (Effective Oxide Thickness) = 1 nm. Also no manufacturable solution has yet been found to fabricate the SiO 2 thickness, as projected by the ITRS. So it is highly preferable that materials with high dielectric constants and lesser physical thicknesses will be used for MOSFET devices (Hasanur et al 2008). A figure of merit to judge a gate oxide high-k dielectric material layer is the equivalent oxide thickness (EOT), defined as, EOT= (k SiO2 / k high k ) d high-k (Hubbard et al 1996) (2.1) According to Equation (2.1), if a dielectric material with a higher dielectric constant material can replace SiO 2 (k = 3.9), the dielectric layer thickness can be increased proportionally while retaining the same capacitance C ox.

3 10 Figure 2.1 ITRS Roadmap. The EOT shows the effective oxide thickness of the high-k dielectric material layer to SiO 2 when the capacitance is the same. Since a thicker layer is used for insulating, the tunnelling current can be drastically reduced in this thickness regime. However, before a new high-k material can be integrated into the present ULSI (Ultra large scale integration) process flow, many requirements have to be met first (Hori 1997; ITRS 2010). One of the most crucial elements that allow the successful scaling is certainly the outstanding material and electrical properties of SiO 2 (Hori et al 1997; Huff et al 2003). First, it can be thermally grown on Si with excellent control of thickness and uniformity, which forms a very stable interface on the Si substrate with a low defect density. SiO 2 is thermally very stable up to 1000 C, which is required for the MOSFET fabrication. The band gap of SiO 2 is large, i.e., ~9 ev, with sufficiently large conduction and valence band offsets. The dielectric breakdown field of SiO 2 is ~ 13 MV/cm. In addition, SiO 2 is water insoluble, which facilitates photolithography. The use of a polysilicon (Poly-Si) gate electrode in the self-aligned CMOS technology was also a

4 11 determining factor in the scaling. However, as technology evolves, SiO 2 will soon reach its physical limitation such as high Off current and reliability concerns (ITRS 2010). Continuing scaling down of the MOSFET device with the minimum feature size of 90 nm and below would require EOT (equivalent oxide thickness) of less than 15 Å. A Å thick SiO 2 layer corresponds to around 3 4 mono layers of SiO 2. In this thinner EOT range, SiO 2 suffers from high Off current and is very difficult for low power applications (Mario Lanza et al 2011). So the next alternative high-k dielectric material for future CMOS technology is proposed with evidence Aluminium Oxide (Al 2 O 3 ) Aluminium oxide (Al 2 O 3 ) has the potential to be used for future generation devices due to its special physical and chemical properties. Al 2 O 3 has a dielectric value of ~8, a large band gap of about 8.8 ev and elevated Aluminium crystallization temperature (Xeng Yang et al 2010). It has thermal stability as well as high-barrier offset in nature. Al 2 O 3 is also an alternative for conventional gate dielectric material because of its high crystallisation temperature, so it is compatible with conventional process of integrating complementary MOS devices, which involves high temperatures above 1000 C. Thermal degradation is not observed for ultrahigh vacuum (UHV) annealing at temperatures as high as 900 o C. Al 2 O 3 exhibits gate leakage much lower than that of conventional SiO 2 of effective oxide thickness (capacitance) and also provides good interface quality (Bouazra et al 2008). But the drawback of Al 2 O 3 is that it has bad wafer-leakage uniformity compared to Zirconium-di-oxide (Berthelot et al 2006) Titanium-Di-Oxide (TiO 2 ) TiO 2 is considered as the alternative gate dielectric for SiO 2. Even though the electronic band gap of this material is relatively small (3.5 ev), its dielectric constant can be varied from 40 to 110. Depending on the growth process, TiO 2 presents two important phases, Anatase and Retile. The last phase is the thermally

5 12 stable phase that presents the higher dielectric constant, approximately 80; Anatase is a thermally unstable phase with lower dielectric constant transforming in Retile phase at temperatures over 600 C (Albertin et al 2007). Though TiO 2 has a very high dielectric constant, it has bad thermo dynamical stability with silicon and large band gap so it is not preferred in devices (Hubbard et al 1997) Hafnium-Di-Oxide (HfO 2 ) HfO 2 can be considered as the most promising dielectric oxide material to replace SiO 2 gate dielectric because it is thermodynamically more stable on Si than any other high-k materials. HfO 2 devices have demonstrated many orders of magnitude reduction in gate leakage with an EOT of around 1.0 nm for cutting edge transistors. HfO 2 shows superior properties due to its higher high-k material value 2 is smaller than Al 2 O 3, both Conduction Band Offset and Valence Band Offset are already larger than 2 ev for HfO 2 with respect to Ge (Yanzhen Wang et al 2011). And also the nano size material synthesis is difficult in HfO Selection of Zirconium as High-k Materials There have been many review papers, books, and industry consensus that proposed a criterion for choosing alternative high-k materials for different applications (Almeida et al 2003; Wilk et al 2001; Robertson et al 2001; Manchanda et al 2001 ; Houssa et al 2004 ; Huf et al 2003). Zirconium is the most appropriate metal oxide since it is thermodynamically stable with SiO 2 (Subramanian et al 2011). Thermally Stable high-k dielectric material is mainly ZrO 2, since it has a dielectric value of 25, a large energy band gap, (With values reported from 5.16 ev to 7.8 ev) (Balog et al 1977; Balazs et al 1998). The TEM microphotograph of nano crystalline ZrO 2 particles prepared by hydrothermal method is shown in Figure 2.2.

6 13 Figure 2.2 TEM(Tunneling Electron Microscopic) microphotograph of nano crystalline ZrO 2 particles In addition to its high-k dielectric material, ZrO 2 films have shown to be stable with respect to reaction with substrate (or over layer) silicon to temperatures as high as 900 O C (Copel et al 2000). This is an important property because some processing steps after gate dielectric deposition can reach temperatures as high as 1000 O C. The nano size particle can be synthesised for ZrO 2 in MOS fabrication, considering the fact that the nano sized ZrO 2 is the best alternate for SiO 2 in future MOS technology Comparison of High-k materials The different high-k dielectric materials and their properties are discussed here in Table 2.1 (Manchanda et al 2001; Hubbard et al 1996; Robertson et al 2002).

7 14 Table 2.1 List of Key parameters of selected gate oxide dielectric materials. Sl. No Dielectric material Dielectric Constant (k) Band Gap (Eg, in ev) Electron Offset ( Be, in ev) Hole Offset ( Bp, in ev) Breakdown Field (EBD, in MV/cm) 1 SiO Al 2 O TiO ZrO HfO Though TiO 2 has better dielectric constant, it is not used as the dielectric material because its band gap is very low. This may lead to more Off current in the MOS transistor. HfO 2 cannot be used because of the difficulty in synthesising nano sized material. Hence zirconium-di-oxide is the best alternative for silicon-di-oxide in the future semiconductor industry LIMITATIONS OF CMOS TECHNOLOGY Since, 1970s people have been predicting the end of Complementary Metal Oxide Semiconductor (Moore 2003). Despite these predictions, the monetary benefit of growth has driven massive research, which has overcome all previous barriers (Scott et al 2003). However, many experts claim that the industry is

8 15 reaching limits that no amount of past research can push past scaling. The scaling of CMOS has resulted in a strong improvement of the RF performance of MOS devices (Woerlee et al 2001). Consequently, CMOS has become a viable option for analog RF applications and RF system-on-chip. With the features of the devices scaling down, many effects including short channel effect, high electric field effect, quantum effects, parasitic effects, and characteristics fluctuation are becoming more and more serious issues in the semiconductor industry. These will lead to severe degrading of Off current, sub threshold slopes and On-state current of the device (Chun-Jen Weng et al 2009) power consumption will be seriously influenced. Besides, the scaling down methodology also faces constraints from structures, materials, operating mechanisms, etc. Under such circumstances, the traditional bulk silicon CMOS technology will no longer be applicable. The device structures, material selection, fabrication technology and device operating mechanism are used to improve device performances to solve problems existing in power, integration density, property optimization and process in semiconductor industry (Tian et al 2005). There are three key factors limiting continued scaling in CMOS: Minimum dimensions that can be fabricated Diminishing returns in switching performance Off-state leakage So far the primary limitations to chip scaling have been lithographic issues. Continuing advances have pushed current lithographic technologies down to using ultraviolet wavelengths (193 nm). And research is being done to reduce the minimum wavelength into the extreme ultraviolet spectrum (13 nm wavelengths) (Nowak et al 2002). However, transistor dimensions are approaching a hard and that limit is the size of the molecule. Clearly devices cannot be fabricated smaller than the dimension of a single molecule and some dimensions will need to be more than a molecule wide. It should also be pointed out here that lithographic equipment costs have also grown exponentially (Theis et al 2003), and this is beginning to limit the profitability of increased scaling. Thus there is a rapidly approaching limit

9 16 to how small transistors can actually be fabricated. MOS transistors may, never reach single molecule gate length. As mentioned earlier, physical systems cannot run to infinity, generally this means that as a model approaches infinity some nonideal effect will begin to dominate and break the model. This is certainly the case for MOS transistors. So scaling of device all the way down to the molecular level in traditional silicon may not produce devices that are significantly better than their larger transistors. The dominant non-ideal effect that must be addressed for current scaling to continue is off-state power consumption. Within digital logic, the sources that contribute to off-state power consumption are: junction leakage, gate induced drain leakage, sub-threshold channel current, and gate tunnel currents. These factors become more and more significant as the dimensions decrease. In fact, Off currents grow exponentially as gate length decreases in the device (Ning et al 2002). Extrapolating current power trends, the off-state power consumption due to Off current would be about equal active power around the 10 nm node. However, in practical terms, off-state power needs to be less than 10% to 20% of total power consumed, and 90 nm technologies is already approaching this limit. Most predictions are, if these trends continue, CMOS scaling can continue for only a decade or two (Nowak 2002; Moore et al 2003; Theis et al 2003). Many experts claim that the practical limit will be around 22 nm to 30 nm nodes (Woerlee et al 2001; Nowak et al 2002; Balazs et al 1998). Even before that limit is reached, there are some serious obstacles like Off current to overcome in the device. The different solutions the researchers proposed are discussed here Silicon-On-Nothing (SON) Silicon-On-Nothing (SON) transistors with gate length varying from 0.25 µm down to 80 nm exhibit excellent performance and scalability. The Silicon- On-Insulator (SOI) like architecture with thin fully depleted Si film and ultra thin buried oxide results in attenuated short-channel effects (charge sharing, DIBL and fringing fields), high current, and electron mobility. A new model accounts for the intrinsic mechanisms of operation in SON MOSFETs:

10 17 Substrate depletion governed by source and drain via doping modulation, Relatively low coupling between the front and back gates, Role of ultra thin buried oxide. Figure 2.3 Schematic architecture of a SON MOSFET The proposed new coupling model, which is necessary to take into account the specifics of the SON structure: very thin Buried Oxide (BOX), two active BOX interfaces, and substrate depletion controlled by source and drain. The new model includes the concept of voltage doping transformation and accurately describes the behavior of the threshold voltage and the sub threshold swing (Jeremy pretet et al 2004) Wafer Bonding Wafer bonding is an enabling technology that allows the fabrication of a variety of complicated structures that would be difficult or impossible to make by other means. The process of hydrophobic bonding removes the thin native oxide at surface of silicon wafers. For devices that utilize bulk conduction through the bond interface, this native oxide would reduce or destroy performance by creating traps and electrical discontinuities that will affect the I-V and C-V characteristics at the interface. Wafer bonding has been used to fabricate several important high power devices such as silicon controlled rectifiers and double side insulated gate bipolar devices. Another useful device for power applications is a stacked diode. In this

11 18 structure, multiple diodes are stacked in series using wafer-bonding techniques to provide the device with very high reverse blocking voltage Double Gate MOSFET The term FinFET (DG MOSFET) was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a non planar, double-gate transistor built on an SOI substrate, based on the earlier DELTA (single-gate) transistor design. DG MOSFETs (Huang et al 2001; Hisamoto et al 2000), have emerged as a superior alternative to replace the conventional bulk MOSFETs to continue the scaling. Figure 2.4 A double-gate DG MOSFET device The distinguishing characteristic of the DG MOSFET is that the conducting channel is wrapped around by a thin silicon "fin", which forms the body of the device. The dimensions of the fin determine the effective channel length of the device even down to a 10 nm feature size SELECTION OF DOUBLE GATE MOSFET According to the International Technology Roadmap for Semiconductor (Lederer et al 2005), MOS transistors will have gate lengths of around 10 nm in 2015, enabling the realization of very high performance VLSI circuits. The performance of these transistors is expected to be severely degraded by

12 19 short-channel effects (SCEs). For sub-100 nm scaling of MOSFETs, double-gate field-effect transistors like DG MOSFET are immune to Short channel effects and proximity to standard bulk planar CMOS processing steps (Kranti et al 2006). DG MOSFET has been proposed to improve the scalability of the MOSFET, for CMOS technology generations beyond the 100-nm technology node (Subramanian Vaidyanathan et al 2010). Since an ultrathin silicon body can effectively suppress short channel effects (SCE), a lightly doped or un doped body can be used to achieve high carrier mobility for improved transistor drive current, as well as to minimize variations in threshold voltage due to statistical doping variations (Antoniadis et al 2002 ; Ghani et al 2000). Figure 2.5 Structure of a DG MOSFET device Lack of body doping necessitates the use of gate work function engineering to adjust the drive current. However, the range of work functions required for thinbody MOSFETs is 4.4 V 5.0 V (Chang et al 2000), ruling out polycrystalline silicon as a gate material (Daewon et al 1996). Since the advanced DG MOSFETs require ultra-thin gate dielectrics, gate tunnelling currents may affect the drain leakage current in the sub threshold region of operation, leading to a substantial increase of the leakage energy which is harmful for applications in circuits of low power consumption (Saini et al 2010). The cross- sectional view of a DG MOSFET is shown in the Figure 2.6.

13 20 Figure 2.6 2D Cross-sectional view of the DG MOSFET In the DG MOSFET, the gate work function is fixed at ev to obtain the threshold voltage of V at a drain voltage of 0.1 V (Mohan Kumar et al 2010). Recently, in DG MOSFET structures with ultra-thin HfO 2 as gate dielectrics, the gate tunnelling current has been investigated experimentally with the source, drain and substrate electrodes grounded. The reported experimental results provide evidence for reduction of the gate tunnelling current density in narrow DG MOSFET structures compared to their counterpart quasi-planar structures (Subramanian et al 2007). However, until the present time there is no experimental work on the gate and drain Off current in DG MOSFETs with the drain bias set equal to the power supply voltage PERFORMANCE IMPROVEMENTS IN CHANNEL AND GATE ENGINEERED DG MOSFETS USING HIGH-K DIELECTRIC To improve the performance in conventional DG MOSFET over high-k dielectric materials using the parameters such as On current, Off current, Electro static surface potential, lateral electric field, transconductance, early voltage and DIBL. For channel lengths below 100 nm, DG MOSFETs show considerable threshold voltage roll off and DIBL (Drain Induced Barrier Lowering) effects. The reduction of threshold voltage with decreasing channel length and increasing drain voltage is widely used as an indicator of the SCEs in evaluating CMOS

14 21 technologies. This adverse threshold voltage roll-off effect is the most daunting road block for future MOSFET design. The minimum acceptable channel length is primarily determined by this roll-off (Shuang et al 2007; Tassis et al 2010). So in this work, Channel and Gate engineering technique is introduced in the DG MOSFETs to reduce the sub threshold leakage current and the Short Channel Effects. In the channel engineering technique, channel is highly doped near the source region to reduce the width of the depletion region in the vicinity of this junction resulting in reduced sub threshold leakage current and increased output impedance (Mohan Kumar et al 2009; Mohan Kumar et al 2010). This method is called as Lateral Channel Engineering. Halo or Pocket implanting in the channel is known as Lateral Asymmetric Channel (LAC) or Graded Channel Engineering (GC). The GC MOSFET is an asymmetric channel device which minimizes the inherent bipolar effects in Fully Depleted transistors (Kranti et al 2004). In single halo, an undoped region is preserved in the drain side of the channel. Such undoped region presents negative threshold voltage and can be considered as an extension of the drain region below the gate (Pavanello et al 2002). Halo implanted devices show excellent output characteristics with low DIBL, higher drive currents, flatter saturation characteristics, and slightly higher breakdown voltages compared to the conventional MOSFET (Venkateshwar et al 2004; Chakraborty et al 2007). On the other hand, Gate Engineering technique is used in the dual-material gate (DMG) DG MOSFET. In the year 1999, Long et al and Mohan Kumar et al (2009) proposed a gate engineering technique in which two different materials having different work functions are merged together to form a single gate of a bulk MOSFET. In the DMG structure, the work function of the gate material (M1) close to the source is chosen higher than that close to the drain end (M2) for n-channel DG MOSFETs (Long et al 1999; Zhou et al 2000). As a result, the electric field and electron velocity along the channel suddenly increases near the interface of the two gate materials, resulting in increased gate transport efficiency, which implies that the threshold voltage under

15 22 gate material M1 is higher than that under gate material M2. When the drain voltage exceeds the drain saturation voltage, the excess voltage is absorbed by gate material M2, preventing the drain field from penetrating into the channel. This is called gate work function engineering in DMG DG MOSFET. This device is to have the same threshold voltage for a reduced doping concentration in the channel region, resulting in better immunity to mobility degradation and also higher transconductance (Robert Chau et al 2005). In DMG DG MOSFET, the work functions of metals M1 (Molybdenum) and M2 (Aluminium) are taken as 4.55 ev and 4.1 ev, respectively, with equal lengths of L1 and L2, and a threshold voltage of 0.3 V and a drain voltage of 0.1 V is also obtained. The 2D schematic cross-sectional view of a DMG DG MOSFET is shown in Figure 2.7. Optimization of the length and concentration of the halo-doped region for the Single Halo DG MOSFET was carried out, and the optimum length was found to be 20 nm with a pocket implantation of cm 3. Increase in the halo doping concentration results in reduced short channel effects but on the other hand results in increased mobility degradation at the source end and threshold voltage. The 2D schematic cross-sectional view of a Single Halo DG MOSFET is shown in Figure 2.8. Figure 2.7 2D Cross-sectional view of the DMG DG MOSFET

16 23 Figure 2.8 2D Cross-sectional view of the Single Halo DG MOSFET The Off current in the channel engineering and gate engineering devices are lesser than the conventional DG MOSFET because of the screening of the drain bias by the step function in the surface potential profile (Mohan Kumar et al 2010). Gain and output resistance are also higher for these devices. So the devices like SHDG MOSFETs and DMGDG MOSFETs can be used for low-power sub threshold analog applications in future NOVEL APPROACH TO DIELECTRICS IN DG MOSFETS Since the advent of the Metal-Oxide Semiconductor (MOS) system over 40 years ago, the SiO 2 gate oxide has been serving as the key enabling material in scaling silicon CMOS technology (Houssa et al 2004). With the continuous miniaturization of devices, in order to improve the capability of gate control and control the short channel effects, the gate dielectric thickness should be scaled down with channel length. However, ultra-thin gate dielectric will increase the gate leakage current exponentially, resulting in a higher power consumption and reliability problem. The traps existing in the gate oxide and the surface will lead to significant Surface scattering and Coulomb scattering, which will greatly reduce the carrier effective mobility. Facing these challenges, scientists have already proposed some applicable solutions, including new materials, new technologies, new fabrication processes and also new device structures. The major advances in new

17 24 materials include the introduction of high-k materials and metal gate to solve the problems existing in the gate stack (Rudenko et al 2007; Kang et al 2005). With the integration of high-k dielectric materials into DG MOSFETs, the performance of the device is further enhanced. The DMGDG MOSFETs and SHDG MOSFETs are the future generation advanced semiconductor industry devices (Kang et al 2005; Nawaz et al 2007, Mohankumar et al 2010). Among the various requirements of gate dielectric materials, the most important are the good insulating properties and high capacitance value. Since the gate dielectric materials constitute the interlayer in the gate stacks, they should also have the ability to prevent diffusion of dopant such as boron and phosphorus and have few electrical defects which often compromise the breakdown performance. Meanwhile, they must have good thermal stability, high recrystallization temperature, sound interface qualities, and so on. The Off current of the devices are expected to decrease exponentially at higher dielectric value which avoids the direct tunnelling of electrons through the insulator. The DIBL which is an important indicator of performance of the devices also decreases exponentially with increasing dielectric value thereby suppressing Short Channel Effects (Rudenko et al 2007; Nowak et al 2002). The transconductance of the devices also increase with higher high-k material constant value. Gain and output resistance of the devices are expected to increase linearly while replacing the SiO 2 with other high-k dielectric materials. Thus the integration of gate oxide highk dielectric materials has improved the performance of the device. The most optimized results are obtained for devices with ZrO 2 as the gate dielectric in the DG MOSFETs CONCLUSION There have been many review papers, books, and industry consensus that proposed criteria for choosing alternative high-k dielectric materials for different applications. From the various analysis and investigations of these literatures, Zirconium dioxide was found out to be the best alternative for SiO 2 because of its excellent thermal stability, capacitive performance and insulating properties.

18 25 So Zirconium-di-oxide as dielectric material in transistors is indeed the future of nanotechnology. These transistors are expected to show excellent performance and they also shows reduced short-channel effects (SCEs). For sub-100 nm scaling of MOSFETs, DGMOSFETs have attracted considerable attention due to their immunity to SCEs and proximity to standard bulk planar CMOS processing (Tian et al 2007; Lederer et al 2005). Furthermore the gate and channel engineering techniques employed in MOSFETs enhance the device performance to a great extent. These techniques suppress the Short Channel Effects such as DIBL in the MOSFETs and also reduce the leakage current which will be discussed in the subsequent chapters. The integration of ZrO 2 as gate dielectric in these DMDG MOSFETs and SHDG MOSFETs further suppresses the leakage current and Short Channel effects making them more applicable for low power sub threshold analog circuits. Thus the channel and gate engineered DG MOSFET devices are the promising candidates for the future semiconductor industry.