Numerical Simulation of a Nanoscale DG N-MOSFET Using SILVACO Software

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1 Numerical Simulation of a Nanoscale DG N-MOSFET Using SILVACO Software Ahlam Guen Faculty of Technology Tlemcen University Tlemcen,Algeria guenahlam@yahoo.fr Benyounes Bouazza Faculty of Technology. Tlemcen University Tlemcen,Algeria bouaguen@yahoo.fr Abstract The regular decrease of transistors sizes which is close to the atomistic dimension leads today to nanometric devices. Double-Gate (DG) MOSFETs are considered to be one of the most promising candidates for nanoscale CMOS devises. DG MOSFET device might be the unique viable alternative to build nano MOSFETs when L g <50nm. It demonstrated a better control of the gate region with a reduction of short channel effects, a perfect electrostatic control and a superior scalability. However the design parameters strongly affect the structure current. This paper presents modeling and simulation of the electrical properties of a nanoscale DGFET n-channel MOSFET. Our contribution focuses on the study a DG n-mosfet parameters variation upon its electrical properties. Simulation results we obtained relating to the influence of some parameters variation, that having a direct impact on its drain current have been performed using SILVACO software [1]. Keywords-device scaling; double-gate MOSFET; SILVACO software ; device Simulation. I. INTRODUCTION Over the last 40 years, we have been witness of a gigantic increase in the semiconductor and consumer electronics industry. With an unrestrained race towards the miniaturization MOSFET size does not cease decreasing involving not only the reduction in the geometrical parameters of the devices such as the channel length, the gate oxide thickness... but also the electric parameters such as supply voltage. The minimum channel length which is a crucial dimension has been shrinking continuously and significantly since the MOSFET fabrication and will necessary continue this decreasing. The motivation behind this decrease has been a growing interest in high speed devices and in very large scale integrated circuits Today, in practice gate length in BULK MOSFETs are scaled to below 50 nm and gate lengths of experimental FETs [2] -[3] have approached currently 15 nm. With this continued scaling short channel effects SCE appears, this is the reason why improvements to MOSFETs transistors have been made in order to reduce these harmful effects. In order to maintain gate control, with an accurate threshold voltage V TH, the gate oxide thickness t ox reduction must imperatively scale with the channel length scaling. The aptitude to control drain current I D with gate voltage V G in conventional transistors could be maintained if channel length L ch, oxide thickness t ox and depletion layer depths are reduced in harmony. The most serious concern in this shrinking is Short Channel Effects (SCE) that motivates further investigations of new MOS structures that might lead to possible integration of transistors with channel lengths in the manometer range. For gate lengths down to 40nm MOSFETs performances are deteriorated due to Short Channel Effects (SCE).This means that the shrinking process will come to an end if no new technology can be found [4]. That is how double gate MOSFETS are nowadays considered to be the promising candidate for nanoscale CMOS devices Compared with conventional single gate metal oxide semiconducteur fieldeffect transistor (MOSFETs) [5]-[6]. These structures with two gates and a thin body demonstrate better control of the gate region and consequently suppression of short channel effects. DC analysis of DG devices has revealed that the drain current and transconductance of a DG MOSFET are higher than twice the drain current and transconductance, respectively,of a Single gate SOI MOSFET [7,8.9], due to volume inversion phenomena. In order to highlight the qualities and also the defects of DG MOSFETs, we propose in this work to present, simulation results we obtained using SILVACO software for a double gate n-channel MOSFET with static biased. II. SIMULATED DEVICE In this work we consider an ideal DG MOSFET viewed as a perfectly symmetrical device where the two channels facing each-other are activated simultaneously and feature identical charge and mobility. A Schematic diagram of Double Gate MOSFET is given in Fig. 1. And a Double gate MOSFET under Scanning Electron Microscopy is shown in Fig 2. 40

2 Where Jn and Jp, are current densities (A/cm 2 ) ; R and G are recombination and generation rate (cm -3 s -1 ). The transport equations used to express electrons and holes current densities due to drift and diffusion are given by (4) and (5). Figure 1. A Schematic diagram of Double Gate MOSFET [3] q is the elementary charge (As); ε is the semiconductor permittivity (As/Vm); p and n are hole and electron density (cm -3 ); are correspondingly ionized donor and acceptor density concentration (cm -3 ), D n and D p are diffusion coefficients (cm 2 s -1 ), µ n and µ p are respectively electrons and holes motilities (cm 2 /Vs). In this work, ATLAS (SILVACO) is used to simulate the electric properties of a 2 dimensional designed DGFET Standard structure represented in Fig.3. Within the calculator, the fundamental equations are based on the conventional drift-diffusion model of charge transport with Fermi-Dirac statistics. The equations Solutions are achieved by Gummel algorithm. All the models used (models for low field mobility, model for velocity saturation) are implemented in ATLAS SILVACO. Figure 2. DG MOSFET structure under Scanning Electron Microscopy [5]. The double gate MOSFET consists of a conducting channel surrounded by gate electrodes on either side. This guarantees that no part of the channel is far away from the gates electrode. In Double gate MOSFETs, gate voltage controls the electric field determining the amount of current flow through the channel. The most common mode of operation is to switch both gates concurrently. The standard model for universal devices simulations is the semi-classical transport simulation of electrons and holes based on the drift diffusion approximation called DD model. The conduction in this model is governed by Poisson's equation (1) which couples the electrostatic potential V to the charge density and carriers continuity equations (index n for electrons and index p for holes). Poisson equation (1) and carrier s continuity equations (2) and (3) are given by [1],[10],[11]: III. NUMERICAL ANALYSIS Figure3. A standard Symmetrical DG-MOSFET. Numerical simulation is a powerful tool in semiconductor industry because it can analyze and predict the behavior of new devices, without the elevated cost required to manufacture the real components. The TCAD, if appropriately used, has the potential to reduce development costs by as much as 40% [12]. The starting point for our simulations is a basic structure represented in Fig.4. The different parameters of our structure are assumed as follows:. 41 Figure 4.Symmetrical DG-MOSFET considered in this work.

3 Drain and source length L GS =L GD =3nm; silicon film thickness t si =3nm; channel length L ch =24nm; gate length L ch =24nm; channel doping N A =10 18 /cm 3 ; source/drain doping N D =10 20 /cm 3. The simulated output and transfer characteristics are plotted in Fig.5 and Fig. 6. A. Influence of t ox variation on I D current Scaling oxide thickness is desirable for better drain current. Consequently it is practical to consider the impact of t ox thickness on the device performance. Figs. 7 and 8 exhibit the output and the transfer characteristics at different gate lengths for our symmetrical DG n-mosfet. Figure 5. Simulated output characteristic I DS V DS of the DG n-mosfet structure Figure 7. Output characteristics for a DG n-mosfet at different oxide thickness irst, confirm that you have the correct template for your In order to study the influence of our structure Figure 6. Simulated transfer characteristic I parameters on its electrical characteristics, some DS V GS of the DG n-mosfet structure. parameters are modified. We examine then the effect of these variations on the considered structure drain current. V. INFLUENCE OF PARAMETERS VARIATION ON THE DRAIN CURRENT. In order to study the influence of our structure parameters on its electrical characteristics, some parameters are modified. We examine then the effect of these variations on the considered structure drain current. Figure 8. Transfer characteristics for a DG n-mosfet at different oxide thickness. Figs.7 and 8, allow observing the influence of the technological parameter t OX on the drain current and on the threshold voltage. Indeed, a significant gate thickness might isolate the gate. At thinner oxide thickness, the drain saturation current increases strongly. 42

4 Thinner gate oxides thickness leads to product higher drain currents and transconductances, and a better pinchoff behavior. Consequently it is suggested to apply the lowest possible oxide thickness in order to achieve a better drain current. We can also validate that oxide thickness has a direct impact on threshold voltage which increases when t ox increases. By reducing oxide thickness from 2 nm to 1 nm, it is possible to improve short channel performances significantly. Moreover, gate oxide thickness values lower than a critical value lead to serious tunneling leakage levels, which presents a severe limitation on further scaling, if SiO 2 is to be chosen as gate oxide. The solution to this issue right now mostly investigated in Silicon MOSFET technology is the substitution of SiO 2 with alternative high-k oxide, such as HfO 2, which can yield an equivalent oxide thickness lower than 1 nm, still keeping tunneling leakage low with a larger physical thickness. B. Influence of gate length variation on I D current This section deals with the study of gate length variation effect on the electrical device characteristics. In order to achieve this task, the channel length transistor was held constant; however the gate length covers part or the entire channel. The influence of gate length variation effects on drain current was studied by holding the channel length constant and equal to 24nm. Figs 9 and 10 illustrate the output and the transfer characteristics at different gate lengths for a DG n- MOSFET. Figure 10. Transfer characteristics for a DG n-mosfet for different gate lengts.. When the gate length increases, the saturation drain current decreases strongly.at shorter gate lengths a threshold voltage roll off can be observed. Gate length reduction may lead to a bad DIBL characteristic; and this will be an important issue for scaling down MOSFET devices from the fabrication engineering opinion, for scaling down MOSFET devices. Without considering the poor SCEs for short channel devices, it could be concluded that the gate length does not drastically modulate the onstate current of double-gate devices which will be limited because of the relatively high parasitic resistance resulting on the limitation of the on-state current devices. We can also note that gate length must be chosen judiciously because the gate loss its control on the channel when the gate length is less significant than channel length. Therefore it is important not to reduce the gate length randomly. C. Influence o f t si thickness variation on I D current It is useful to consider the impact of silicon thickness on the device current and performances.figs 11 and 12 show the output and the transfer characteristics for different silicon film thickness t si. Figure9. Output characteristics for a DG n-mosfet for different gate lengths. Figure 11: Transfer characteristics at different silicon film thickness t si. 43

5 Figure 12: Transfer characteristics at different silicon film thickness t si. We can observe that thicker channels lead to larger drain currents, and also to a displacement of the threshold voltage toward smaller values. Those drawbacks are principally caused by the fact that the device with a thicker tsi weakens the controllability of the gate electrodes. Figure 14. Description of DIBL for silicon film thickness t si=9nm Figs 13 and 14 allow to notice that transfer curves with tsi=3 nm slightly shows DIBL effects, whereas these transfer curves with tsi= 9nm present significant DIBL effects. Moreover, the off-state current Ioff is much higher with the thicker tsi than the off-state current Ioff with a thinner tsi. Also the Ioff current of our n-dgfet device with the thicker silicon film tsi is significantly elevated compared with the thinner one. At the end we can conclude that, devices with a thicker tsi owing poor gate controllability have a lesser channel barrier height, present a higher leakage current level, and get a bad result for DIBL effects. VI. CONCLUSION The scaling down of conventional planar bulk MOSFETs according to the International Technology Roadmap for Semiconductors requires new structures such Double Gate MOSFETs. These new structures allow reducing short channel effects that appears under 50nm node. In order to conceive these new structures numerical devices simulations are required. Variations of different structure parameters have been carried out to calculate their influence on the device characteristics. In this work Variations of the different DGFET structure parameters have been carried out to calculate the influence of these variations on the device characteristics. Figure 13. Description of DIBL for silicon film thickness t si=3nm. At the end of this paper, we observe that simulation results we obtained are comparable to the results encountered in theory and are thus considered very promising and satisfactory. 44

6 REFERENCE [1] SILVACO, ATLAS User s Manual, Ver. 4.0, June 1995 [2] B. Metzger, Radio priručnik za amatere i tehničare, Tehnička knjiga,beograd, 1983 [3] I.M. Kostić, Radiorehnički sklopovi i arhitekture, Pergamena,Podgorica, 1996 [4] S. Eminente, M. Alessandrini, and C. Fiegna Comparative analysis of the RF and noise performance of bulk and singlegate ultra-thin SOI MOSFETs by numerical simulation, Solid- State Electronics, vol. 48, no 4, pp , [5] Kavitha Ramasamy, Cristina Crespo, Double-Gate MOSFETS Portland State University ECE 515 Winter 2003 [6] M. Vinet, et al. Bonded planar double-metal-gate NMOS transistors down to 10nm, IEEE Transactions on Electron Devices, vol. 26, no. 5, pp , 2005 [7] S. Cristoloveanu, Silicon on Insulator Technologies anddevices: from present to future, Solid-State Electronics, vol. 43, pp , [8] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T.Elewa, Double-gate silicon-on-insulator transistor with volumeinversion: A new device with greatly enhancedperformance,ieee Electron Device Lett., vol. 8, no.9, pp , 1987 [9] F. Allibert, T. Ernst, J. Pretet, N. Hefyene, C. Perret, A.Zaslavsky, S. Cristoloveanu, From SOI materials to innovative devices, Solid-State Electronics, vol. 45, no. 4, pp ,2001. [10] Selberherr, S.: Analysis and Simulation of Semiconductor Devices. Berlin, Germany, Springer-Verlag [11] A.Amara, O. Rozeau, Planar, Double-Gate Transistor From Technology to Circuit Springer. [12] The International Technology Roadmap for Semiconductors 45