IMPACT OF CHANNEL ENGINEERING ON FINFETS USING HIGH-K DIELECTRICS

Transcription

1 International Journal of Micro and Nano Electronics, Circuits and Systems, 3(1), 2011, pp IMPACT OF CHANNEL ENGINEERING ON FINFETS USING HIGH-K DIELECTRICS D. Nirmal 1, Shruti K 1, Divya Mary Thomas 1, Patrick Chella Samuel 1, Vijaya Kumar 2 & N. Mohankumar 3 1 Department of Electronics and Communication Engineering, Karunya University, Coimbatore, (nirmal@karunya.edu, k.shruti@yahoo.co.in) 2 Department of Electrical and Electronic Engineering, Karpagam College of Engineering, Coimbatore. 3 Department of Electronics and Communication Engineering, SKP Engineering College, Thiruvanamalai. Abstract: FIN-SHAPED field-effect transistors (FinFETs) are being considered as preferred devices for the sub-70-nm-node CMOS technologies. However FinFETs with channel lengths below 100 nm show considerable leakage current and threshold voltage roll off. An investigation of the influence of channel engineering on the performances of FinFETs using high-k dielectrics for system-on-chip applications is done in this paper. A Single Halo (SH) FinFET is simulated using a 2D device simulator and their performance is analysed for parameters such as leakage current, DIBL and lateral electric field. The device performance is analyzed by replacing the SiO 2 with various high-k materials and the gate oxide thickness is scaled so that they have the same equivalent Oxide Thickness (EOT). The leakage associated with the device decreases by around 32% while DIBL decreases by around 60% with the integration of gate dielectrics. Thus the channel engineered FinFET with high-k dielectrics better immunity to short channel effects. Keywords: System-On-Chip; Lateral Asymmetric Channel; High-k dielectrics; Short Channel Effects. 1. INTRODUCTION CMOS technology is the most dominant and promising technology over the past decade in terms of scaling, performance, device properties, speed and dynamic power dissipation etc. The scaling of CMOS technology has been done for quite some years to achieve improved performance in terms of speed of operation, dynamic power dissipation etc. The RF performance of Metal Oxide Semiconductor devices has also improved to a great extent because of scaling of CMOS. As a result CMOS has become a viable option for analog RF applications and System-On-Chip (SoC) applications, where the analog circuits are realized with the digital circuits in the same integrated circuit to reduce the cost and improve the performance [1]-[2]. The scaling of MOSFETs is the main cause of the exponential improvements in integrated circuit performance. However with down-scaling of CMOS, the shortchannel effects (SCEs) which are caused by the decreasing gate control over the channel are among the most important challenges in the semiconductor industry. In order to suppress the SCEs, novel device architectures have been proposed. One of them is the double-gate MOSFET termed as FinFETs which has shown better downscaling characteristics and high performance when compared to the conventional single-gate device structures, due to better gate controllability over the channel. The gates shield the channel from both the sides in FinFETs thereby suppressing the penetration of carriers from the gate. Both the gates are strongly coupled to the channel to increase the transconductance. The FinFETs provide excellent immunity to SCEs, higher drive current and lower leakage current. The presence of second gate increases the effective gate control thereby reducing DIBL [3]. However, when the channel length of the device is below 100 nm, FinFETs show considerable threshold voltage roll off and DIBL effects. This adverse threshold voltage roll-off effect is the most daunting road block in future MOSFET design. The threshold voltage roll-off can be reduced or even reversed by locally raising the channel doping next to the drain or drain/source junctions [4] This method is called lateral channel engineering, e.g. halo or pocket implants and the engineered channel is known as Lateral Asymmetric Channel (LAC) or

2 8 International Journal of Micro and Nano Electronics, Circuits and Systems Graded channel {GC}. The GC MOSFET is an asymmetric channel device which minimizes the inherent bipolar effects in Fully Depleted transistors [5]. In single halo, an undoped region is preserved at the drain side of the channel. Such undoped region presents negative threshold voltage and can be considered as an extension of the drain region below the gate [6]. On the other hand the channel is heavily doped near the source region to reduce the width of the depletion region in the vicinity of this junction, thus reducing the subthreshold leakage current and increasing the output impedance. Halo implanted devices show excellent output characteristics with low DIBL, higher drive currents, flatter saturation characteristics, and slightly higher breakdown voltages compared to the FinFETs [7]. Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. From the beginning of MOS devices technology, SiO 2 has been used as gate oxide because of its stable SiO 2 /Si interface as well as its electrical isolation property [8]. For the past many years the physical thickness of SiO 2 has been aggressively scaled for low-power, high performance CMOS applications. The capacitive coupling between gate and substrate has been increased over the years by decreasing the gatedielectric thickness down to sub 2 nm [9]. In both logic and memory applications, SiO 2 gate dielectric s have reached minimum thickness due to direct tunnelling current and reliability concerns. The main driver for search for high-k materials is exponentially increasing gate oxide leakage with decreasing gate oxide thickness. Also SiO 2 is running out of atoms for further scaling. So in order to improve the circuit performance, materials with high dielectric (K) constant are used as gate dielectrics in devices instead of SiO 2. High-k dielectric materials have Equivalent Oxide Thickness (EOT) of 1.0nm with negligible gate oxide leakage, desirable transistor threshold voltages for n and p-channel MOSFETs, and transistor channel mobility close to those of SiO 2 [10]. Many candidates of possible high-k gate dielectrics have been suggested to replace SiO 2 and they include nitrided SiO 2, Hf-based oxides, and Zr-based oxides. These gate dielectric materials should have good insulating properties and capacitance performance. Because the gate dielectric materials constitute the interlayer in the gate stacks, they should also have the ability to prevent diffusion of dopants such as boron and phosphorus and have few electrical defects which often compromise the breakdown performance. They must also have good thermal stability, high recrystallization temperature, sound interface qualities, and so on [11]. So in this paper, the impact of high-k gate dielectrics on the device and circuit performance is studied over a range of dielectric permittivities. A Single Halo FinFET is created using Sentaurus of ISE TCAD and the device is simulated to analyse several parameters. The device is redesigned by replacing the gate dielectric of the device with various high-k dielectric materials and the performance of the device is analysed for parameters such as leakage current, DIBL and lateral electric field. 2. DEVICE STRUCTURE The technology parameters and the supply voltages used for device simulations are according to International Technology Roadmap for Semiconductors (ITRS), 2009 [12] for 100nm gate length devices Figure 1 shows the two dimensional cross-sectional view of a Single Halo (SH) FinFET. All the simulations performed are calibrated with standard experimental data [13]. The front and back gate oxide thickness is 2nm and the channel thickness is 20nm. The use of poly-si electrodes in MOS devices can significantly increase the Capacitance Equivalent Thickness (CET) result in high sheet resistance and cause dopant diffusion through the high-k layer. One viable way to solve these challenges is to use a metal as gate electrode. Metal gates eliminate poly depletion effect resulting in the reduction of inversion capacitance. [14] Molybdenum is taken as the gate material so that the gate work function can be fixed at 4.577eV to obtain the threshold voltage of V at a drain voltage of 0.1 V. Optimization of the length and concentration of the halo-doped region was carried out, and the optimum length was found to be 20 nm with a pocket implantation of cm 3. Increase in the halo doping concentration results in reduced short channel effects but on the other hand results in increased mobility degradation at the source end and threshold voltage. Gate length is fixed at 65nm. Simulations are carried out for a range of dielectric constants 10 and 25 which corresponds to materials Al 2 O 3, and HfO 2 respectively [15].Sentaurus of ISE TCAD [16] is used for 2-D simulation. Sentaurus device is a multidimensional,

3 Impact of Channel Engineering on FinFEts Using High-K Dielectrics 9 electro thermal, mixed-mode device and circuit simulator for one-dimensional, two-dimensional, and three-dimensional semiconductor devices. In Sentaurus Structure Editor, structures are generated or edited interactively using the graphical user interface (GUI). Doping profiles and meshing strategies can also be defined interactively. Figure 2 shows the screenshot of Single Halo FinFET created in structure editor of ISE TCAD. physical thickness and reduce the direct tunnelling leakage current [15]. Simulations are carried out for each of the devices with the above gate dielectric values. Figure 3 shows the I D -V GS curve for the n- channel Single Halo FinFET at different gate voltages for different high-k materials. Figure 1: 2D Cross-sectional View of the Single Halo-FINFET Figure 3: Plot of I D -V GS Curve at Different Vg for Different k Values in SH FInFET Figure 2: Screenshot of the Single Halo FinFET Created Using TCAD 3. SIMULATION RESULTS AND DISCUSSIONS In this work, the gate dielectric SiO 2 is replaced with various high-k dielectric materials. The proposed gate dielectric k values are 3.9,15 and 25. These dielectric materials corresponding to these dielectric constants are SiO 2, LaAlO 3, and HfO 2 respectively. These materials provide higher There is a 20% increase of drain current in the subthreshold regime for the channel-engineered device. The reason behind such improvement of the drain current is due to the increased electron velocity at the source end and thus improved carrier transport efficiency of the device. Since this improvement is more prominent in the subthreshold regime, the device is applicable for low power subthreshold analog circuits. The Single Halo (SH) FInFET exhibits a decrease of drain current in the case of strong inversion, owing to increased carrierto-carrier scattering. The device with SiO 2 as the gate dielectric has a drain current of.0023 A. As the k value increases, the drain current also increases. The device with LaAlO 3 as the gate dielectric has a drain current of.005 A while that with HfO 2 has the highest value of.007 A. Thus as the dielectric value increases, the drain current also increases. Leakage current or off current is the drain current at a gate to source voltage of 0.15V and drain to source voltage of 0.65V. FinFETs with thin silicon fins exhibit enhanced short channel immunity, due to better control of the channel by the gates, leading to relatively low values of the off-current. Due to the screening of the drain bias by the step function in the surface potential profile, any increase in the

4 10 International Journal of Micro and Nano Electronics, Circuits and Systems leakage current is suppressed in the Single Halo FinFET structure and the off-state leakage current is in fact less. Figure 4 shows the plot of off current variation with dielectric constant. The leakage current of the device with SiO 2 as the dielectric is.31na. As the gate dielectric value increases the leakage current is found to decrease exponentially. The device with LaAlO 3 as the gate dielectric has a drain current of.21na while that with HfO 2 has the lowest value of.20na. Figure 5: Variation of DIBL with Gate Dielectrics in SH FinFET Figure 6 shows the lateral electric field variation along the channel position for various k values. Figure 4: Variation of Leakage Current with Gate Dielectrics in SH FinFET For logic applications, Drain Induced Barrier Lowering (DIBL) plays an important role as device dimensions are scaled rigorously. The linear threshold voltage is based on the maximum transconductance and saturation threshold voltage is based on a modified constant-current method The DIBL co-efficient is computed as DIBL V, V = T LIN T, SAT (1) V DD V D, LIN where V t, lin and V t,sat are the threshold voltages measured at linear and saturation region for drain voltages of 0.1 V and 1.2 V respectively.the supply voltage of 1.2 V is taken as per the conventions of ITRS for 100 nm gate length in regard of logic applications. Figure 5 shows the Drain Induced Barrier Lowering as a function of various k values and it reveals that DIBL is the highest for device having SiO 2 as the dielectric material with a value of 12.5mV/V. DIBL decreases exponentially with increasing k values. FinFET with HfO 2 as the gate dielectric has the least DIBL value of 5mV/V. Figure 6: Variation of Lateral Electric Field Along the Channel in SH FinFET with Gate Dielectrics The Halo FinFETs shows a minute increase of potential, starting at the interface of the halo-doped portion and the silicon channel, due to the abrupt change of doping profile. The step increase of surface potential in these devices results in an additional electric field peak at the interface, in addition to that existing at the drain end. These additional peaks due to channel engineering techniques reduce the effective field at the drain end, resulting in smaller DIBL and hot-carrier effects, which are the major effects in the case of the shortchannel devices. From the figure, we can infer that the electric field increases with increasing k value. The peak shows the highest value for the device

5 Impact of Channel Engineering on FinFEts Using High-K Dielectrics 11 implemented with HfO 2 as dielectric material which has a gate dielectric value of CONCLUSIONS A clear analysis of the influence channel engineering on the performances of FinFETs is done in this paper. A Single Halo FinFET is created using ISE TCAD and simulated. The gate dielectric SiO 2 of the device is replaced with various high-k materials and simulations are done to evaluate their performance. The performance of the device for the gate dielectric values of 3.9,15 and 25 are analysed. The single Halo devices show a 20% increase in the drain current. The integration of high-k gate dielectrics further increases the drain current by about 25%. The off current and the DIBL are found to decrease exponentially with increase in gate dielectrics which implies that the device has superior short channel effect suppression capability. The lateral electric field also increases with increase in gate dielectric value. Thus the Single Halo FinFETs with high-k gate dielectrics are the promising devices of the future semiconductor industry. ACKNOWLEDGMENT The authors would like to thank the laboratory of Karunya University, Centre of Excellence in VLSI for its technical support. REFERENCES [1] N. Mohankumar, Binit Syamal, C.K. Sarkar, Performance and Optimization of Dual Material Gate (DMG) Short Channel BULK MOSFETs for Analog/Mixed Signal Applications, International Journal of Electronics. [2] Chakraborty S, Mallik A, Sarkar CK, Ramgopal Rao V., Impact of Halo Doping on the Subthreshold Performance of Deep-sub Micrometer CMOS Devices and Circuits for Ultralow Power Analog/ mixed Signal Applications, IEEE Trans Electron Dev; Vol. 54, No. 2, pp , Feb [3] N. Mohankumar, Binit Syamal, C.K. Sarkar, Investigation of Novel Attributes of Single Halo Dual-material Double Gate MOSFETs for Analog/ RF Applications, Microelectronics Reliability, 49, pp , Jul [4] N. Mohankumar, Binit Syamal, and Chandan Kumar Sarkar, Influenze of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs, IEEE Trans Electron Devices, Vol. 57, No. 4, pp , Apr [5] Kranti A, Chung TM, Flandre D, Raskin JP., Laterally Asymmetric Channel Engineering in Fully Depleted Double Gate SOI MOSFETs for High Performance Analog Applications, Solid State Electron, Vol. 48, pp , [6] Pavanello MA, Martino JA, Flandre D., Analog Circuit Design Using Graded Channel Silicon-on- Insulator n-mosfets, Solid State Electron, Vol. 46, pp , [7] G. Venkateshwar Reddy, M. Jagadesh Kumar, Investigation of the Novel Attributes of a Singlehalo Double Gate SOI MOSFET: 2D Simulation Study, Microelectronics Journal, Vol. 35, pp , July [8] A. Bouazra,1 S. Abdi-Ben Nasrallah,1 M. Said,1 and A. Poncet2, Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric, Research Letters in Physics, Vol. 2008, pp. 1-5, Januarary [9] Jung Han Kang, Chang Eun Kim, Myoung-Seok Kim, Jae-Min Myoung and Ilgu Yun; Material Characterization and Process Modelling Issues of High-k Dielectrics for FET Applications, IEEE Nanotechnology Materials and Devices Conference, pp , June [10] Krishna Kumar Bhuwalka, Nihar R. Mohapatra, Siva G. Narendra1, V Ramgopal Rao, Effective Dielectric Thickness Scaling for High-K Gate Dielectric MOSFETs, Mat. Res. Soc. Symp. Proc, Vol. 716, pp. B [11] A. P. Huang1,2, Z. C. Yang1 and Paul K. Chu2, Hafnium-based High-k Gate Dielectrics, Advances in Solid State Circuits Technologies pp [12] International Technology Roadmaps for Semiconductor (ITRS); [13] D. Esseni, M. Mastrapasqua, G. K. Celler, F. H. Baumann, C. Fiegna, L. Selmi, and E. Sangiorgi, Low field mobility of ultra-thin SOI N- and P- MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs, in IEDM Tech. Dig., 2000, pp [14] Robert Chau, Justin Brask, Suman Datta, Gilbert Dewey, Mark Doczy, Brian Doyle, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljevic, Application of High-k Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology, Research, Technology and Manufacturing Group, Intel Corporation, 2004 [15] C. R. Manoj, V.Ramgopal Rao, Impact of High-k gate dielectrics on the device and circuit performance of Nanoscale FinFETs, IEEE Electron Device Letters, vol. 28, no. 4, pp , April [16] Integrated Systems Engineering (ISE) TCAD Manuals. Release 10.0; 2006.