The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance

Transcription

1 826 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002 The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance Nihar R. Mohapatra, Student Member, IEEE, Madhav P. Desai, Member, IEEE, Siva G. Narendra, and V. Ramgopal Rao, Senior Member, IEEE Abstract The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities ( gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high- gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low- gate sidewalls with high- gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum gate for different target subthreshold leakage currents has been identified. Index Terms Circuit simulation, fringing field, gate insulator, high- dielectric, Monte Carlo methods and leakage current, MOSFETs, short channel effect. Fig. 1. Schematic of a MOS transistor with various capacitance components. I. INTRODUCTION ACCORDING to the SIA roadmap, CMOS with gate length below 70 nm will need an oxide thickness of less than 1.5 nm, which corresponds to two to three layers of silicon dioxide atoms. With such a thin gate oxide, direct tunneling occurs resulting in an exponential increase of gate leakage current [1] [4]. The resulting gate leakage current will increase the power dissipation and will deteriorate the device performance and circuit stability for VLSI circuits. High- gate dielectrics such as Al O, HfO ZrO,La O and TiO have received much attention recently to prevent direct gate tunneling [5] [7]. In the last few years, much work has been done to understand the properties of above high- gate dielectrics including the technological issues with their fabrication. Some of the problems currently being looked Manuscript received May 15, 2001; revised January 21, This work was supported by the Intel Corporation. The review of this paper was arranged by Editor K. Shenai. N. R. Mohapatra, M. P. Desai, and V. R. Rao are with the Department of Electrical Engineering, Indian Institute of Technology, Bombay, , India ( rrao@ee.iitb.ac.in). S. G. Narendra is with the Microprocessor Research Laboratory, Intel Corporation, Hillsboro, OR USA. Publisher Item Identifier S (02) Fig. 2. Dependence of outer fringe capacitance of a 70-nm MOS transistor on gate and spacer dielectric constant. at by various research groups include interfacial layer formation during the thermal process, micro-crystal formation during the process and the mobility degradation. Also, higher physical gate dielectric thickness (by a factor of ) in high, MOS transistors results in higher fringing fields from gate to source/drain regions, weakening the gate control [8]. This leads to poor subthreshold performance and increased short channel effects /02$ IEEE

2 MOHAPATRA et al.: EFFECT OF HIGH- GATE DIELECTRICS 827 Fig. 3. Variation of inner fringe capacitance and surface potential of a 70-nm MOS transistor along the channel as a function of gate dielectric constant. In this article, extensive simulations have been carried out to study the impact of high- gate dielectrics and spacer dielectric materials on deep sub-micrometer MOS transistor performance. We have analyzed the gate to source/drain parasitic fringe capacitances and gate-to-channel capacitance for various high- gate dielectric MOS transistors using a highly accurate three-dimensional (3-D) Monte Carlo technique [9]. The detailed analysis of 70 nm CMOS circuit performance issues with various high- dielectrics is presented using extensive mixed-mode simulations. Results are presented which provide useful insight into the physics of MOS transistors with highgate dielectrics. Fig. 4. Threshold voltage and drain-induced barrier lowering (DIBL) for a 70-nm MOS transistor as a function of gate dielectric constant for different spacer dielectric material. II. SIMULATION STRUCTURES The various components of fringing capacitances are extracted using a Monte-Carlo based 3-D capacitance extractor, CAPEM. For this purpose we used a simple structure. The source, drain and gate are defined as conductors. The substrate is also assumed to be highly doped. The gate electrode length and source/drain electrode depths used are 70 nm and 36 nm, respectively. A channel plate is used to measure the gate-to-substrate capacitance, which is kept at 18 nm and 1 nm from the Si/SiO interface to represent depletion and weak inversion conditions respectively. The extractor solves the Laplace s equation for the different electrode potentials using a random walk algorithm [9], which directly evaluates the interelectrode capacitance. Device simulations are performed using a two-dimensional (2-D) device simulator MEDICI [10]. The simulated structures, which are based on scaled device dimensions outlined in the SIA roadmap [11], have a gate length down to 70 nm and an oxide thickness of 1.5 nm. A spacer technology with heavily doped source/drain extensions is used. The source/drain extensions and deep source/drain junction depths are 30 nm and 50 nm, respectively. The device has a peak channel doping of 2 10 cm. The permittivities of gate dielectric are varied from 3.9 to 100 keeping the effective gate dielectric thickness constant at 1.5 nm. The spacer dielectric Fig. 5. Gate-to-channel capacitance for a 70-nm MOS transistor as a function of gate dielectric constant. Results are plotted for different spacer dielectric material. constant is also varied from 1.2 to 10 to observe the fringing field distribution with different spacer material. The calibrated energy balance model is incorporated to consider the spatial variation of carrier energy in order to account for the velocity overshoot and nonlocal transport phenomena. The energy relaxation time used for the hydrodynamic simulation was 0.2 ps. The Fermi Dirac statistics are used to determine the active carrier density within the simulation structures. A combination of coupled and uncoupled solution technique is used for simulation of devices at room temperature. To isolate the capacitance degradation essentially due to fringing fields, the effects of poly-depletion and quantum mechanical effects are not taken into account. III. RESULTS AND DISCUSSION The different capacitances associated with the MOS system are shown in Fig. 1. The top capacitance is the top fringing capacitance associated with electric field emerging

3 828 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002 from top surface of the poly-gate and going through the first layer of passivation/planarization dielectrics (TEOS) and ending at source/drain regions. The sidewall capacitance is the sidewall fringing capacitance associated with the electric field emerging from the sidewall of poly-gate and ending at source/drain regions. For our study, we have defined the outer fringe capacitance as the parallel combination of and These capacitances are extracted using a Monte-Carlo based 3-D capacitance extraction technique. Fig. 2 shows the variation of outer fringe capacitance as a function of gate and spacer dielectric permittivity. As shown in the figure, the decreases with increasing due to larger distance (because of higher physical gate dielectric thickness), traveled by the field lines before reaching the source/drain regions from side and top of the gate electrode. In case of low- material as spacer, the field lines travel through low- material, further reducing. The internal fringe capacitance, shown in Fig. 3, increases with due to a large number of field lines terminating on the inside edges of source/drain. These field lines finally induce an electric field from the source-to-channel thereby reducing the source-to-channel barrier height, as shown in the same figure. Since the threshold voltage of the device is controlled by the injection of electrons over this potential barrier, it decreases with increasing, as shown in Fig. 4. With increase in, the physical thickness of the gate dielectric becomes comparable to the channel length. So the percentage of field lines originating from bottom of the gate electrode and terminating on the source/drain regions (shown as increased ) increases compared to the field lines terminating on the channel. Therefore, decreases with increasing as shown in Fig. 5. However, the use of a low- spacer can well confine the electric field lines within the channel region thereby increasing the gate-to-channel capacitance. Due to this decrease in gate control in high- gate MOS transistors, the drain electrode is tightly coupled to the channel and the lateral electric field from the drain reaches a larger distance into the channel. This electrically closer proximity of drain to source gives rise to higher short channel effect such as drain-induced barrier lowering (DIBL) in high MOS transistors (shown in Fig. 4). We have also measured the off-state leakage of the worst case device, having a channel length and saturation drain current for different and supply voltage. As shown in Fig. 6, the ratio decreases with due to a decrease in the threshold voltage as well as due to the degraded subthreshold characteristics. This behavior can pose a major challenge for high- MOSFETs to be used in dynamic logic circuits. The effect of high permittivity gate dielectrics on the circuit performance is studied using mixed-mode simulation module of MEDICI. The circuit used for the simulation is shown in Fig. 7. For circuit simulations, the zero carrier solution as well as the doping information, mesh, material properties, electrode contact, and model information for the NMOS and PMOS transistors are extracted from device simulation module of MEDICI. Fig. 6. Threshold voltage (a) Saturation current (I ) to off-state current (I ) ratio of (b) a 70-nm MOS transistor as a function of supply voltage for various gate dielectrics. Fig. 7. Inverter structure used for mixed-mode simulations in MEDICI. The widths of PMOS transistors (P1, P2) are three times that of NMOS transistors (N1, N2) to maximize the noise margins and to obtain symmetrical characteristic [11]. The input pulse applied to the gate of the first stage inverter has a rise and fall time smaller than the inverter input rise and fall time to achieve lower short circuit power dissipation and higher speed. The cur-

4 MOHAPATRA et al.: EFFECT OF HIGH- GATE DIELECTRICS 829 Fig. 8. Dc output characteristics and noise margin (NM) of a 70-nm CMOS inverter as a function of gate dielectric constant. Fig. 10. Total energy dissipation (switching energy and leakage energy) for a 70-nm CMOS inverter, with gate and drain bias of 0.8 V, for various gate dielectrics. Fig. 9. Inverter gate delay for a 70-nm CMOS inverter, with gate and drain bias of 0.8 V, for various gate dielectrics. rent-controlled current source (CCCS) is used to measure the switching energy dissipation and has a gain of unity. Fig. 8 shows the dc characteristics of the inverter for different gate dielectric permittivities. It can be seen that with increase in the slope of the transition region (region between two logic levels) increases due to higher short channel effects. This results in decreased output impedance and noise margin. Since the gain of an analog circuit is directly proportional to the transconductance and output impedance of MOS transistors, this could be a bottleneck for higher MOS- FETs to be used in analog circuits. Fig. 9 shows the delay characteristics of the inverter for different gate dielectric permittivities. The delays are measured between the 50% transitions of input output waveforms of the first stage inverter. As can be seen, the delay decreases with higher due to a decrease in parasitic capacitance and increase in the saturation current (lower ) of the device. However, the delay is improved with Fig. 11. Variation of substrate doping as a function of gate dielectric constant for different off-state leakage currents. decrease in spacer dielectric constant, due to better confinement of field lines in the gate region and lower outer fringe capacitance. Fig. 10 shows the total energy dissipation (switching and leakage energy) of the circuit (shown in Fig. 7) for different and supply voltage. The switching energy is calculated by multiplying the charge collected by the second stage (measured from the voltage developed across the capacitor C1 due to switching current ) with the voltage swing at the output node of the first stage The leakage energy has two components. One is due to leakage current flowing through the reverse diode junctions of the transistors located between the source or drain and substrate. This

5 830 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 5, MAY 2002 MOSFETs, however, increases the transverse electric field and degrades the surface mobility. Hence, the circuit delay is increased after a certain, as shown in Fig. 12(a). From this figure, the existence of an optimum can be observed for achieving the specified off-state leakage with the help of high- gate dielectrics. We have also extracted the delay characteristics for different off-state leakage with different spacer dielectric material. This is plotted in Fig. 12(b). It can be observed that with low- gate sidewalls the delay is improved but there is very less change in optimum. IV. CONCLUSIONS The impact of high- gate dielectrics on device short-channel and circuit performance is studied using extensive device and circuit simulations. It is found that the degradation in short channel performance using highgate dielectrics is caused by the fringing fields from the gate-to-source/drain regions. A quantitative estimate of the fringing field effects has been provided for the first time by extracting the various capacitance components in the MOS system using Monte-Carlo techniques. It is found that the use of low- sidewalls can improve the device short channel performance by reducing the fringing-induced barrier lowering for thick-gate insulators. It is also beneficial from the circuit point of view. It is also confirmed from the results that there is the presence of an optimum for specified off-current requirements in different technology generations. REFERENCES Fig. 12. Inverter gate delay for a 70-nm CMOS inverter at a gate and drain bias of 0.8 V, as a function of gate dielectric constant. (a) Results are plotted for various subthreshold leakage currents and (b) results are plotted for various spacer dielectric materials. contribution in general is very small and can be ignored. Another component of leakage energy is due to the subthreshold leakage current. The contribution of this component is larger in short channel devices. So where is the clock-width in secs. In this work we have used a clock-width of 400 ps. As can be seen from the figure, the total energy dissipation decreases in higher MOSFETs due to lower load capacitance. This behavior could be advantageous for higher MOSFETs to be used in low power circuits. In this paper, we have also looked at the device optimization with high- gate dielectrics for maintaining an off-state leakage current of 10, 1, 0.1 na m. This is achieved by varying the peak channel doping for different. As shown in Fig. 11, higher channel doping is required for higher to achieve identical and subthreshold characteristics as that of SiO MOSFETs. The higher channel doping in high [1] H. Iwai, Ultra thin gate oxides Performance and reliability, in IEDM Tech. Dig., 1998, pp [2] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide MOSFETs, IEEE Electron Device Lett., vol. 18, pp , May [3] H. Iwai, Downsizing of silicon MOSFETs beyond 0.1 m, Microelectron. J., vol. 29, pp , Apr [4] B. Yu, H. Wang, C. Ricobene, Q. Xiang, and M. R. Lin, Limits of gate oxide scaling in nano-transistors, in VLSI Tech. Dig., 2000, pp [5] S. A. Campbell, D. C. Gilmer, X. C. Wang, H. S. Kim, and J. Yan, MOS transistors fabricated with high permittivity TiO dielectrics, IEEE Trans. Electron Devices, vol. 44, pp , May [6] W. J. Qi, R. Nieh, B. H. Lee, K. Onishi, and L. Kang, Performance of MOSFETs with ultra-thin ZrO and Zr silicate gate dielectrics, in VLSI Tech. Dig., 2000, pp [7] A. Chin, Y. H. Wu, S. B. Chen, C. C. Lias, and W. J. Chen, High quality La O and Al O gate dielectrics with equivalent oxide thickness 5 10 A, in VLSI Tech. Dig., 2000, pp [8] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. Zeitzoff, and J. C. S. Woo, The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs, IEEE Trans. Electron Devices, vol. 46, pp , July [9] Y. L. Lecoz and J. N. Jere, An improved floating random walk algorithm for solving multi-dielectric drichlet problem, IEEE Trans. Microw. Theory Tech., vol. 41, pp , Feb [10] User s Manual for MEDICI 2-Dimensional Device Simulation, AVANT Corporation, Fremont, CA, [11] The National Technology Roadmap for Semiconductors Technology Needs, Semiconductor Industry Association. [12] P. Chandrakasan and W. Broderson, Low Power CMOS Digital Design. Norwood, MA: Kluwer, 1996.

6 MOHAPATRA et al.: EFFECT OF HIGH- GATE DIELECTRICS 831 Nihar R. Mohapatra (S 01) received the B.Tech. degree in electrical engineering from Sambalpur University, Orissa, India, in Since July 1999, he has been pursuing the Ph.D. degree at the Indian Institute of Technology (IIT), Bombay, India. His current interests are in the areas of MOS physics and technology, characterization, modeling and simulation. He has worked on modeling and simulation of high-k gate dielectrics, short-channel effects, and hot-carrier reliability in MOS transistors. Siva G. Narendra received the B.E. degree from Government College of Technology, Coimbatore, India, in 1992, the M.S. degree from Syracuse University, Syracuse, NY, in 1994, and the Ph.D. degree from Massachusetts Institute of Technology, Cambridge, in He has been with Intel Laboratories since 1997, where his research areas include low voltage MOS analog and digital circuits and impact of MOS parameter variation on circuit design. He is Adjunct Faculty with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis, and has authored or co-authored over 15 papers and has 11 issued and 31 pending patents. Dr. Narendra is an Associate Editor for the IEEE TRANSACTIONS ON VLSI SYSTEMS and a Member of the Technical Program Committee of the 2002 International Symposium on Low Power Electronics and Design. Madhav P. Desai (M 01) received the B.Tech. in electrical engineering from the Indian Institute of Technology (IIT), Bombay, India, in 1984, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana. From 1992 to 1996, he was with the Semiconductor Engineering Group, Digital Equipment Corporation, Hudson, MA, where he was a Principal Engineer. He is currently an Associate Professor in the Department of Electrical Engineering, IIT. Dr. Desai s interests are in the areas of VLSI design and design tools, circuits, and systems, and combinatorial algorithms. His doctoral work involved the study of the simulated annealing algorithm, which is a popular combinatorial optimization technique. While at Digital, he worked on timing verification, delay modeling, and circuit and interconnect optimization, and contributed to the design of two of the world s fastest CMOS microprocessors. Dr. Desai has been the recipient of GTE and Schlumberger Graduate Fellowships. He has served as a reviewer for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, the IEEE TRANSACTIONS ON COMPUTERS, the SIAM Journal on Control, and various conferences. V. Ramgopal Rao (SM 01) received the M.Tech. from the Indian Institute of Technology (IIT), Bombay, India, in 1991, and the Dr.-Ing (magna cum laude) degree from the Faculty of Electrical Engineering, Universitaet der Bundeswehr Munich, Germany, in 1997, writing his doctoral thesis on planar-doped-barrier sub-100 nm channel length MOSFETs. He was a Deutscher Akademischer Austauschdienst/German-Academic-Exchange Service (DAAD) Fellow for three years ( ) and from February 1997 to July 1998, a Visiting Scholar with the Electrical Engineering Department, University of California, Los Angeles. He is currently an Associate Professor in the Department of Electrical Engineering, IIT. His areas of interest include ultra-thin gate oxides and their reliability due to plasma and hot-carrier stress, gate and channel engineering issues for deep submicron MOSFETs, molecular electronics, and Bio-MEMS. He has over 90 publications in these areas in refereed international journals and conference proceedings and holds a couple of patents in the area of vertical MOSFETs.