THE primary motivation for scaling complementary metal

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1 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER Shielded Channel Double-Gate MOSFET: A Novel Device for Reliable Nanoscale CMOS Applications AliA.Orouji,Member, IEEE, and M. Jagadesh Kumar, Senior Member, IEEE Abstract In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated. Index Terms Hot carrier effect, shielded channel (SC), shortchannel effects (SCEs), side gate, SOI MOSFET, subthreshold swing, threshold voltage, two-dimensional (2-D) simulation. I. INTRODUCTION THE primary motivation for scaling complementary metal oxide semiconductor (CMOS) devices is the increased functionality per unit cost and the improved performance of devices. As the scaling continues, it becomes harder to fabricate devices without compromising performance due to the undesirable effects such as threshold voltage roll-off, draininduced barrier lowering (DIBL), and degraded subthreshold swing. A number of solutions have been proposed for these problems [1] [4]. Employing a double-gate (DG) metal-oxidesemiconductor field-effect transistor (MOSFET) structure instead of using the conventional metal-oxide-semiconductor (MOS) transistors is one of these solutions. The DG structure exhibits the best performance in terms of the short-channel effects (SCEs), subthreshold swing, current drivability, and transconductance [5] [7]. One of the problems affecting the DG MOSFETs is the control of the threshold voltage that is hardly dependent on the doping concentration and strongly affected by the thickness of the silicon thin film at the same time. Acceptable values for the threshold voltage ( V for V DD =1 1.5 V) are obtained when asymmetrical double-gate (A-DG) structure Manuscript received October 14, 2004; revised March 18, The work of A. A. Orouji is supported by Semnan University, Semnan, Iran. A. A. Orouji is with the Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi , India and also with Semnan University, Semnan, Iran. M. J. Kumar is with the Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi , India ( mamidala@ieee.org). Digital Object Identifier /TDMR Fig. 1. Cross-sectional view of an N-channel SC-DG MOSFET. with one p + -poly and one n + -poly is realized [8]. Furthermore, device simulations demonstrate that the asymmetric structure provides almost the same drain ON current as the symmetric one [8]. For these reasons, it might be concluded that the A-DG structure is preferable because the symmetric DG structure would require alternative gate materials with a work function tailored to provide an acceptable threshold voltage, leading to a more expensive fabrication process. The DG MOSFETs also suffer from considerable shortchannel behavior in the sub-100-nm regime. To enhance the immunity against the SCEs and therefore improve the device reliability in high-performance circuit applications, a new concept, called the shielded channel DG (SC-DG) MOSFET structure, in which the front gate consists of two side gates, which are biased independently of the main gate, to provide an electrical shield to the channel region and also to function as the virtual extensions of the source and the drain, is proposed. The aim of this paper is therefore to present the design and performance considerations of the SC-DG SOI MOSFET and compare its performance with that of the conventional A-DG SOI MOSFET in terms of threshold voltage roll-off, electric field in the channel, subthreshold swing, and hot carrier effects. The effects of varying the side/main gate parameters are investigated using the two-dimensional (2-D) simulator MEDICI [9]. Our results demonstrate that the proposed SC-DG silicon-on-insulator (SOI) MOSFET exhibits significantly reduced SCEs, thus making it a more reliable device configuration than the conventional DG SOI MOSFET for high-performance CMOS circuit applications /$ IEEE

2 510 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 Fig. 2. Electron distribution in log scale for the SC-DG structure under V MGS =0.1 V, V SGS =0.5 V,andV DS =0Vconditions. Fig. 3. Surface potential profiles in the channel of the SC-DG MOSFET for different drain biases. II. SC-DG STRUCTURE A schematic cross-sectional view of the SC-DG MOSFET implemented in the 2-D device simulator MEDICI is shown in Fig. 1. The front gate consists of n + -poly and p + -poly for the side gates and the main gate, respectively, while the back gate is an n + -poly gate. To avoid adverse effects associated with heavy doping, such as the mobility degradation [10] and the random microscopic fluctuations of dopant atoms [11], the doping in the silicon thin film is kept at cm 3 (i.e., lightly doped with N A < cm 3 [12]). The doping in the n + source/drain regions is kept at cm 3. The typical values of the main gate and the side gate lengths are identical and equal to 50 nm. Note that the thicknesses of the main gate oxide and the side gate oxide are identical and equal to 3 nm. The thickness of the diffusion barrier between the main and the side gate is 4 nm. The work functions of the p + -poly and the n + -poly gates are chosen as 5.25 and 4.17 ev, respectively. The typical value of the silicon film thickness is chosen as 10 nm. All the device parameters of the SC-DG MOSFET are equivalent to those of the A-DG MOSFET, unless otherwise stated. It is worth noting that the front gate of the SC-DG structure can be fabricated using the same experimental procedure as reported for the electrically shallow junction MOSFET (EJ-MOSFET) in [13] and [14]. III. SIMULATION METHOD Conventional 2-D simulation of semiconductor devices is based on the thermal equilibrium approximation (TEA) in which the carrier temperatures are assumed to be the same as the lattice (constant) temperature. For extremely scaled devices, this assumption is invalid because under a high electric

3 OROUJI AND KUMAR: SC-DG MOSFET: NOVEL DEVICE FOR RELIABLE NANOSCALE CMOS APPLICATIONS 511 Fig. 5. Threshold voltage versus main channel length for channel lengths up to 20 nm with V DS =50mV. Fig. 4. Output characteristics of the SC-DG and the A-DG structures for (a) V SGS =1.5 Vand (b) V SGS =0.5 V. field in these devices, the carrier temperature can be much higher than the ambient temperature. Therefore, conventional drift models are not sufficient to describe the drain current characteristics and the energy balance equation needs to be used for improved prediction of the short-channel device behavior [15] [17]. Hence, the authors have selected the full energy balance model for the mobility model in the simulations in which the electron temperature is fed back into the continuity equation and the impact ionization is again computed as a postprocessing step. If the carrier temperature is not fed back to the drift-diffusion equation [9], substantial errors can result in the prediction of the carrier transport. IV. RESULTS AND DISCUSSION A typical MEDICI simulated 2-D electron density distribution under the main gate voltage V MGS =0.1 V, the side gate voltage V SGS =0.5 V, and the drain-to-source voltage V DS = 0Vconditions is shown in Fig. 2. Due to the exponential relation between the carrier concentration and the potential, the figure also illustrates the 2-D distribution of electrostatic potential φ(x, y). It can be seen from the figure that the electron distribution in the channel region under the side gates is almost fixed, and the change is very limited [18]. Since a very thin silicon layer (10 nm) is used in the DG structure [19], [20] and due to the small and identical values of work functions of the side gates and the back gate, a strong and almost uniform inversion region can be formed under the side gates. This inversion layer not only acts as an effective electrical shield to the channel region, but it will also function as the virtual extensions of the source and the drain regions. It is worth noting that the SC-DG structure is a symmetrical double-gate (S-DG) structure in the side gate regions and an A-DG structure in the main gate region. Therefore, the proposed SC-DG structure combines the good features of both the S-DG and A-DG structures. In Fig. 3, the surface potential is plotted against the horizontal distance in the channel. It can be seen from the figure that due to the presence of the shielding provided by the inversion regions under the side gates, there is no significant change in the potential under the main gate when the drain bias is increased even up to 1.5 V. Hence, the channel region under the main gate is shielded from the changes in the drain potential, i.e., the drain voltage variations do not affect the potential in the main gate region. As a consequence, V DS has only a very small effect on drain current after saturation. This can be observed from the simulated output characteristics, including impact ionization, for the SC-DG and the A-DG structures shown in Fig. 4 for two cases: V SGS =1.5Vand V SGS =0.5V. The drain current decreases slightly when the value of V SGS is reduced from 1.5 to 0.5 V due to the reduction in the inversion layer charge under the side gates. In both cases, it is noted that the output conductance of the SC-DG is significantly improved over that of the A-DG structure. In addition, it can be seen from the figure that the operating voltage range of the device will be improved due to an increase in the breakdown voltage of the device. Therefore, the side gates (i.e., virtual source/drain) are expected to effectively suppress the SCEs.

4 512 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 Fig. 6. Subthreshold swing versus main channel length for channel lengths up to 20 nm. Fig. 8. Surface potential profiles in the channel of the SC-DG MOSFET for different side gate biases. Fig. 9. Threshold voltage versus side gate length for different side gate biases. Fig. 7. Longitudinal electric fields along the channel toward the drain end. In Fig. 5 and 6, the threshold voltage and the subthreshold swing of the SC-DG structure are compared with the A-DG MOSFET as a function of the main channel length. It can be clearly observed that the SC-DG structure exhibits lower threshold voltage rolloff and better subthreshold swing than the A-DG structure. The threshold voltage values in the simulation are obtained from the commonly used maximum transconductance method. In Fig. 7, the electric field distribution along the channel near the drain is shown for the A-DG and the SC-DG MOSFETs with a channel length L =50nm. It is evident from the figure that the presence of a side gate at the drain side reduces the peak electric field considerably. As a result, the breakdown voltage of the device increases, as observed in Fig. 4 earlier. Fig. 8 shows the dependence of the surface potential on the side gate bias. The main gate voltage is set at 0.3 V. When the side gate bias is less than 0 V, the surface potential in the virtual drain is low, and there are not enough carriers in the virtual drain. However, when the side gate bias is more than 0 V, the potential in the virtual drain will increase, and the carrier concentration in the virtual source and drain is sufficient for the inversion regions to function as the virtual source and drain. As the side gate voltage increases, resistance of the virtual source and drain (due to dependency of carrier s concentration to voltage bias) will be reduced and the current of the device will increase. It should be noted that the potential edge in the virtual drain moves only slightly toward the channel as the side gate bias increases above 0 V. This indicates that the channel length depends only marginally on the side gate bias. Fig. 9 shows the threshold voltage rolloff on the variation of side gate conditions (length and bias). It can be observed clearly that the SC-DG structure exhibits a very good feature, i.e., the threshold voltage has a very small rollup (less than 2 mv increase when the side gate voltage increases from 0.5 to 1.5 V for L S =50nm). For a given side gate voltage, if the side gate length is reduced from 60 to 20 nm, the increase in threshold voltage is less than 5 mv. Hence, it is clear that the threshold voltage practically remains invariant with length and

5 OROUJI AND KUMAR: SC-DG MOSFET: NOVEL DEVICE FOR RELIABLE NANOSCALE CMOS APPLICATIONS 513 A-DG structure, as shown in the figure. The hot carrier effect increases with a decrease in the side gate length. In other words, the choice of the side gate length determines the extent of hot carrier effects in the device. As a final discussion, the SC-DG structure suffers from the coupling capacitance between the side and the main gates. Therefore, the material and thickness of the diffusion barrier have an important role in reducing this capacitance that is under further investigation. Nevertheless, this structure is suitable for studies on SCEs, hot electron behaviors, and the device reliability. Fig. 10. Vertical electric field profiles along the A A cut line. V. C ONCLUSION To overcome the short-channel effects (SCEs) for improving the reliability of nanoscale metal-oxide-semiconductor fieldeffect transistors (MOSFETs) in high-performance complementary metal oxide semiconductor (CMOS) applications, a novel shielded channel double-gate (SC-DG) silicon-oninsulator (SOI) MOSFET has been proposed. In this structure, two side gates on either side of the main gate are biased independent of the main gate to create ultrashallow virtual extensions to the source and the drain and also to provide an effective electrical shield for the channel region from the drain voltage variations. The performance of the device has been evaluated using two-dimensional (2-D) simulation and compared with that of a conventional DG SOI MOSFET. Based on the simulation results, it is demonstrated that due to the presence of an effective shield provided by the side gates, the proposed device exhibits significantly reduced SCEs such as drain-induced barrier lowering (DIBL) and hot carrier effect. It is expected that the SC MOSFET could be of significant importance in CMOS applications requiring extreme scaling with improved reliability. Fig. 11. Electron temperature at the surface of the silicon thin film layer for different side gate lengths. applied bias of the side gate, making this an important useful feature of the SC-DG MOSFET. To investigate the hot carrier effects in the SC-DG structure, a comparison in terms of vertical electric field and electron temperature is performed. Fig. 10 shows the vertical field in the side gate region along the A A cut line located at 5 nm from the edge of the side gate region on the drain side. It can be seen that the peak electric field at the front gate side is large compared to the back gate and that the electric field at the back gate side increases with a decrease in the side gate length. Fig. 11 shows the electron temperature at the silicon thin-film surface for the SC-DG and A-DG structures for a fixed main channel length of 50 nm. The side gate lengths of the SC-DG structure are varied from 20 to 50 nm. Due to the high electric field near the drain end, the electron temperature is different from the lattice temperature. However, it is observed that for a side gate length of 50 nm, the hot carrier effect will be significantly lower in the SC-DG structure, as compared to the REFERENCES [1] A. Chaudhry and M. J. Kumar, Controlling short-channel effect in deepsubmicron SOI MOSFETs for improved reliability: A review, IEEE Trans. Device Mater. Reliab., vol. 4, no. 1, pp , Mar [2] M. J. Kumar and A. Chaudhry, Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs, IEEE Trans. Electron Devices, vol. 51, no. 4, pp , Apr [3] A. Chaudhry and M. J. Kumar, Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET, IEEE Trans. Electron Devices, vol. 51, no. 9, pp , Sep [4] G. V. Reddy and M. J. Kumar, A new dual-material double-gate (DMDG) nanoscale SOI MOSFET Two-dimensional analytical modeling and simulation, IEEE Trans. Nanotechnol., vol. 4, no. 2, pp , Mar [5] H. P. Wong, D. J. Frank, and P. M. Solomon, Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation, in Int. Electron Devices Meeting (IEDM) Tech. Dig., San Francisco, CA, Dec. 1998, pp [6] T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, Ultrafast operation of V th -adjusted p + n + double-gate SOI MOSFETs, IEEE Electron Device Lett., vol. 15, no. 10, pp , Oct [7] J. G. Fossum and Y. Chong, Simulation-based assessment of 50 nm double-gate SOI CMOS performance, in Proc. IEEE Int. SOI Conf., Stuart, FL, Oct. 1998, pp [8] K. Kim and J. G. Fossum, Double gate CMOS: Symmetrical versus asymmetrical gate devices, IEEE Trans. Electron Devices, vol. 48, no. 2, pp , Feb [9] MEDICI 4.0. Palo Alto, CA: Technology Modeling Assoc., 1997.

6 514 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 [10] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Amimoto, and T. Itoh, Analytical surface potential expression for thin-film double-gate SOI MOSFETs, Solid-State Electron., vol. 37, no. 2, pp , [11] P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, Modeling of ultrathin double-gate nmos/soi transistors, IEEE Trans. Electron Devices, vol. 41, no. 5, pp , May [12] Y. Taur, Analytical solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs, IEEE Trans. Electron Devices, vol. 48, no. 12, pp , Dec [13] W. Y. Choi, B. Y. Choi, D. S. Woo, Y. J. Choi, J. D. Lee, and B. G. Park, Side-gate design optimization of 50 nm MOSFETs with electrically induced source/drain, Jpn. J. Appl. Phys., vol.41,no.4b,pp , Apr [14] H. Kawaura, T. Sakamoto, T. Baba, Y. Ochiai, J. Fujita, and J. Sone, Transistor characteristics of 14-nm-gate-length EJ-MOSFETs, IEEE Trans. Electron Devices, vol. 47, no. 4, pp , Apr [15] T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Schuster, and H. N. Yu, 1 µm MOSFET VLSI technology part IV: Hot-electron design constraints, IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp , Apr [16] H. Gesch, J. P. Leburton, and G. E. Dorda, Generation of interface states by hot hole injection in MOSFETs, IEEE Trans. Electron Devices, vol. ED-29, no. 5, pp , May [17] K. K. Ng and G. W. Taylor, Effects of hot-carrier trapping in n- and p-channel MOSFETs, IEEE Trans. Electron Devices, vol. ED-30, no. 8, pp , Aug [18] Q. Chen, E. M. Harrell, and J. D. Meindl, A physical shortchannel threshold voltage model for undoped symmetrical double-gate MOSFETs, IEEE Trans. Electron Devices,vol.50,no.7,pp , Jul [19] B. Majkusiak, T. Janik, and J. Walczak, Semiconductor thickness effects in the double-gate SOI MOSFET, IEEE Trans. Electron Devices,vol.45, no. 5, pp , May [20] K. Suzuki and T. Sugii, Analytical models for n + p + double-gate SOI MOSFET s, IEEE Trans. Electron Devices, vol. 42, no. 11, pp , Nov M. Jagadesh Kumar (M 95 SM 99) was born in Mamidala, Nalgonda District, Andhra Pradesh, India. He received the M.S. and Ph.D. degrees in electrical engineering from the Indian Institute of Technology, Madras, India. From 1991 to 1994, he performed postdoctoral research in modeling and processing of high-speed bipolar transistors with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada. While with the University of Waterloo, he also did research on amorphous silicon thin-film transistors (TFTs). From July 1994 to December 1995, he was initially with the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India, and then joined the Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi, India, where he became an Associate Professor in July 1997 and a Full Professor in January His research interests are in very large-scale integrated (VLSI) device modeling and simulation for nanoscale applications, integrated circuit technology, and power semiconductor devices. Dr. Kumar is a Fellow of the Institute of Electronics and Telecommunication Engineers (IETE), India. He has reviewed extensively for different journals including the IEEE TRANSACTIONS ON ELECTRON DEVICES, the Proceedings of the Institute of Electrical Engineers on Circuits, Devices and Systems, Electronics Letters, and Solid-State Electronics. He was the Chairman, Fellowship Committee, of the 16th International Conference on VLSI Design, January 4 8, 2003, New Delhi, India. He is the Chairman of the Technical Committee for High-Frequency Devices, International Workshop on the Physics of Semiconductor Devices, December 13 17, 2005, New Delhi. Ali A. Orouji (M 05) was born in Neyshabour, Iran, in He received the B.S. and M.S. degrees in electronic engineering from the Iran University of Science and Technology (IUST), Tehran, Iran, in 1989 and 1992, respectively. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi, India. Since 1992, he has been working at the Semnan University, Semnan, Iran, as a faculty member. His research interests are in modeling of siliconon-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET), novel device structures, and analog integrated circuits design.