Investigation of a new modified source/drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation

Transcription

1 Phsica E 33 (2006) Investigation of a new modified source/drain for diminished self-heating effects in nanoscale MOSFETs using computer simulation M. Jagadesh Kumar a,, Ali A. Orouji b a Department of Electrical Engineering, Indian Institute of Technolog, New Delhi, India b Department of Electrical Engineering, Semnan Universit, Semnan, Iran Received 17 October 2005; received in revised form 16 Januar 2006; accepted 19 Januar 2006 Available online 17 April 2006 Abstract In this paper, we demonstrate that b introducing a buried oide in a bulk MOSFET onl under the source and drain regions, i.e., using an ogen implanted source/drain (OISD) structure, the drain capacitance of a nanoscale MOSFET can be made close to that of a silicon-on-insulator SOI MOSFET while the self-heating effects are highl diminished and are similar to that of a bulk MOSFET. Twodimensional simulation is used to optimize the length and thickness of the OISD regions. r 2006 Published b Elsevier B.V. PACS: e Kewords: Self-heating; Silicon-on-insulator (SOI); MOSFET; Capacitance; Temperature distribution; Two-dimensional (2-D) simulation 1. Introduction Silicon-on-insulator (SOI) MOSFETs have man advantages for high-performance and low-voltage applications in the sub-half-micron regime since the offer a steeper subthreshold swing, reduced parasitic capacitance and elimination of latch up [1]. However, self-heating is a major problem in SOI MOSFETs as compared to the bulk MOSFETs due to the decreased heat flow across the buried oide. The temperature rise causes a decrease in the drain current and leads to more serious reliabilit problems such as increased electromigraton and enhanced impact ionization. In the past, several attempts have been made to reduce the temperature rise stemming from this self-heating [2,3]. In this paper, we eamine an alternative measure to reduce the self-heating effects b introducing a buried oide in a bulk MOSFET onl under the source and drain regions which can be easil created with implantation of Corresponding author. Fa: address: mamidala@ieee.org (M. Jagadesh Kumar). ogen molecules under source/drain regions. Using twodimensional simulation [4], we demonstrate that introducing optimized ogen implanted source and drain (OISD) Fig. 1. Cross-sectional view of an N-channel /$ - see front matter r 2006 Published b Elsevier B.V. doi: /j.phse

2 M. Jagadesh Kumar, A.A. Orouji / Phsica E 33 (2006) Table 1 Parameters for OISD structure used in MEDICI simulation Parameter /drain p-tpe silicon film doping Thickness of the source/drain laer ( ) Thickness of the OISD region ( ) Distance of the OISD regions ( ) Channel length oide thickness work function Value cm cm 3 50nm 300 nm 100 nm 100 nm 5 nm 4.8 ev regions in a bulk MOSFET, we can achieve low junction capacitances comparable to that of an SOI MOSFET while the self-heating effects are significantl reduced. 2. Simulation method and device parameters There is a lattice temperature advanced application module (LT-AAM) in MEDICI simulator [4]. Therefore, it is possible to couple the electrical and thermal characteristics of devices for their accurate modeling. In this case, a new state variable, the temperature of the lattice, is Fig D temperature distribution of (a) OISD, (b) bulk and (c) SOI MOSFETs.

3 136 ARTICLE IN PRESS M. Jagadesh Kumar, A.A. Orouji / Phsica E 33 (2006) introduced into MEDICI in order to describe the selfheating of devices. Poisson s equation, the current continuit equation, and the heat equation are solved in a completel coupled manner to obtain the temperature of the lattice. A schematic cross-sectional view of the OISD MOSFET implemented using the 2-D device simulator MEDICI is shown in Fig. 1 where and are the thickness of OISD region and the distance between the two OISD regions, respectivel. The simulation parameters of the structure are given in Table 1. We have compared this OISD structure with that SOI and bulk MOSFETs with equivalent parameters. 3. Results and discussions Fig. 2 shows a tpical MEDICI simulated 3-D temperature distribution in the OISD, SOI and bulk MOSFETs for V GS ¼ 1 V and V DS ¼ 1:5 V. The temperature in the substrate is fied at 300 K. As can be seen from Fig. 2(a), the maimum temperature in the OISD structure (E320 K) is ver close to that of the peak temperature in the bulk MOSFET (E310 K) as shown in Fig. 2(b) and is significantl smaller than the peak temperature (E510 K) shown in Fig. 2(c) for the SOI MOSFET. The reduced selfheating effect is also clearl reflected in the output characteristics shown in Fig. 3 in which the drain current of the OISD structure is close to that of the bulk MOSFET. For optimizing the length and thickness of the OISD regions, we have carried out a comparison in terms of zerobias drain capacitance and maimum device temperature as shown in Fig. 4. It can be observed clearl that when the distance between OISD regions ( ) decreases, the maimum temperature of the device will increase. However, the zero-bias drain capacitance of the device is ver weakl dependent on the distance between the OISD regions up to 90 nm and ehibits onl about 5% variation. Therefore, in the OISD MOSFETs, b keeping the distance between the OISD regions ( ) almost equal to that of the channel length, the temperature of the device can be kept close to that of the bulk MOSFET, while the drain Capacitance (F/µm) 5.00E E E E E E = 300 nm Distance between OISD regions (nm) Fig. 4. Maimum temperature and zero drain capacitance versus distance between OISD-regions. (a) Maimum Temperature (Kelvin) V GS = 1 V = 300 nm = 100 nm Current (ma) (b) Voltage (Volts) Fig. 3. Output characteristics of OISD, SOI and bulk MOSFETs. Fig. 5. Depletion region formation when the distance between OISDregions (L OSID ) is (a) less than the channel length and (b) greater than the channel length.

4 M. Jagadesh Kumar, A.A. Orouji / Phsica E 33 (2006) capacitance is close to that of the SOI MOSFET. However, if the distance between the OISD regions ( ) is below the channel length (100 nm), the zero-bias drain capacitance abruptl increases. This can be understood from Fig. 5. Our simulation shows that when is less than the channel length, the zero-bias depletion region is as shown schematicall in Fig. 5(a). However, if eceeds the channel length, the zero-bias depletion region forms over an etended length as shown schematicall in Fig. 5(b) increasing the zero-bias drain capacitance. Fig. 6 shows the dependence of the maimum temperature and zero drain-bias capacitance on the thickness ( ) of the OISD regions. The distance between OISD regions is set equal to the channel length at 100 nm. We can observe that the maimum device temperature is weakl dependent on the thickness of the OISD regions because heat removal takes place through the gap between the OISD regions. The drain capacitance is also weakl dependent on the thickness of the OISD regions if the thickness is more than 50 nm. However, if the thickness of the OISD regions ( ) is smaller than 50 nm, the zero-bias drain capacitance increases abruptl. This can be understood from Fig. 7 in which, based on our simulation results, the formation of the depletion for two different cases are schematicall shown. If the thickness of the OISD-regions (t OSID ) is less than the zero-bias source/drain depletion region thickness (Fig. 7(a)), the length over which the depletion region forms is more than the case when the thickness of the OISD-regions (t OSID ) is greater than the zero-bias source/drain depletion region thickness (Fig. 7(b)). This clearl shows the reason wh the drain capacitance increases when is smaller than 50 nm. The importance of the standb current or leakage current as a factor to be included in the performance figure of merit for deep submicron CMOS has recentl been proposed and analzed for bulk CMOS technolog [5,6]. Therefore, the transfer characteristic of OISD structure is shown in Fig. 8. It can be seen from the figure that the leakage current of OISD device reduces when compared to the bulk MOSFET due to the junction area Capacitance (F/µm) 5.00E E E E E E = 100 nm Thickness of OISD regions (nm) Fig. 6. Maimum temperature and zero drain capacitance versus thickness of OISD regions. Maimum Temperature (Kelvin) (a) (b) LOISD reduction. Also, the subthreshold slope of the device improves. Fig. 9 shows the threshold voltage of OISD, SOI, and bulk MOSFET structures versus the channel Fig. 7. Depletion region formation when the thickness of the OISDregions (t OSID ) is (a) less than the zero-bias source/drain depletion region thickness and (b) greater than the zero-bias source/drain depletion region thickness. Current (Amp) 1E-4 1E-5 1E-6 1E-7 1E-8 V DS = 50 mv = 300 nm = 100 nm 1E-9 1E Voltage (Volts) Fig. 8. Transfer characteristics of OISD, SOI, and bulk MOSFETs.

5 138 ARTICLE IN PRESS M. Jagadesh Kumar, A.A. Orouji / Phsica E 33 (2006) Threshold Voltage (Volts) length up to 50 nm. It is clear that the variation of threshold voltage for the OISD structure is similar or slightl better when compared to the bulk MOSFET. 4. Conclusions V DS = 50 mv = 300 nm = 100 nm Channel Length (nm) Fig. 9. Threshold voltage of OISD structure versus channel length up to 50 nm. under the source and drain of a MOSFET, one can realize self heating effects close to that of a bulk MOSFET while the drain capacitance is similar to that an SOI MOSFET. We have also shown that even if there are variations in the distance between the OISD regions or their thickness, it will not criticall affect the projected benefits. In conclusion, we can design the OISD structure for best performance b choosing the distance between the OISD regions about the channel length, and the thickness of OISD regions greater than the difference between width of depletion region under the gate and the thickness of n+ source/drain regions. References [1] A. Chaudhr, M.J. Kumar, IEEE Trans. Device Mater. Reliabilit 4 (2004) 99. [2] M. Zhu, P. Chen, R.K.Y. Fu, Z. An, C. Lin, P.K. Chu, IEEE Trans. Electron. Devices 51 (2004) 901. [3] B. Cole, S. Parke, A method to overcome self-heating effects in SOI MOSFETs, IEEE Universit/Government/Industr Microelectronics Smposium, Proceeding of the 15th Biennial, 2003, p [4] MEDICI 4.0, Technolog Modeling Associates, PaloAlto, CA, [5] R.A. Chapman, T.C. Hollowa, V.M. McNeil, A. Chatterjee, G.E. Stace, IEEE Trans. Electron Devices 4 (1997) [6] K. Ro, S. Mukhopadha, H. Mahmoodi-Meimand, Proc. IEEE 91 (2003) 305. In this paper, using two-dimensional simulation, we have demonstrated that b introducing an oide region just