ANALYTICAL MODELING OF TRIPLE GATE MOSFET

Transcription

1 International Journal of Semiconductor Science & Technology (IJSST) ISSN Vol. 3, Issue 4, Oct 2013, 1-10 TJPRC Pvt. Ltd. ANALYTICAL MODELING OF TRIPLE GATE MOSFET S NANDI 1 & M SARKAR 2 1 Department of E. C. E., Bengal Institute of Technology, Kolkata, West Bengal, India 2 Department of E. C. E., B.P.Poddar Institute of Management and Technology, Kolkata, West Bengal, India ABSTRACT There are so many reasons for evolving from single-gate to multi-gate structures of MOSFET. Our proposal describes how to increase the quality of current drive and improve the short-channel effects (SCEs) of Triple Gate (TG) MOSFET. We also calculate the threshold voltage, drain-induced barrier lowering (DIBL) and surface potential and discussed a model for the transconductance, drain current and drain conductance in comparison with the Double-gate (DG) and Single-gate (SG) MOSFET. The simulation of triple-gate MOSFET shown the transconductance and voltage gain are increased to 81.47uS and respectively with respect to Double-gate (DG) and Single-gate (SG) MOSFET. Better results of operation for the parameters like surface potential, electric field and threshold voltage in triple gate (TG) MOSFET are also established. KEYWORDS: Triple Gate, Conductance, Drain-Induced Barrier Lowering (DIBL), Transconductance, Voltage-Gain and BOX INTRODUCTION In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator (SOI) MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and properties of such devices are described and the emergence of a new class of MOSFETs, called Triple-Gate (TG) MOSFET. Scaling or mapping the CMOS technology into nanometer authorities requires advanced approach in order to overcome a number of short-channel effects (SCEs) [12]. Triple-gate MOSFET has excellent short-channel effect (SCE) exemption, high transconductance and ideal subthreshold factor [1-10, 21]. With fast-growing technology scaling is used to improve performance, single-gate (SG) MOSFET scaling is preferred to overcome the prejudiced short-channel effects (SCEs) and henceforth to better the device reliableness [14]. The control ability of the gate voltage on the threshold voltage reduces as the channel length decreases because the amount of charge sharing increases from source-to-drain [25]. Therefore, channel length decreases with reduction in the threshold voltage as well as drain-induced barrier lowering (DIBL) have their significant effects that demand to be accosted while offering immunity against SCEs [1, 5]. To raise the exemption versus SCEs, a new structure called a Triple-gate (TG) MOSFET was proposed [1, 24], which include a thin gate insulator and a gate on all three sides of the channel, as shown in Figure 1 (a) to explain the basic transistor dimensions. Double-gate (DG) MOSFET can be scaled to shortest channel-length possible for a given gate oxide thickness, because the back gate can efficiently block out the field penetration from the drain, hence inhibit the short channel effects (SCEs) [16, 27]. In Double-gate (DG) MOSFET, the front and back gates can be able to control together to get greater Ion/Ioff ratio [26].

2 2 S Nandi & M Sarkar Figure 1(a): Basic 3D Structure Model of Triple Gate SOI MOSFET Figure 1(b): Cross Sectional View of Double Gate SOI MOSFET Figure 1(c): Cross Sectional View of Single Gate SOI MOSFET Triple-Gate MOSFETs has the quality in terms of current drive & short channel effect control. It is possible to design & fabricate quasi-surrounding gate MOSFET [11, 17] using the same process which is used for Triple gate MOSFET. These devices are called either π-gate [14] or Ω-gate [15]. Basically, these are a form of Triple-gate MOSFET with a extension of the gate electrode below the active Silicon island which increases current drive & improves shortchannel effects. The gate extension can readily be formed by slightly overetching the buried oxide (BOX) during the Silicon island patterning step. Triple-gate MOSFETs are considered as important candidates for prospective in very large scale integration (VLSI), particularly for low-power and high-performance at 45 nm CMOS Technology [18]. The Triplegate MOSFET is a non-planar narrow transistor where the gates are wrapping the silicon body. The gates control two lateral channels as well as the top horizontal channel. It is a thin film consists of narrow silicon island with a gate on three of its sides. The triple gate transistor is ideal for use in fully depleted transistor applications. The triple gate MOSFET includes a thin semiconductor body formed on a substrate. A gate dielectric formed on top surface and side wall of semiconductor body. Source and drain regions formed on semiconductor body on opposite side of gate electrode. Because the gate electrode and gate dielectric surround the semiconductor body on three sides, the transistor has three separate channels and gates. The transistor gate width is equal to sum of each of the three sides of semiconductor body. Double-Gate (DG) MOSFETs are the good candidate to replace the conventional MOSFETs in this particular region because of their excellent immunity to the short channel effects [12]. It is the most suitable device structures for suppressing short-channel effects such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off as the channel length of device goes down in 45 nm Technology. The role of threshold voltage has an important with IC applications for achieving targets such as low-voltage, high speed and low power applications [23, 29]. Figure 1(b) shows

3 Analytical Modeling of Triple Gate MOSFET 3 the cross sectional view of double-gate SOI MOSFET. It has two gates, which controls the charge in the thin silicon body layer, and allows current flow for both the channels. Because SOI film is thin, a direct charge coupling exists between the front and back gate invariably [13]. In a symmetric long-channel DG MOSFET, the oxide thickness (tox), the gate material and gate voltage (Vg) are identical for both the gates. In the subthreshold region of operation since the amount of charge in the fully depleted lightly doped silicon film is negligible, the potential in the entire silicon film is almost constant and depends only on Vg resulting in almost ideal subthreshold swing. Since the silicon film is almost equi-potential, an interesting phenomenon of volume inversion [19] is observed. Volume inversion essentially refers to the fact that with increased Vg, the entire silicon film is inverted to the same extent. In the DG MOSFET structure, the alignment of the top and bottom gates to each other as well to source/drain capacitance. This problem is resolved in the FinFET, which has a self-aligned triple gate structure [20]. 2-D simulation is used here to show the decreasing in SCEs is demonstrated by the Triple-gate (TG) structure at 45nm technology, whenever at the same time get a higher transconductance is compared to the Double-gate (DG) MOSFET. The aim of this research is display how to apply two dimensional (2-D) simulations; the decreasing in (SCEs) is demonstrated by the Triple-gate (TG) structure at 45nm technology, whenever at the same time get a higher transconductance is compared to the Double-gate (DG) MOSFET. With this model, we can explain an appreciable decrement in the peak electrical field near the drain end and rise in drain break down voltage. Higher level transconductance and a suitable threshold voltage roll-up even for channel lengths of 45nm. We must examine the two dimensional (2-D) modeling inside TG MOSFET and DG MOSFET, it can used to solving Poisson s equations to productive the surface potential, electrical field, drain current [12], leakage of electric current and DIBL [13]. 1 (c) shows the cross sectional view of single-gate SOI MOSFET. The model is verified by comparing the model results with the simulation results using Cadence Virtuoso Simulator. ANALYTICAL DETAILS Body Potential The schematic diagram of an n-channel Triple-gate (TG) MOSFET, the current flow direction is perpendicular as shown in Figure 2. along the axis. The following assumptions and steps are use for the potential modeling. The potential variation is parabolic between the two lateral gates: p, q q p q p q (1) Where is the two dimensional body potential to a body region. This assumption is used for addressing the short channel effects in MOSFETs and describing the variation in potential in the vertical direction (between the front and the back interface). Figure 2: Cross Sectional View of Triple Gate (TG) MOSFET

4 4 S Nandi & M Sarkar The high depletion and negligible body structure doping is solved using Poisson s equation: (2) The surface potential at front end is: w/ 2, q p, 0 s1 (3) This assumption is absolutely explained at q = 0 in undoped body because the corner effects are negligible. The surface potential at back end is: 0, tsi s2 (4) Where s2 is the maximum surface potential. The solution of (2) by using (1) and (3) is given by: p, q = s1+ ( ) (5) Where f (q) defined as: f = Sin h (6) In triple gate, the front gate and the lateral gates are connected and give the assumption given by equation (3). The two dimensional potential founded by equation (5). According to equation (5), and are sufficient for reassemble of the two dimensional (2-D) potential. The accuracy of the potential along the q direction for p 0 depends on V g2 in. The two dimensional (2-D) simulations is superior for q<20nm and = (0, t si ). Threshold Voltage as: In the potential model, the derivation of the threshold voltage is straight forward. The threshold voltage is follows V g1 =V fb1 + E + s1 (7) The electrical field Es1 is given by: E Substitute the value of E in equation (7) V g1 =V fb1 + s1 +γ ( ) (8) Where, γ = (9) and C w = (10)

5 Analytical Modeling of Triple Gate MOSFET 5 Where C w is the film capacitance. Similarly, we can write: V g2 =V fb2 + s2 + ) (11) Where, (12) V fb2 is the back interface voltage and C ox2 is the buried oxide capacitance. Equation (8) and (11) are describing the coupling interface between the substrate and front gate in a triple gate MOSFET. The drain-induced barrier lowering (DIBL) of the TG MOSFET structure can be given as: DIBL = V th V th (13) SIMULATION DETAILS The 2-D analytical modeling and Cadence Virtuoso tool simulation results of the electric field and minimum surface potential (Ø_(s.min)) of triple gate (TG) MOSFET are represented here. The typical dimensions used for the triple gate (TG), double gate (DG) and single gate (SG) are mentioned in Table 1. Table 1: Typical Dimensions Used for the TG, DG and SG Structure Parameter Value Front Gate Oxide 2.2nm Back Gate Oxide 2.2nm Top Gate Oxide 2.2nm Figure 3. (a) can display the simulated surface potential and electric field with respect to the channel length (L) of 45nm at the (TG) triple gate structure along with the (SG) single gate model. The surface potential is advance, when drainsource voltage V ds is increased for a fixed value of gate voltage V g. The drain-source voltage V ds is increased, the minimum surface potential (Ø_(s.min) ) shifts towards the source, then we can applying higher level gate to source voltage (V gs ), the magnitude of entire surface potential can also be elevated and it reduced the hot carrier effect [24]. Also in 2-D numerical model the radiation induced change in the flat-band voltage has been utilized to estimate the changes in the surface potential and hence the threshold voltage of the device in the irradiated condition. [16] Figure 3(a): Surface Potential with Respect to the Channel Length Figure 3(b): Electric Field with Respect to the Channel Length

6 6 S Nandi & M Sarkar Figure 3. (b) explain the electric field at drain end of the triple gate (TG), double gate (DG) and single gate (SG) MOSFET, the calculated and simulated data of electric field with respect to the channel length of model are shown in that figure. The peak value electric field of the triple gate (TG) structure at the drain end is reduced by approximately (20%) twenty percent with respect to the double gate (DG) and single gate (SG) model due to the discontinuity in the surface potential. Figure 4. shows the variation in DIBL along with the channel length for TG, DG and SG MOSFETs. Drain induced barrier lowering (DIBL) can take place due to the increase in the drain to source voltage (V ds ) as well as gate to source voltage (V gs ) because it reduces the source-channel barrier of TG MOSFET [26]. The Cadence virtuoso tool simulation results are computed as the difference between the linear threshold voltage and saturation threshold voltage. The value of DIBL in triple gate (TG) structure along the channel length is mV. It can be concluded that the DIBL increase in the TG structure is less than the DG and SG structures with the reducing channel lengths. Figure 5. (a), (b) and (c) shows the drain current characteristics (I ds -V ds ) of TG, DG and SG MOSFETs for a channel length of 45nm. The drain current of triple gate (TG) structure is larger than the double gate (DG) and single gate (SG) model structures. The SG structure presents increased transconductance, reduced drain conductance, and increase in drain breakdown voltage. The surface potential increased along the channel length with reduces the DIBL and the peak electric field at the drain end [21]. Figure 4: DIBL of TG, DG and SG MOSFETs Figure 5(a): Shows the Drain Characteristics (I ds - V ds ) are Plotted for Different Channel Lengths of TG MOSFETs for a Channel Length L=45nm Figure 5(b): Shows the Drain Characteristics (I ds - V ds ) Figure 5(c): Shows the Drain Characteristics (I ds - V ds ) of DG MOSFETs For a Channel Length L=45nm of SG MOSFETs for a Channel Length L=45nm Figure 6 and 7 show the transconductance (g m ) and drain conductance (g d ) for TG, DG and SG structures are plotted with different channel lengths. Transconductance of TG MOSFET is higher than that of the DG and SG MOSFETs, because of an increase in channel length the transconductance is decreasing. The value of g m is found the slope of I ds - V ds

7 Analytical Modeling of Triple Gate MOSFET 7 between V gs = 0.7V at V ds = 0.5V, where g d is found from the slope of I ds - V ds between V ds = 0.5V at V gs = 0.7V. The transconductance of TG MOSFET is obtained by differentiating the drain current with respect to the gate to source voltage for a constant drain to source voltage and is expressed as: g m = Figure 6: Shows the variation of g m with Different Channels for DG and SG MOSFETs Figure 7: Shows the variation of g d with Different Channels for DG and SG MOSFETs Figure 8: Shows the Variation of Voltage Gain (gm/gd) with Different Channel Lengths for TG, DG and SG MOSFETs Figure 9: Shows the Variation of Drain Resistance with Different Channel Lengths for TG, DG and SG MOSFETs Figure 8 shows the voltage gain (g m /g d ) of the TG, DG and SG MOSFETs as a function of channel length for 45nm. The voltage gain of triple gate (TG) structure is higher when compared with that of the DG and SG structures, because of an increase in transconductance and a decrease in the drain conductance. Figure 9. shows the variation of drain resistance of the TG, DG and SG MOSFETs as a function of channel length for 45nm. Drain resistance is important for design of low-voltage, high frequency devices. It can be expressed as: r ds = It is observed that the drain-resistance in case of TG structure is lower than that of DG and SG structures. This is reliable with higher current drive capability of the TG structure. CONCLUSIONS In this work the triple-gate devices offer high current & reduced short-channel effects. Unlike classical single or double-gate MOSFET, these devices present a non-planner Silicon/gate oxide interface. At 45nm, the result shows that short-channel effect like Drain Induced Barrier Lowering (DIBL) and drain conductance are reduced to 21.67mV and

8 8 S Nandi & M Sarkar 7.20uS which is lesser in comparison to the DG and SG MOSFET. Therefore, in triple gate (TG) MOSFET the transconductance and voltage gain are increased to 81.47uS and respectively with respect to DG and SG MOSFET. We have a triple gate (TG) MOSFET. Since no work have been reported in this field of higher current drive capability for analytical modeling of triple gate (TG) MOSFET in best of our knowledge and few work have been reported in the area of fabrication of multiple gate MOSFETs, our results have shown good agreement with the analytical results which have been reported in past for triple gate (TG) silicon MOSFET [22, 28]. REFERENCES 1. F. Balestra, S. Christoloveanu, M. Benachir, and T. Elewa Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Lett., vol. 8, pp J. P. Colinge, M. H. Gao, A. R. Rodriguez, and C. Claeys Silicon-on-insulator gate-all-around device, Int. Electron Devices Meeting Tech.Dig., pp H. Horie, S. Ando, T. Tanaka, M. Imai, Y. Arimoto, and S. Hijiya Fabrication of double-gate thin-film SOI MOSFET s using wafer bonding and polishing, SSDM Tech. Dig., pp T. Tanaka, H. Horie, S. Ando, and S. Hijiya Analysis of p double-gate thin film SOI MOSFET s, Int. Electron Devices Meeting Tech. Dig., pp D. J. Frank, S. E. Laux, and M. V. Fischetti Monte Carlo simulation of a 30-nm dual-gate MOSFET: How short can Si go?, Int. Electron Devices Meeting Tech. Dig., pp S. Venkatesan, G. W. Neudeck, and R. F. Pierret, Jan Dual gate operation and volume inversion in n- channel SOI MOSFET s, IEEE Electron Device Lett., vol. 13, no. 1, pp K. Suzuki, S. Satoh, T. Tanaka, and S. Ando Analytical models for symmetric thin-film double-gate silicon-on-insulator metal oxide semiconductor field-effect transistors, Jpn. J. Appl. Phy., vol. 32, pp K. Suzuki, Y. Tosaka, T. Tanaka, H. Horie, and Y. Arimoto, Dec Scaling theory of double-gate SOI MOSFET s, IEEE Trans. Electron Devices, vol. 40, no. 12, pp K. Suzuki, Y. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, and T. Itoh, Analytical surface potential expression for thin-film double-gate SOI MOSFET s, Solid State Electron., vol. 37, pp T. Tosaka, K. Suzuki, H. Horie, and T. Sugii, Nov Scaling-parameter- dependent model for sub-threshold swing S in double-gate SOI MOSFET s, IEEE Electron Device Lett., vol. 15, no. 11, pp Tetsu Tanaka, Kunihiro Suzuki, Hiroshi Horie, and Toshihiro Sugii, Oct Ultrafast Operation of Vth- Adjusted p+-n+ Double-Gate SOI MOSFET's, IEEE Electron Device Lett., vol. 15, no. 10, pp K. Suzuki and T. Sugii, Nov Analytical models for n-p double gate SOI MOSFET s, IEEETrans. Electron Devices, vol. 42, no. 11, pp J. B. Roldan, F. Gamiz, J. A. Lopez-Villanueva, P. Cartujo, and J. E. Carceller, Oct Amodel for the drain current of deep submicrometer MOSFET s including electron-velocity overshoot, IEEE Trans. Electron Devices, vol. 45, no. 10, pp

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