LTC High Efficiency Bidirectional Multicell Battery Balancer APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Bidirectiona Synchronous Fyback Baancing of Up to 6 Li-Ion or LiFePO 4 Ces in Series n Up to 1A Baancing Current (Set by Externas) n Integrates Seamessy with the LT8x Famiy of Mutice Battery Stack Monitors n Bidirectiona Architecture Minimizes Baancing Time and Power Dissipation n Up to 92% Charge Transfer Efficiency n Stackabe Architecture Enabes >1V Systems n Uses Simpe 2-Winding Transformers n 1MHz Daisy-Chainabe Seria Interface with 4-Bit CRC Packet Error Checking n High Noise Margin Seria Communication n Numerous Faut Protection Features n 48-Lead Exposed Pad QFN and LQFP Packages APPLICATIONS n Eectric Vehices/Pug-in HEVs n High Power UPS/Grid Energy Storage Systems n Genera Purpose Mutice Battery Stacks L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and isospi is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. High Efficiency Bidirectiona Mutice Battery Baancer DESCRIPTION The LTC 33-1 is a faut-protected controer IC for transformer-based bidirectiona active baancing of mutice battery stacks. A associated gate drive circuitry, precision current sensing, faut detection circuitry and a robust seria interface with buit-in watchdog timer are integrated. Each can baance up to 6 series-connected battery ces with an input common mode votage up to 36V. Charge from any seected ce can be transferred at high efficiency to or from 12 or more adjacent ces. A unique eve-shifting SPI-compatibe seria interface enabes mutipe devices to be connected in series, without opto-coupers or isoators, aowing for baancing of every ce in a ong string of series-connected batteries. When mutipe devices are connected in series they can operate simutaneousy, permitting a ces in the stack to be baanced concurrenty and independenty. Faut protection features incude readback capabiity, cycic redundancy check (CRC) error detection, maximum on-time vot-second camps, and overvotage shutoffs. TYPICAL APPLICATION CHARGE SUPPLY (I CHARGE 1-6) High Efficiency Bidirectiona Baancing CHARGE RETURN (I DISCHARGE 1-6) CHARGE RETURN CHARGE SUPPLY NEXT CELL ABOVE I DISCHARGE I CHARGE CELL 12 CELL 7 CELL 6 CELL SERIAL DATA OUT TO ABOVE SERIAL DATA IN FROM BELOW CHARGE TRANSFER EFFICIENCY (%) Baancer Efficiency D64A DEMO BOARD I CHARGE = I DISCHARGE = 2.5A V CELL = 3.6V CHARGE DISCHARGE NUMBER OF CELLS (SECONDARY SIDE) 331 TA1b 331 TA1a NEXT CELL BELOW For more information 1

2 ABSOLUTE MAXIMUM RATINGS Tota Suppy Votage ( to )...36V Input Votage (Reative to ) C1....3V to 6V I1P....3V to.3v I1S, I2S, I3S, I4S, I5S, I6S....3V to.3v CSBI, SCKI, SDI....3V to 6V CSBO, SCKO, SDOI....3V to 36V V REG, SDO....3V to 6V RTONP, RTONS....3V to Min[V REG.3V, 6V] TOS, V MODE, CTRL, BOOST, WDT....3V to Min[V REG.3V, 6V] (Note 1) Votage Between Pins Cn to Cn-1*....3V to 6V InP to Cn-1*....3V to.3v BOOST to....3v to 6V CSBO to SCKO, CSBO to SDOI, SCKO to SDOI....3V to.3v SDO Current...1mA G1P, GnP, G1S, GnS, BOOST Current... ±2mA Operating Junction Temperature Range (Notes 2, 7) LTC33I C to 125 C LTC33H C to 15 C Storage Temperature Range C to 15 C *n = 2 to 6 PIN CONFIGURATION TOP VIEW 48 V REG 47 TOS 46 VMODE 45 CSBO 44 SCKO 43 SDOI 42 BOOST 41 BOOST 4 BOOST G6P 37 I6P TOP VIEW VREG TOS VMODE CSBO SCKO SDOI BOOST BOOST BOOST G6P I6P G6S 1 I6S 2 G5S 3 I5S 4 G4S 5 I4S 6 G3S 7 I3S 8 G2S 9 I2S 1 G1S 11 I1S G5P 34 I5P 33 C4 32 G4P 31 I4P 3 C3 29 G3P 28 I3P G2P 25 I2P G6S 1 I6S 2 G5S 3 I5S 4 G4S 5 I4S 6 G3S 7 I3S 8 G2S 9 I2S 1 G1S 11 I1S G5P 34 I5P 33 C4 32 G4P 31 I4P 3 C3 29 G3P 28 I3P G2P 25 I2P RTONS 13 RTONP 14 CTRL 15 CSBI 16 SCKI 17 SDI 18 SDO 19 WDT 2 21 I1P 22 G1P 23 C1 24 UK PACKAGE 48-LEAD (7mm 7mm) PLASTIC QFN T JMAX = 15 C, θ JA = 34 C/W, θ JC = 3 C/W EXPOSED PAD (PIN 49) IS, MUST BE SOLDERED TO PCB RTONS RTONP CTRL CSBI SCKI SDI SDO WDT I1P G1P C1 LXE PACKAGE 48-LEAD (7mm 7mm) PLASTIC LQFP T JMAX = 15 C, θ JA = 2.46 C/W, θ JC = 3.68 C/W EXPOSED PAD (PIN 49) IS, MUST BE SOLDERED TO PCB 2 For more information

3 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC33IUK-1#PBF LTC33IUK-1#TRPBF LTC33UK-1 48-Lead (7mm 7mm) Pastic QFN 4 C to 125 C LTC33HUK-1#PBF LTC33HUK-1#TRPBF LTC33UK-1 48-Lead (7mm 7mm) Pastic QFN 4 C to 15 C LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC33ILXE-1#PBF LTC33ILXE-1#PBF LTC33LXE-1 48-Lead (7mm 7mm) Pastic elqfp 4 C to 125 C LTC33HLXE-1#PBF LTC33HLXE-1#PBF LTC33LXE-1 48-Lead (7mm 7mm) Pastic elqfp 4 C to 15 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C. (Note 2) BOOST = 25.2V, = 21.6V, = 18V, C4 = 14.4V, C3 = 1.8V, = 7.2V, C1 = 3.6V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications I Q_SD Suppy Current When Not Baancing (Post Suspend or Pre Measured at C1,, C3, C4, Measured at First Execute) Measured at BOOST 7 1 I Q_ACTIVE Suppy Current When Baancing (Note 3) Baancing C1 Ony (Note 4 for,, ) Measured at C1 Measured at, C3, C4, Measured at Measured at BOOST Baancing Ony (Note 4 for C1, C3, ) Measured at C1 Measured at Measured at C3, C4, Measured at Measured at BOOST Baancing C3 Ony (Note 4 for, C4, ) Measured at C1, C4, Measured at Measured at C3 Measured at Measured at BOOST Baancing C4 Ony (Note 4 for C3,, ) Measured at C1,, Measured at C3 Measured at C4 Measured at Measured at BOOST Baancing Ony (Note 4 for C4, ) Measured at C1,, C3 Measured at C4 Measured at Measured at Measured at BOOST Baancing Ony (Note 4 for,, BOOST ) Measured at C1,, C3, C4 Measured at Measured at Measured at BOOST (BOOST = ) Measured at BOOST (BOOST = V REG ) For more information 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C. (Note 2) BOOST = 25.2V, = 21.6V, = 18V, C4 = 14.4V, C3 = 1.8V, = 7.2V, C1 = 3.6V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Q_EXTRA Suppy Current Extra (Seria I/O in Current Mode) Additiona Current Measured at, V MODE = (CSBI Logic Low, SCKI and SDI Both Logic High; Refer to I IL1, I IH1, I OH1, I OL1 Specs) 3.75 ma V CELL MIN Minimum Ce Votage (Rising) Required for Primary Gate Drive Cn to Cn 1 Votage to Baance Cn, n = 2 to 6 C1 Votage to Baance C1 Cn 1 to Cn Votage to Baance Cn, n = 1 to 5 BOOST to Votage to Baance, BOOST = V CELL MIN(HYST) V CELL MIN Comparator Hysteresis 7 mv V CELL MAX Maximum Ce Votage (Rising) C1, Cn to Cn 1 Votage to Baance Any Ce, V Before Disabing Baancing n = 2 to 6 V CELL MAX(HYST) V CELL MAX Comparator Hysteresis.5 V V CELL RECONNECT Maximum Ce Votage (Faing) to 4.25 V Re-Enabe Baancing V REG Reguator Pin Votage 9V 36V, ma I LOAD 2mA V V REG POR V REG Votage (Rising) for 4. V Power-On Reset V REG MIN Minimum V REG Votage (Faing) V REG Votage to Baance Cn, n = 1 to V for Secondary Gate Drive I REG_SC Reguator Pin Short Circuit Current V REG = V 55 ma Limit V RTONP RTONP Servo Votage R RTONP = 2kΩ V V RTONS RTONS Servo Votage R RTONS = 15kΩ V I WDT_RISING WDT Pin Current, Baancing R TONS = 15kΩ, WDT =.5V I WDT_FALLING WDT Pin Current as a Percentage of I WDT_RISING, Secondary OV R TONS = 15kΩ, WDT = 2V % V PEAK_P V PEAK_S V ZERO_P V ZERO_S Primary Winding Peak Current Sense Votage I1P InP to Cn 1, n = 2 to 6 V PEAK_P Matching (A 6) ±[(Max Min)/(Max Min)] 1% ±1.7 ±5 % Secondary Winding Peak Current Sense Votage I1S InS to Cn 1, n = 2 to 6, CTRL = Ony V PEAK_S Matching (A 6) ±[(Max Min)/(Max Min)] 1% ±.5 ±3 % Primary Winding Zero Current Sense Votage (Note 5) I1P InP to Cn 1, n = 2 to 6 V ZERO_P Matching (A 6) ±{[(Max Min)/2]/(V PEAK_P MIDRANGE )} 1% Normaized to Mid-Range V PEAK_P (Note 6) Secondary Winding Zero Current Sense Votage (Note 5) I1S InS to Cn 1, n = 2 to 6, CTRL = Ony V V V V mv mv mv mv mv mv ±1.7 ±5 % ±{[(Max Min)/2]/(V )} 1% V ZERO_S Matching (A 6) ±.5 ±3 % Normaized to Mid-Range V PEAK_S PEAK_S MIDRANGE (Note 6) R BOOST_L BOOST Pin Pu-Down R ON Measured at 1mA Into Pin, BOOST = V REG 2.5 Ω R BOOST_H BOOST Pin Pu-Up R ON Measured at 1mA Out of Pin, BOOST = V REG 4 Ω T SD Therma Shutdown Threshod Rising Temperature 155 C (Note 7) T HYS Therma Shutdown Hysteresis 1 C Timing Specifications t r_p Primary Winding Gate Drive Rise G1P Through G6P, C GATE = 25pF 35 7 ns Time (1% to 9%) t f_p Primary Winding Gate Drive Fa Time (9% to 1%) G1P Through G6P, C GATE = 25pF 2 4 ns mv mv 4 For more information

5 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C. (Note 2) BOOST = 25.2V, = 21.6V, = 18V, C4 = 14.4V, C3 = 1.8V, = 7.2V, C1 = 3.6V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t r_s t f_s t ONP MAX Secondary Winding Gate Drive Rise Time (1% to 9%) Secondary Winding Gate Drive Fa Time (9% to 1%) Primary Winding Switch Maximum On-Time G1S, C GATE = 25pF G2S Through G6S, CTRL = Ony, C GATE = 25pF G1S, C GATE = 25pF G2S Through G6S, CTRL = Ony, C GATE = 25pF R RTONP = 2kΩ (Measured at G1P-G6P) µs t ONP MAX Matching (A 6) ±[(Max Min)/(Max Min)] 1% ±1 ±4 % t ONS MAX Secondary Winding Switch R RTONS = 15kΩ (Measured at G1S-G6S) µs Maximum On-Time t ONS MAX Matching (A 6) ±[(Max Min)/(Max Min)] 1% ±1 ±4 % t DLY_START Deayed Start Time After New/ Different Baance Command or Recovery from Votage/Temp Faut 2 ms Votage Mode Timing Specifications t 1 SDI Vaid to SCKI Rising Setup Write Operation 1 ns t 2 SDI Vaid from SCKI Rising Hod Write Operation 25 ns t 3 SCKI Low 4 ns t 4 SCKI High 4 ns t 5 CSBI Puse Width 4 ns t 6 SCKI Rising to CSBI Rising 1 ns t 7 CSBI Faing to SCKI Rising 1 ns t 8 SCKI Faing to SDO Vaid Read Operation 25 ns f CLK Cock Frequency 1 MHz t WD1 Watchdog Timer Timeout Period WDT Assertion Measured from Last Vaid second Command Byte t WD2 Watchdog Timer Reset Time WDT Negation Measured from Last Vaid Command Byte µs Current Mode Timing Specifications t PD1 CSBI to CSBO Deay C CSBO = 15pF 6 ns t PD2 SCKI Rising to SCKO Deay C SCKO = 15pF 3 ns t PD3 SDI to SDOI Deay C SDOI = 15pF, Command Byte 3 ns t PD4 SCKI Faing to SDOI Vaid C SDOI = 15pF, Write Baance Command 3 ns t PD5 SCKI Faing to SDI Vaid C SDI = 15pF, Read Operation 3 ns t SCKO SCKO Puse Width C SCKO = 15pF 1 ns Votage Mode Digita I/O Specifications V IH Digita Input Votage High Pins CSBI, SCKI, SDI; V MODE = V REG Pins CTRL, BOOST, V MODE, TOS Pin WDT V IL Digita Input Votage Low Pins CSBI, SCKI, SDI; V MODE = V REG Pins CTRL, BOOST, V MODE, TOS Pin WDT I IH Digita Input Current High Pins CSBI, SCKI, SDI; V MODE = V REG Pins CTRL, BOOST, V MODE, TOS Pin WDT, Timed Out I IL Digita Input Current Low Pins CSBI, SCKI, SDI; V MODE = V REG Pins CTRL, BOOST, V MODE, TOS Pin WDT, Not Baancing V REG.5 V REG ns ns ns ns V V V V V V For more information 5

6 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating junction temperature range, otherwise specifications are at T A = 25 C. (Note 2) BOOST = 25.2V, = 21.6V, = 18V, C4 = 14.4V, C3 = 1.8V, = 7.2V, C1 = 3.6V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OL Digita Output Votage Low Pin SDO, Sinking 5; V MODE = V REG ; Read.3 V I OH Digita Output Current High Pin SDO at 6V 1 na Current Mode Digita I/O Specifications I IL1 Digita Input Current Low Pin CSBI; V MODE = Pin SCKI; V MODE = Pin SDI, V MODE =, Write Pin SDOI, TOS =, Read I IH1 Digita Input Current High Pin CSBI; V MODE = Pin SCKI; V MODE = Pin SDI, V MODE =, Write Pin SDOI, TOS =, Read I OH1 Digita Output Current High Pin CSBO; TOS = Pin SCKO; TOS = Pin SDOI, TOS =, Write Pin SDI, V MODE =, Read I OL1 Digita Output Current Low Pin CSBO; TOS = Pin SCKO; TOS = Pin SDOI, TOS =, Write Pin SDI, V MODE =, Read Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The is tested under pused oad conditions such that T J T A. The LTC33I-1 is guaranteed over the 4 C to 125 C operating junction temperature range and the LTC33H-1 is guaranteed over the 4 C to 15 C operating junction temperature. High junction temperatures degrade operating ifetimes; operating ifetime is derated for junction temperatures greater than 125 C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board ayout, the rated package therma impedance and other environmenta factors. The junction temperature (T J, in C) is cacuated from the ambient temperature (T A, in C) and power dissipation (P D, in Watts) according to the formua: T J = T A (P D θ JA ) where θ JA (in C/W) is the package therma impedance. Note 3: When baancing more than one ce at a time, the individua ce suppy currents can be cacuated from the vaues given in the tabe as foows: First add the appropriate tabe entries ce by ce for the baancers that are on. Second, for each additiona baancer that is on, subtract 7 from the resutant sums for C1,, C3, C4, and, and 45 from the resutant sum for. For exampe, if a six baancers are on, the resutant current for C1 is [ (7)] = 11 and for is [ (45)] = 129. Note 4: Dynamic suppy current is higher due to gate charge being deivered at the switching frequency during active baancing. See Gate Drivers/Gate Drive Comparators and Votage Reguator in the Operation section for more information on estimating these currents. Note 5: The zero current sense votages given in the tabe are DC threshods. The actua zero current sense votage seen in appication wi be coser to zero due to the sew rate of the winding current and the finite deay of the current sense comparator. Note 6: The mid-range vaue is the average of the minimum and maximum readings within the group of six. Note 7: This IC incudes overtemperature protection intended to protect the device during momentary overoad conditions. The maximum junction temperature may be exceeded when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may resut in device degradation or faiure. 6 For more information

7 TYPICAL PERFORMANCE CHARACTERISTICS I Q(SD) () Suppy Current When Not Baancing vs Temperature = 21.6V TEMPERATURE ( C) I Q(ACTIVE) /I Q(ACTIVE AT 25 C) Suppy Current When Baancing vs Temperature Normaized to 25 C 3.6V PER CELL MATCH CURVE WITH TABLE ENTRY TYP = 74 TYP = 56 TYP = 25 TYP = 7 TYP = 6 TYP = TEMPERATURE ( C) T A = 25 C uness otherwise specified. V CELL(MIN) (V) Minimum Ce Votage Required for Primary Gate Drive vs Temperature CELL VOLTAGE RISING CELL VOLTAGE FALLING TEMPERATURE ( C) 331 G1 331 G2 331 G3 V CELL(MAX) (V) Maximum Ce Votage to Aow Baancing vs Temperature V REG Load Reguation V REG Votage vs Temperature CELL VOLTAGE RISING CELL VOLTAGE FALLING TEMPERATURE ( C) V REG (V) T A = 25 C = 9V = 36V I VREG (ma) V REG (V) I VREG = 1mA = 36V = 9V TEMPERATURE ( C) LT1372 G1 331 G5 331 G6 V REG (V) V REG POR Votage and Minimum Secondary Gate Drive vs Temperature = 21.6V V REG RISING (POR) V REG FALLING (MIN SEC. GATE DRIVE TEMPERATURE ( C) G7 I VREG (ma) V REG Short-Circuit Current Limit vs Temperature = 21.6V TEMPERATURE ( C) 331 G8 For more information V RTONP, V RTONS (V) V RTONP, V RTONS vs Temperature V RTONP V RTONS TEMPERATURE ( C) 331 G9 7

8 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C uness otherwise specified. V RTONP, V RTONS (V) V RTONP, V RTONS vs Externa Resistance WDT Pin Current vs Temperature WDT Pin Current vs R TONS T A = 25 C V RTONS V RTONP 1 1 R TONP, R TONS RESISTANCE (kω) I WDT () R TONS = 15k BALANCING WDT =.5V SECONDARY OV WDT = 2V TEMPERATURE ( C) I WDT () BALANCING WDT =.5V SECONDARY OV WDT = 2V T A = 25 C R TONS (kω) 331 G1 331 G G12 V PEAK_P, V PEAK_S (mv) Peak Current Sense Threshod vs Temperature V CELL = 3.6V RANDOM CELL SELECTED PRIMARY SECONDARY V ZERO_P, V ZERO_S (mv) Zero Current Sense Threshod vs Temperature V CELL = 3.6V RANDOM CELL SELECTED PRIMARY SECONDARY t ONP(MAX) (µs) Primary Winding Switch Maximum On-Time vs Temperature R TONP = 2k V CELL = 3.6V TEMPERATURE ( C) 331 G TEMPERATURE ( C) 331 G TEMPERATURE ( C) 331 G15 t ONS(MAX) (µs) Secondary Winding Switch Maximum On-Time vs Temperature R TONS = 15k t ONP(MAX),t ONS(MAX) (µs) Maximum On-Time vs R TONP, R TONS T A = 25 C PRIMARY SECONDARY t WD1 (SECONDS) Watchdog Timer Timeout Period vs Temperature TEMPERATURE ( C) R TONP, R TONS (kω) TEMPERATURE ( C) 331 G G G18 8 For more information

9 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C uness otherwise specified. I OH1 () CSBO Digita Output Current High vs Temperature TOS = TEMPERATURE ( C) 331 G19 I OL1 () CSBO Digita Output Current Low vs Temperature TOS = TEMPERATURE ( C) 331 G2 CHARGE TRANSFER EFFICIENCY (%) Baancer Efficiency vs Ce Votage D64A DEMO BOARD I CHARGE = I DISCHARGE = 2.5A FOR 12-CELL STACK ONLY DISCHARGE, 12-CELL STACK DISCHARGE, 6-CELL STACK CHARGE, 6-CELL STACK CHARGE, 12-CELL STACK VOLTAGE PER CELL (V) 331 G Baance Current vs Ce Votage CHARGE, 12-CELL STACK I1S 5mV/DIV Typica Charge Waveforms I1P 5mV/DIV Typica Discharge Waveforms BALANCE CURRENT (A) DISCHARGE, 12-CELL STACK DISCHARGE, 6-CELL STACK D64A DEMO BOARD I CHARGE = I DISCHARGE = 2.5A FOR 12-CELL STACK ONLY CHARGE, 6-CELL STACK VOLTAGE PER CELL (V) I1P 5mV/DIV PRIMARY DRAIN 5V/DIV SECONDARY DRAIN 5V/DIV 2µs/DIV D64A DEMO BOARD I CHARGE = 2.5A T = 2 S = G23 I1S 5mV/DIV SECONDARY DRAIN 5V/DIV PRIMARY DRAIN 5V/DIV 2µs/DIV D64A DEMO BOARD I DISCHARGE = 2.5A T = 2 S = G24 C1 PIN 1V/DIV 331 G22 Protection for Broken Connection to Ce Whie Charging 3.6V ~5.2V CONNECTION TO C1 BROKEN SECONDARY STACK VOLTAGE 1V/DIV Protection for Broken Connection to Secondary Stack Whie Discharging 43.2V ~66V CONNECTION TO STACK BROKEN SCKI 5V/DIV I1P 5mV/DIV Changing Baancer Direction On the Fy CHARGING 2ms DISCHARGING G1P 2V/DIV BALANCING SHUTS OFF G1P 2V/DIV BALANCING SHUTS OFF G1P 2V/DIV 5µs/DIV 331 G25 5µs/DIV 331 G26 2µs/DIV 331 G27 For more information 9

10 PIN FUNCTIONS Note: The convention adopted in this data sheet is to refer to the transformer winding paraeing an individua battery ce as the primary and the transformer winding paraeing mutipe series-stacked ces as the secondary, regardess of the direction of energy transfer. G6S, G5S, G4S, G3S, G2S, G1S (Pins 1, 3, 5, 7, 9, 11): G1S through G6S are gate driver outputs for driving externa NMOS transistors connected in series with the secondary windings of transformers whose primaries are connected in parae with battery ces 1 through 6. For the minimum part count baancing appication empoying a singe transformer (CTRL = V REG ), G2S through G6S are no connects. I6S, I5S, I4S, I3S, I2S, I1S (Pins 2, 4, 6, 8, 1, 12): I1S through I6S are current sense inputs for measuring secondary winding current in transformers whose primaries are connected in parae with battery ces 1 through 6. For the minimum part count baancing appication empoying a singe transformer (CTRL = V REG ), I2S through I6S shoud be tied to. RTONS (Pin 13): Secondary Winding Max t ON Setting Resistor. The RTONS pin servos to 1.2V. A resistor to programs the maximum on-time for a externa NMOS transistors connected in series with secondary windings. This protects against a short-circuited current sense resistor in any secondary winding. To defeat this function, connect RTONS to V REG. The secondary winding OVP threshod (see WDT pin) is aso saved to the vaue of the R TONS resistor. RTONP (Pin 14): Primary Winding Max t ON Setting Resistor. The RTONP pin servos to 1.2V. A resistor to programs the maximum on-time for a externa NMOS transistors connected in series with primary windings. This protects against a short-circuited current sense resistor in any primary winding. To defeat this function, connect RTONP to V REG. CTRL: (Pin 15): Contro Input. The CTRL pin configures the for the minimum part count appication empoying a singe transformer if CTRL is tied to V REG or for the mutipe transformer appication if CTRL is tied to. This pin must be tied to either V REG or. CSBI (Pin 16): Chip Seect (Active Low) Input. The CSBI pin interfaces to a rai-to-rai output ogic gate if V MODE is tied to V REG. CSBI must be driven by the CSBO pin of another if V MODE is tied to. See Seria Port in the Appications Information section. SCKI (Pin 17): Seria Cock Input. The SCKI pin interfaces to a rai-to-rai output ogic gate if V MODE is tied to V REG. SCKI must be driven by the SCKO pin of another if V MODE is tied to. See Seria Port in the Appications Information section. SDI (Pin 18): Seria Data Input. When writing data to the, the SDI pin interfaces to a rai-to-rai output ogic gate if V MODE is tied to V REG or must be driven by the SDOI pin of another if V MODE is tied to. See Seria Port in the Appications Information section. SDO (Pin 19): Seria Data Output. When reading data from the, the SDO pin is an NMOS open-drain output if V MODE is tied to V REG. The SDO pin is not used if V MODE is tied to. See Seria Port in the Appications Information section. WDT (Pin 2): Watchdog Timer Output (Active High). At initia power-up and when not attempting to execute a vaid baance command, the WDT pin is high impedance and wi be pued high (internay camped to ~5.6V) if an externa pu-up resistor is present. Whie baancing (or attempting to baance but not abe to due to votage/temperature fauts) and during norma communication activity, the WDT pin is pued ow by a precision current source saved to the R TONS resistor. However, if no vaid command byte is written for 1.5 seconds (typica), the WDT output wi go back high. When WDT is high, a baancers are off. The watchdog timer function can be disabed by connecting WDT to. The secondary winding OVP function can aso be impemented using this pin (See Operation section). (Pin 21): Connect to the most negative potentia in the series of ces. I1P, I2P, I3P, I4P, I5P, I6P (Pins 22, 25, 28, 31, 34, 37): I1P through I6P are current sense inputs for measuring primary winding current in transformers connected in parae with battery ces 1 through 6. 1 For more information

11 PIN FUNCTIONS G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35, 38): G1P through G6P are gate driver outputs for driving externa NMOS transistors connected in series with the primary windings of transformers connected in parae with battery ces 1 through 6. C1,, C3, C4,, (Pins 24, 27, 3, 33, 36, 39): C1 through connect to the positive terminas of battery ces 1 through 6. Connect the negative termina of battery ce 1 to. BOOST (Pin 4): Boost Pin. Connects to the anode of the externa fying capacitor used for generating sufficient gate drive necessary for baancing the topmost battery ce in a given sub-stack. A Schottky diode from to BOOST is needed as we. Aternatey, the BOOST pin can connect to one ce up in the above sub-stack (if present). This pin is effectivey C7. (Note: Sub-stack refers to the 3-6 battery ces connected ocay to an individua as part of a arger stack.) BOOST (Pin 41): Boost Pin. Connects to the cathode of the externa fying capacitor used for generating sufficient gate drive necessary for baancing the topmost battery ce in a given sub-stack. Aternatey, if the BOOST pin connects to the next higher ce in the above sub-stack (if present), this pin is a no connect. BOOST (Pin 42): Enabe Boost Pin. Connect BOOST to V REG to enabe the boosted gate drive needed for baancing the top ce in a given sub-stack. If the BOOST pin can be connected to the next ce up in the stack (i.e., C1 of the next in the stack), then BOOST shoud be tied to and BOOST no connected. This pin must be tied to either V REG or. SDOI (Pin 43): Seria Data Output/Input. SDOI transfers data to and from the next IC higher in the daisy chain when writing and reading. See Seria Port in the Appications Information section. SCKO (Pin 44): Seria Cock Output. SCKO is a buffered and one-shotted version of the seria cock input, SCKI, when CSBI is ow. SCKO drives the next IC higher in the daisy chain. See Seria Port in the Appications Information section. CSBO (Pin 45): Chip Seect (Active Low) Output. CSBO is a buffered version of the chip seect input, CSBI. CSBO drives the next IC higher in the daisy chain. See Seria Port in the Appications Information section. V MODE (Pin 46): Votage Mode Input. When V MODE is tied to V REG, the CSBI, SCKI, SDI and SDO pins are configured as votage inputs and outputs. This means these pins accept V REG -referred rai-to-rai ogic eves. Connect V MODE to V REG when the is the bottom device in a daisy chain. When V MODE is tied to, the CSBI, SCKI and SDI pins are configured as current inputs and outputs, and SDO is unused. Connect V MODE to when the is being driven by another ower in the daisy chain. This pin must be tied to either V REG or. TOS (Pin 47): Top Of Stack Input. Tie TOS to V REG when the is the top device in a daisy chain. Tie TOS to when the is any other device in the daisy chain. When TOS is tied to V REG, the ignores the SDOI input. When TOS is tied to, the expects data to be passed to and from the SDOI pin. This pin must be tied to either V REG or. V REG (Pin 48): Linear Votage Reguator Output. This 4.8V output shoud be bypassed with a 1µF or arger capacitor to. The V REG pin is capabe of suppying up to 4mA to interna and externa oads. The V REG pin does not sink current. (Exposed Pad Pin 49): The exposed pad shoud be connected to a continuous (ground) pane biased at on the second ayer of the printed circuit board by severa vias directy under the. For more information 11

12 BLOCK DIAGRAM VOLTAGE REGULATOR 4mA MAX POR V REG BOOST BOOST 4.8V V REG BOOST THERMAL SD GATE DRIVE SHUTDOWN GENERATOR BOOST BOOST G6P CSBO SCKO SDOI 2 BALANCER CONTROLLER V REG 5mV/ /5mV I6P 37 I6S 2 LEVEL-SHIFTING SERIAL INTERFACE G6S 1 16 CRC/RCRC PACKET ERROR CHECKING DATA 12 STATUS 12 6-CELL SYNCHRONOUS FLYBACK CONTROLLER BALANCER PINS 3 TO 1, 25 TO SDO C1 24 G1P SDI 17 SCKI 16 CSBI WATCHDOG TIMER ACTIVE 2 BALANCER CONTROLLER V REG 5mV/ /5mV I1P 22 I1S 12 2 WDT RESET G1S V R TONS 5.6V MAX ON-TIME VOLT-SEC CLAMPS 21 EXPOSED PAD 49 TOS 47 V MODE 46 CTRL 15 RTONS 13 RTONP BD 12 For more information

13 TIMING DIAGRAM Timing Diagram of the Seria Interface t 1 t 2 t 4 t 3 t 6 t 7 SCKI SDI t 5 CSBI t 8 SDO 331 TD For more information 13

14 OPERATION Battery Management System (BMS) The mutice battery ce baancer is a key component in a high performance battery management system (BMS) for series-connected Li-Ion ces. It is designed to operate in conjunction with a monitor, a charger, and a microprocessor or microcontroer (see Figure 1). The function of the baancer is to efficienty transfer charge to/from a given out-of-baance ce in the stack from/to a arger group of neighboring ces (which incudes that individua ce) in order to bring that ce into votage or capacity baance with its neighboring ces. Ideay, this charge woud aways be transferred directy from/to the entire stack, but this is impractica for votage reasons when the number of ces in the overa stack is arge. The is designed to interface to a group of up to 6 series ces, so the number of ICs required to baance a series stack of N ces is N/6 rounded up to the nearest integer, with no imitation imposed on how arge N can be. For connecting an individua in the stack to fewer than 6 ces, refer to the Appications Information section. Because the baancing function entais switching arge (mutiampere) currents between ces, precision votage monitoring in the BMS is better served by a dedicated monitor component such as the LT83-1 or one of its famiy of parts. The LT83-1 provides for high precision A/D monitoring of up to 12 series ces. The ony votage monitoring provided by the is a coarse outof-range overvotage and undervotage ce baancing disquaification, which provides a safety shutoff in the event Kevin sensing to the monitor component is ost. In the process of bringing the ces into baance, the overa stack is sighty discharged. The charger component provides a means for net charging of the entire stack from an aternate power source. The ast component in the BMS is a microprocessor/ microcontroer which communicates directy with the baancer, monitor, and charger to receive votage, current, and temperature information and to impement a baancing agorithm. There is no singe baancing agorithm optima for a situations. For exampe, during net charging of the overa stack, it may be desirabe to discharge the highest votage ces first to avoid reaching termina charge on any ce before the entire stack is fuy charged. Simiary, during net discharging of the overa stack, it may be desirabe to charge the owest votage ces first to keep them from reaching a criticay ow eve. Other agorithms may prioritize fastest time to overa baance. The impements no agorithm for baancing the stack. Instead it provides maximum fexibiity by imposing no imitation on the agorithm impemented as a individua ce baancers can operate simutaneousy and bidirectionay. Unidirectiona Versus Bidirectiona Baancing Most baancers in use today empoy a unidirectiona (discharge ony) approach. The simpest of these operate by switching in a resistor across the highest votage ce(s) in the stack (passive baancing). No charge is recovered in this approach -instead it is dissipated as heat in the resistive eement. This can be improved by empoying an energy storage eement (inductive or capacitive) to transfer 14 For more information

15 OPERATION CN I CHARGE SERIAL COMMUNICATION TOP OF STACK CELL N C11 C12 I LOAD C4 BALANCER C3 C1 C4 C3 BALANCER C1 CELL N 1 C1 CELL N 2 C9 CELL N 3 C8 CELL N 4 C7 CELL N 5 LT83-1 MONITOR CELL N 6 CELL N 7 C4 CELL N 8 C3 CELL N 9 CELL N 1 C1 CELL N 11 CHARGER SERIAL COMMUNICATION SERIAL COMMUNICATION SERIAL COMMUNICATION C4 BALANCER C3 C1 C4 BALANCER C3 C1 CELL 12 CELL 11 CELL 1 CELL 9 CELL 8 CELL 7 CELL 6 CELL 5 CELL 4 CELL 3 CELL 2 CELL 1 C11 C1 C9 C8 C7 LT83-1 MONITOR C4 C3 C1 C12 V CC µp/µc V EE SERIAL COMMUNICATION BUS 331 F1 Figure 1. /LT83-1 Typica Battery Management System (BMS) For more information 15

16 OPERATION charge from the highest votage ce(s) in the stack to other ower votage ces in the stack (active baancing). This can be very efficient (in terms of charge recovery) for the case where ony a few ces in the overa stack are high, but wi be very inefficient (and time consuming) for the case where ony a few ces in the overa stack are ow. A bidirectiona active baancing approach, such as empoyed by the, is needed to achieve minimum baancing time and maximum charge recovery for a common ce capacity errors. Synchronous Fyback Baancer The baancing architecture impemented by the LTC33 1 is bidirectiona synchronous fyback. Each contains six independent synchronous fyback controers that are capabe of directy charging or discharging an individua ce. Baance current is scaabe with externa components. Each baancer operates independenty of the others and provides a means for bidirectiona charge transfer between an individua ce and a arger group of adjacent ces. Refer to Figure 2. Singe-Ce Discharge Cyce for Ce 1 Singe-Ce Charge Cyce for Ce 1 V CC I PEAK_PRI = 2A (I1P = 5mV) I PEAK_SEC = 2A (I1S = 5mV) I CHARGE I PRIMARY I SECONDARY V TOP_OF_STACK CELL N I LOAD 5µs 2A t ~417ns 2A t I SECONDARY CELL 13 I SECONDARY I PRIMARY I PRIMARY (48V) CELL 12 CELL V ~417ns t 52V 48V 5mV 5µs t 52V 48V V SECONDARY T:1 L PRI V PRIMARY (4V) CELL 1 V PRIMARY 4V 5mV t 4V V SECONDARY 5mV t G1S G1P 52V 48V 5mV 48V 52V 51.95V I1S I1P R SNS_SEC R SNS_PRI V SECONDARY V PRIMARY 5mV t 4V 5mV t 331 F2 4V Figure 2. Synchronous Fyback Baancing Exampe with T = 1, S = For more information

17 OPERATION Ce Discharging (Synchronous) When discharging is enabed for a given ce, the primary side switch is turned on and current ramps in the primary winding of the transformer unti the programmed peak current (I PEAK_PRI ) is detected at the InP pin. The primary side switch is then turned off, and the stored energy in the transformer is transferred to the secondary-side ces causing current to fow in the secondary winding of the transformer. The secondary-side synchronous switch is turned on to minimize power oss during the transfer period unti the secondary current drops to zero (detected at InS). Once the secondary current reaches zero, the secondary switch turns off and the primary-side switch is turned back on thus repeating the cyce. In this manner, charge is transferred from the ce being discharged to a of the ces connected between the top and bottom of the secondary side thereby charging the adjacent ces. In the exampe of Figure 2, the secondary-side connects across 12 ces incuding the ce being discharged. I PEAK_PRI is programmed using the foowing equation: I PEAK _PRI = 5mV R SNS_PRI Ce discharge current (primary side) and secondary-side charge recovery current are determined to first order by the foowing equations: I DISCHARGE = I PEAK _PRI 2 I SECONDARY = I PEAK _PRI 2 S S T 1 S T η DISCHARGE where S is the number of secondary-side ces, 1:T is the transformer turns ratio from primary to secondary, and η DISCHARGE is the transfer efficiency from primary ce discharge to the secondary side stack. Ce Charging When charging is enabed for a given ce, the secondaryside switch for the enabed ce is turned on and current fows from the secondary-side ces through the transformer. Once I PEAK_SEC is reached in the secondary side (detected at the InS pin), the secondary switch is turned off and current then fows in the primary side thus charging the seected ce from the entire stack of secondary ces. As with the discharging case, the primary-side synchronous switch is turned on to minimize power oss during the ce charging phase. Once the primary current drops to zero, the primary switch is turned off and the secondary-side switch is turned back on thus repeating the cyce. I PEAK_SEC is programmed using the foowing equation: I PEAK _SEC = 5mV R SNS_SEC Ce charge current and corresponding secondary-side discharge current are determined to first order by the foowing equations: I CHARGE = I PEAK _SEC 2 I SECONDARY = I PEAK _SEC 2 ST S T η CHARGE T S T where S is the number of secondary ces in the stack, 1:T is the transformer turns ratio from primary to secondary, and η CHARGE is the transfer efficiency from secondary-side stack discharge to the primary-side ce. Each baancer s charge transfer frequency and duty factor depend on a number of factors incuding I PEAK_PRI, I PEAK_SEC, transformer winding inductances, turns ratio, ce votage and the number of secondary-side ces. The frequency of switching seen at the gate driver outputs is given by: f DISCHARGE = f CHARGE = S S T V CELL L PRI I PEAK _PRI S S T V CELL L PRI I PEAK _SEC T where L PRI is the primary winding inductance. Figure 3 shows a fuy popuated appication empoying a six baancers. For more information 17

18 OPERATION BOOST.1µF BOOST 6.8Ω 1µF 1:1 UP TO CELL 12 G6P I6P G6S CELL 6 I6S 1µF 1:1 G5P I5P G5S CELL 5 I5S C4 C3 1µF 1:1 SERIAL COMMUNICATION RELATED PINS CSBO SCKO SDOI CSBI SCKI SDI SDO TOS V MODE WDT G2P I2P G2S I2S C1 1µF 1:1 CELL 2 V REG G1P I1P G1S CELL 1 BOOST I1S CTRL RTONP RTONS 1µF 22.6k 6.98k 331 F3 Figure 3. 6-Ce Active Baancer Modue Showing Power Connections for the Muti-Transformer Appication (CTRL = ) 18 For more information

19 OPERATION Baancing High Votage Battery Stacks TOP Baancing series connected batteries which contain >>12 ces in series requires intereaving of the transformer secondary connections in order to achieve fu stack baancing whie imiting the breakdown votage requirements of the primary- and secondary-side power FETs. Figure 4 shows typica intereaved transformer connections for a mutice battery stack in the generic sense, and Figure 5 for the specific case of an 18-ce stack. In these exampes, the secondary side of each transformer is connected to the top of the ce that is 12 positions higher in the stack than the bottom of the owest votage ce in each sub-stack. For the top most in the stack, it is not possibe to connect the secondary side of the transformer across 12 ces. Instead, it is connected to the top of the stack, or effectivey across ony 6 ces. Intereaving in this fashion aows charge to transfer between 6-ce sub-stacks throughout the entire battery stack. Max On-Time Vot-Sec Camps The contains programmabe faut protection camps which imit the amount of time that current is aowed to ramp in either the primary or secondary windings in the event of a shorted sense resistor. Maximum on time for a primary connections (active during ce discharging) and a secondary connections (active during ce charging) is individuay programmabe by connecting resistors from the R TONP and R TONS pins to according to the foowing equations: t ON(MAX) PRIMARY = 7.2µs R TONP 2kΩ t ON(MAX) SECONDARY = 1.2µs R TONS 15kΩ FROM CELL N-12 SECONDARY TO CELL 24 SEC SEC CELL N CELL N-6 POWER STAGES PRI CELL 12 CELL 7 POWER STAGES PRI PRI CELL 18 CELL 13 PRI CELL 6 CELL 5 CELL 4 CELL 3 POWER STAGES POWER STAGES SEC SEC For more information on seecting the appropriate maximum on-times, refer to the Appications Information section. To defeat this function, short the appropriate R TON pin(s) to V REG. CELL 2 CELL F4 For more information Figure 4. Diagram of Power Transfer Intereaving Through the Stack, Transformer Connections for High Votage Stacks 19

20 OPERATION.1µF 6.8Ω BOOST BOOST C1 TO TRANSFORMER SECONDARIES OF BALANCERS 14 TO 18 1:1 CELL 18 1µF G1P I1P CELL 13 G1S I1S BOOST V REG BOOST C1 TO TRANSFORMER SECONDARIES OF BALANCERS 8 TO 12 1:1 CELL 12 1µF G1P I1P CELL 7 G1S I1S BOOST BOOST C1 TO TRANSFORMER SECONDARIES OF BALANCERS 2 TO 6 1:1 CELL 6 1µF G1P I1P CELL 1 G1S I1S BOOST 331 F5 2 Figure Ce Active Baancer Showing Power Connections, Intereaved Transformer Secondaries and BOOST Rai Generation Up the Stack For more information

21 OPERATION Gate Drivers/Gate Drive Comparators A secondary-side gate drivers (G1S through G6S) are powered from the V REG output, puing up to 4.8V when on and puing down to when off. A primary-side gate drivers (G1P through G6P) are powered from their respective ce votage and the next ce votage higher in the stack (see Tabe 1). An individua ce baancer wi ony be enabed if its corresponding ce votage is greater than 2V and the ce votage of the next higher ce in the stack is aso greater than 2V. For the G6P gate driver output, the next higher ce in the stack is C1 of the next higher in the stack (if present) and is ony used if the boosted gate drive is disabed (by connecting BOOST = ). If the boosted gate drive is enabed (by connecting BOOST = V REG ), ony the ce votage is ooked at to enabe baancing of Ce 6. In the case of the topmost in the stack, the boosted gate drive must be enabed. The boosted gate drive requires an externa diode from to BOOST and a boost capacitor from BOOST to BOOST. For information on seecting these components, refer to the Appications Information section. Aso note that the dynamic suppy current referred to in Note 4 of the Eectrica Characteristics tabe adds to the termina currents of the pins indicated in the Votage When Off and Votage When On coumns of Tabe 1. The gate drive comparators have a DC hysteresis of 7mV. For improved noise immunity, the inputs are internay ow pass fitered and the outputs are fitered so as to not transition uness the interna comparator state is unchanged for 3µs to 6µs (typica). If insufficient gate drive is detected whie active baancing is in progress (perhaps, for exampe, if the stack is under heavy oad), the affected baancer(s) and ony the affected baancer(s) wi shut off. The baance command remains stored in memory, and active baancing wi resume where it eft off if sufficient gate drive is subsequenty restored. This can happen if, for exampe, the stack is being charged. Ce Overvotage Comparators In addition to sufficient gate drive being required to enabe baancing, there are additiona comparators which disabe a active baancing if any of the six individua ce votages is greater than 5V. These comparators have a DC hysteresis of 5mV. For improved noise immunity, the inputs are internay ow pass fitered and the outputs are fitered so as to not transition uness the interna comparator state is unchanged for 3µs to 6µs (typica). If any ce votage goes overvotage whie active baancing is in progress, a active baancers wi shut off. The baance command remains stored in memory, and active baancing wi resume where if eft off if the ce votage subsequenty comes back in range. These comparators wi protect the if a connection to a battery is ost whie baancing and the ce votage is sti increasing as a resut of that baancing. Tabe 1 DRIVER OUTPUT VOLTAGE WHEN OFF VOLTAGE WHEN ON GATE DRIVE REQUIRED TO ENABLE BALANCING G1P V- ( C1) 2V and (C1 ) 2V G2P C1 C3 (C3 ) 2V and ( C1) 2V G3P C4 (C4 C3) 2V and (C3 ) 2V G4P C3 ( C4) 2V and (C4 C3) 2V G5P C4 ( ) 2V and ( C4) 2V G6P If BOOST = V REG : BOOST (Generated) ( ) 2V If BOOST = : BOOST = C7* (C7* ) 2V and ( ) 2V *C7 is equa to C1 of the next higher in the stack if this connection is used. For more information 21

22 OPERATION Votage Reguator A inear votage reguator powered from creates a 4.8V rai at the V REG pin which is used for powering certain interna circuitry of the incuding a 6 secondary gate drivers. The V REG output can aso be used for powering externa oads, provided that the tota DC oading of the reguator does not exceed 4mA at which point current imit is imposed to imit on-chip power dissipation. The interna component of the DC oad current is dominated by the average gate driver current(s) (G1S through G6S), each approximated by C V f, where C is the gate capacitance of the externa NMOS transistor, V = V REG = 4.8V, and f is the frequency that the gate driver output is running at. FET manufacturers usuay specify the C V product as Q g (gate charge) measured in couombs at a given gate drive votage. The frequency, f, is dependent on many terms, primariy the votage of each individua ce, the number of ces in the secondary stack, the programmed peak baancing current, and the transformer primary and secondary winding inductances. In a typica appication, the C V f current oading the V REG output is expected to be ow singe-digit miiamperes per driver. Note that the V REG oading current is utimatey deivered from the pin. For appications invoving very arge baance currents and/or empoying externa NMOS transistors with very arge gate capacitance, the V REG output may need to source more than 4mA average. For information on how to design for these situations, refer to the Appications Information section. One additiona function saved to the V REG output is the power-on reset (POR). During initia power-up and subsequenty if the V REG pin votage ever fas beow approximatey 4V (e.g., due to overoading), the seria port is ceared to the defaut power-up state with no baancers active. This feature thus guarantees that the minimum gate drive provided to the externa secondary side FETs is aso 4V. For a 1µF capacitor oading the output at initia powerup, the output reaches reguation in approximatey 1ms. Therma Shutdown The has an overtemperature protection circuit which shuts down a active baancing if the interna siicon die temperature rises to approximatey 155 C. When in therma shutdown, a seria communication remains active and the ce baancer status (which contains temperature information) can be read back. The baance command which had been being executed remains stored in memory. This function has 1 C of hysteresis so that when the die temperature subsequenty fas to approximatey 145 C, active baancing wi resume with the previousy executing command. Watchdog Timer Circuit The watchdog timer circuit provides a means of shutting down a active baancing in the event that communication to the is ost. The watchdog timer initiates when a baance command begins executing and is reset to zero every time a vaid 8-bit command byte (see Seria Port Operation) is written. The vaid command byte can be an execute, a write, or a read (command or status). Partia reads and writes are considered vaid, i.e., it is ony necessary that the first 8 bits have to be written and contain the correct address. Referring to Figure 6a, at initia power-up and when not baancing, the WDT pin is high impedance and wi be pued high (internay camped to ~5.6V) if an externa pu-up resistor is present. Whie baancing and during norma communication activity, the WDT pin is pued ow by a precision current source equa to 1.2V/R TONS. (Note: if the secondary vot-second camp is defeated by connecting R TONS to V REG, the watchdog function is aso defeated.) If no vaid command byte is written for 1.5 seconds (typica), the WDT output wi go back high. When WDT is high, a baancers wi be shut down but the previousy executing baance command sti remains in memory. From this timed-out state, a subsequent vaid command byte wi reset the timer, but the baancers wi 22 For more information

23 OPERATION ony restart if an execute command is written. To defeat the watchdog function, simpy connect the WDT pin to. Pause/Resume Baancing (via WDT Pin) The WDT output pin doubes as a ogic input (TTL eves) which can be driven by an externa ogic gate as shown in Figure 6b (no watchdog), or by a PMOS/three-state ogic gate as shown in Figure 6c (with watchdog) to pause and resume baancing in progress. The externa pu-up must have sufficient drive capabiity to override the current source to ground at the WDT pin (=1.2V/R TONS ). Provided that the interna watchdog timer has not independenty timed out, externay puing the WDT pin high wi immediatey pause baancing, and it wi resume where it eft off when the pin is reeased. Secondary Winding OVP Function (via WDT pin) The precision current source pu-down on the WDT pin during baancing can be used to construct an accurate secondary winding OVP protection circuit as shown in Figure 6c. A second externa resistor, scaed to R TONS and connected to the transformer secondary winding, is used to set the comparator threshod. An NMOS cascode device (with gate tied to V REG ) is aso needed to protect WDT V REG R WDT V TH = 1.4V WDT V REG PAUSE/ RESUME ACTIVE 5.6V 1.2V R TONS RTONS R TONS 331 F6a ACTIVE 5.6V 1.2V R TONS RTONS R TONS 331 F6b (6a) Watchdog Timer Ony (WDT = to Defeat) (6b) Pause/Resume Baancing Ony TO TRANSFORMER SECONDARY WINDINGS R SEC_OVP V REG WDT V REG PAUSE/ RESUME EITHER/OR ACTIVE 5.6V 1.2V R TONS RTONS R TONS V REG V REG PAUSE/ RESUME 331 F6c (6c) Watchdog Timer with Pause/Resume Baancing and Secondary Winding OVP Protection Figure 6. WDT Pin Connection Options For more information 23

24 OPERATION the WDT pin from high votage. The secondary winding OVP threshods are given by: V SEC OVP(RISING) = 1.4V 1.2V (R SEC_OVP /R TONS ) V SEC OVP(FALLING) = 1.4V 1.5V (R SEC_OVP /R TONS ) This comparator wi protect the appication circuit if the secondary winding connection to the battery stack is ost whie baancing and the secondary winding votage is sti increasing as a resut of that baancing. The baance command remains stored in memory, and active baancing wi resume where it eft off if the stack votage subsequenty fas to a safer eve. Singe Transformer Appication (CTRL = V REG ) Figure 7 shows a fuy popuated appication empoying a six baancers with a singe shared custom transformer. In this appication, the transformer has six primary windings couped to a singe secondary winding. Ony one baancer can be active at a given time as a six share the secondary gate driver G1S and secondary current sense input I1S. The unused gate driver outputs G2S-G6S must be eft foating and the unused current sense inputs I2S-I6S shoud be connected to. Any baance command which attempts to operate more than one baancer at a time wi be ignored. This appication represents the minimum component count active baancer achievabe. SERIAL PORT OPERATION Overview The has an SPI bus compatibe seria port. Severa devices can be daisy chained in series. There are two sets of seria port pins, designated as ow side and high side. The ow side and high side ports enabe devices to be daisy chained even when they operate at different power suppy potentias. In a typica configuration, the positive power suppy of the first, bottom device is connected to the negative power suppy of the second, top device. When devices are stacked in this manner, they can be daisy chained by connecting the high side port of the bottom device to the ow side port of the top device. With this arrangement, the master writes to or reads from the cascaded devices as if they formed one ong shift register. The transates the votage eve of the signas between the ow side and high side ports to pass data up and down the battery stack. Physica Layer On the, seven pins comprise the ow side and high side ports. The ow side pins are CSBI, SCKI, SDI and SDO. The high side pins are CSBO, SCKO and SDOI. CSBI and SCKI are aways inputs, driven by the master or by the next ower device in a stack. CSBO and SCKO are aways outputs that can drive the next higher device in a stack. SDI is a data input when writing to a stack of devices. For devices not at the bottom of a stack, SDI is a data output when reading from the stack. SDOI is a data output when writing to and a data input when reading from a stack of devices. SDO is an open-drain output that is ony used on the bottom device of a stack, where it may be tied with SDI, if desired, to form a singe, bidirectiona port. The SDO pin on the bottom device of a stack requires a pu-up resistor. For devices up in the stack, SDO shoud be tied to the oca or eft foating. To communicate between daisy-chained devices, the high side port pins of a ower device (CSBO, SCKO and SDOI) shoud be connected through high votage diodes to the respective ow side port pins of the next higher device (CSBI, SCKI and SDI). In this configuration, the devices communicate using current rather than votage. To signa a ogic high from the ower device to the higher device, the ower device sinks a smaer current from the higher device pin. To signa a ogic ow, the ower device sinks a arger current. Likewise, to signa a ogic high from the higher device to the ower device, the higher device sources a arger current to the ower device pin. To signa a ogic ow, the higher device sources a smaer current. 24 For more information