LTC2938/LTC2939 Configurable 4- and 6-Supply Monitors with Watchdog Timer FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION

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1 Configurabe 4- and 6-Suppy Monitors with Watchdog Timer FEATURES n Simutaneousy Monitors Four (LTC2938) or Six Suppies (LTC2939) n Sixteen User-Seectabe Combinations of 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V and/or ± Adjustabe Votage Threshods n Guaranteed Threshod Accuracy: ±1.5% n Adjustabe Reset and Watchdog Timeout n Low Suppy Current: 80μA Typica n Power Suppy Gitch Immunity n Guaranteed for V CC > 1V n High Temperature Operation to 125 C n 12-Pin 4mm 3mm DFN or 12-Lead MSOP (LTC2938) and 16-Lead MSOP Package (LTC2939) APPLICATIONS n Desktop and Notebook Computers n Mutivotage Systems n Teecom Equipment n Network Servers n Automotive Contro Systems DESCRIPTION The LTC 2938/LTC2939 are confi gurabe suppy monitors for systems with up to four or six suppy votages that need watchdog supervision. One of sixteen preset or adjustabe votage monitor combinations can be seected using an externa resistive divider connected to the program input. The preset votage threshods are accurate to ±1.5% over temperature. The LTC2938 and LTC2939 aso feature adjustabe inputs with a 0.5V nomina threshod. The reset and watchdog timeout periods are adjustabe using externa capacitors. Tight votage threshod accuracy and gitch immunity ensure reiabe reset operation without fase triggering. The output is guaranteed to be in the correct state for V CC down to 1V. Each status output has a weak interna pu-up and may be externay pued up to a user-defined votage. The 80μA suppy current makes the LTC2938 and LTC2939 idea for power conscious systems. The LTC2939 monitors up to six suppies and the LTC2938 monitors up to four suppies. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents, incuding , , TYPICAL APPLICATION 12V 5V 3.3V 2.5V 1.8V 1.2V 6-Suppy Monitor 12V (ADJ), 5V, 3.3V, 2.5V, 1.8V, 1.2V (ADJ) 2150k 100k 124k 100k R1 59k R2 40.2k V5 V6 LTC2939 C WT V PG GND CWT CRT C RT SYSTEM LOGIC t = 94ms t WD = 940ms TA01 Votage Confi guration Tabe (V) (V) (V) (V) V5 (V) V6 (V) ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 1

2 ABSOLUTE MAXIMUM RATINGS,,,, V5, V6, V PG V to 7V V to 7V CWT, V to 7V CRT,, V to (V CC + 0.3V) Reference Load Current (I VREF )...±1mA Input Current ( ADJ Mode)... 1mA, Currents...±10mA (Notes 1, 2, 3) Operating Temperature Range LTC2939C... 0 C to 70 C LTC2939I C to 85 C LTC2939H C to 125 C Storage Temperature Range C to 150 C Lead Temperature (Sodering 10 sec) MS Package Ony C PIN CONFIGURATION LTC2938 LTC2938 LTC2939 TOP VIEW CRT V PG GND CWT DE PACKAGE 12-LEAD (4mm 3mm) PLASTIC DFN T JMAX = 125 C, θ JA = 43 C/W EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL CRT TOP VIEW MS PACKAGE 12-LEAD PLASTIC MSOP T JMAX = 125 C, θ JA = 130 C/W V PG GND CWT V5 NC CRT TOP VIEW MS PACKAGE 16-LEAD PLASTIC MSOP T JMAX = 125 C, θ JA = 110 C/W V6 NC V PG GND CWT ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2938CDE#PBF LTC2938CDE#TRPBF Lead (4mm 3mm) Pastic DFN 0 C to 70 C LTC2938IDE#PBF LTC2938IDE#TRPBF Lead (4mm 3mm) Pastic DFN 40 C to 85 C LTC2938HDE#PBF LTC2938HDE#TRPBF Lead (4mm 3mm) Pastic DFN 40 C to 125 C LTC2938CMS#PBF LTC2938CMS#TRPBF Lead Pastic MSOP 0 C to 70 C LTC2938IMS#PBF LTC2938IMS#TRPBF Lead Pastic MSOP 40 C to 85 C LTC2938HMS#PBF LTC2938HMS#TRPBF Lead Pastic MSOP 40 C to 125 C LTC2939CMS#PBF LTC2939CMS#TRPBF Lead Pastic MSOP 0 C to 70 C LTC2939IMS#PBF LTC2939IMS#TRPBF Lead Pastic MSOP 40 C to 85 C LTC2939HMS#PBF LTC2939HMS#TRPBF Lead Pastic MSOP 40 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifi cations, go to: 2

3 ELECTRICAL CHARACTERISTICS LTC2938/LTC2939 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C, V CC = 5V uness otherwise specified. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC Minimum Interna Operating Votage in Correct Logic State 1 V V CCMINP Minimum Required for Confi guration V CC Rising 2.6 V V RT50 5V, 5% Reset Threshod Input Threshod V V RT33 3.3V, 5% Reset Threshod, Input Threshod V V RT25 2.5V, 5% Reset Threshod, Input Threshod V V RT18 1.8V, 5% Reset Threshod,, Input Threshod V V RT15 1.5V, 5% Reset Threshod,, Input Threshod V V RT12 1.2V, 5% Reset Threshod,, Input Threshod V V RTA ADJ Reset Threshod,, V5, V6 Input Threshod mv V RTAN ADJ Reset Threshod Input Threshod mv Reference Votage V CC > 2.3V, I VREF = ±1mA, V C REF < 1000pF V PG Confi guration Votage Range V CC > V CCMINP 0 V I VPG V PG Input Current V PG = ±20 na I Input Current = 5V, I VREF = 12μA, (Note 4) μa I Input Current = 3.3V μa I Input Current = 2.5V = 0.55V (ADJ Mode) I Input Current = 1.8V = 0.55V (ADJ Mode) = -0.02V ( ADJ Mode) ± ±15 ±15 I V5, I V6 V5, V6 Input Current (LTC2939) V5, V6 = 0.55V ±15 na I CRT(UP) CRT Pu-Up Current V CRT = GND μa I CRT(DN) CRT Pu-Down Current V CRT = 1.3V μa t Reset Timeout Period C RT = 1500pF ms t UV V n Undervotage Detect to V n Less Than Reset Threshod V RTX by 150 μs More Than V OL Votage Output Low I SINK = 2.5mA; V CC = 3V V I SINK = 100μA; V CC = 1V V V OL Votage Output Low I SINK = 2.5mA; V CC = 3.3V V V OH Votage Output High, I SOURCE = 1μA; = 3.3V 1 V (Note 5) I CWT(UP) CWT Pu-Up Current V CWT = GND μa I CWT(DN) CWT Pu-Down Current V CWT = 1.3V μa t WD Watchdog Timeout Period C WT = 1500pF ms V Input Threshod (V CC = 3.3V to 5.5V) Logic Low Open Logic High V V V μa na μa na na 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C, V CC = 5V uness otherwise specified. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Input Current V = GND 30 μa V = 0.7V 10 μa V = 1.1V 10 μa V = 5V 30 μa t WP Input Puse Width V CC = 3.3V or 5.5V 2 μs Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A currents into pins are positive, a votages are referenced to GND uness otherwise noted. Note 3: The greater of, is the interna suppy votage (V CC ). Note 4: Under static no-faut conditions, wi necessariy suppy quiescent current. If at any time is arger than, must be capabe of suppying the quiescent current, programming (transient) current and reference oad current. Note 5: The outputs and have interna pu-ups to of typicay 6μA. However, externa pu-up resistors may be used when faster rise times are required or for V OH votages greater than. For configured to monitor 1.2V, 1.5V, 1.8V and 2.5V suppies, externa pu-up resistors are required to ensure that the output votage, high, is above the V IH input threshod of the externa circuit. TYPICAL PERFORMANCE CHARACTERISTICS NORMALIZED THRESHOLD VOLTAGES (V/V) Normaized Threshod Votages vs Temperature TEMPERATURE ( C) G01 THRESHOLD VOLTAGE, V RTAN (mv) ADJ Threshod Votage vs Temperature TEMPERATURE ( C) G02 (V) vs Temperature TEMPERATURE ( C) G03 4

5 TYPICAL PERFORMANCE CHARACTERISTICS LTC2938/LTC2939 SUPPLY CURRENT, I (μa) Suppy Current vs Temperature = 5V = 3.3V = 2.5V = 1.8V V5 = V6 = 1V I (A) 100μ 10μ 1μ 100n 10n 1n I() vs in ADJ mode 125 C 85 C 25 C TYPICAL TRANSIENT DURATION (μs) Transient Duration vs Comparator Overdrive RESET OCCURS ABOVE CURVE T A = 25 C TEMPERATURE ( C) G04 100p (mv) G RESET COMPARATOR OVERDRIVE (% OF V RTX ) G06 PULL-UP CURRENT (μa) Pu-Up Current vs 18 T A = 25 C V RT33 6 V RT25 V RT18 3 V RT15 V RT (V) OUTPUT VOLTAGE (V) Output Votage vs, V PG = GND T A = 25 C 10k PULL-UP FROM TO = (V) 5 WATCHDOG TIMEOUT PERIOD, t WD (ms) Watchdog Timeout Period vs Temperature C WT = 1500pF (SILVER MICA) TEMPERATURE ( C) G G G09 RESET TIMEOUT PERIOD, t (ms) Reset Timeout Period vs Temperature Watchdog Timeout Period vs C WT Reset Timeout Period vs C RT C RT = 1500pF (SILVER MICA) WATCHDOG TIMEOUT PERIOD t WD (s) m 10m 1m T A = 25 C RESET TIMEOUT PERIOD t (s) 10 T A = 25 C 1 100m 10m 1m 100μ TEMPERATURE ( C) G10 100μ 10p 100p 1n 10n 100n 1μ C WT (F) G11 10μ 10p 100p 1n 10n 100n 1μ C RT (F) G12 5

6 TYPICAL PERFORMANCE CHARACTERISTICS I SINK (ma) I SINK vs Suppy Votage () 15 T A = 25 C 12 V OL = 0.4V 9 V OL = 0.2V OR (V) V OL (mv) Votage Output Low vs Sink Current (, ) = 5V = 3V 25 C 85 C I SINK (ma) 40 C 125 C INPUT CURRENT, I (μa) Input Current vs Temperature V = 5V V = 1.1V V = 0V V = 0.7V TEMPERATURE ( C) G G G15 PULL-UP CURRENT (μa) Pu-Up Current vs T A = 25 C = GND INPUT THRESHOLD, V (V) Input Threshod vs Temperature HIGH OPEN (MAXIMUM) OPEN (MINIMUM) LOW (V) TEMPERATURE ( C) G G17 PIN FUNCTIONS CRT: Reset Timeout Capacitor. Attach an externa capacitor (C RT ) to GND to set a reset timeout of 2ms/nF. A capacitor generates a 94ms reset deay time. Leaving CRT unconnected generates a minimum timeout period of approximatey 20μs which wi vary depending on parasitic capacitance on the pin. CWT: Watchdog Timeout Capacitor. Attach a capacitor (C WT ) between CWT and GND to set a watchdog timeout period of 20ms/nF. A capacitor generates a 940ms watchdog timeout period. Leaving CWT unconnected generates a minimum timeout period of approximatey 200μs which 6

7 PIN FUNCTIONS wi vary depending on parasitic capacitance on the pin. Tie CWT to GND to disabe the watchdog function. GND: Device Ground. NC: No Interna Connection. : Reset Output. Logic output with weak 6μA pu-up to. Pus ow when any votage input is beow the reset threshod and hed ow for the confi gured reset deay time after a votage inputs are above threshod. When the watchdog timer is enabed but not serviced prior to the confi gured watchdog timeout period, pus ow for one reset deay time. May be pued to greater than using an externa pu-up. For confi gured to monitor 2.5V or beow, connect an externa pu-up resistor to the interface ogic suppy to ensure that the output high votage is above the V IH of the externa circuit. Leave open if unused. : Votage Input 1. Seect from 5V or 3.3V. See the Appications Information section for detais. The greater of or is aso V CC for the device. Bypass this input to ground with a (or greater) capacitor. : Votage Input 2. Seect from 3.3V, 2.5V, 1.8V, 1.5V or 1.2V. See the Appications Information section for detais. The greater of, is aso V CC for the device. Bypass this input to ground with a (or greater) capacitor. A status outputs are weaky pued up to. : Votage Input 3. Seect from 2.5V, 1.8V, 1.5V, 1.2V or ADJ. See the Appications Information section for detais. Tie to if unused. : Votage Input 4. Seect from 1.8V, 1.5V, 1.2V, ADJ or ADJ. See the Appications Information section for detais. Tie to if unused and confi gured for positive votage. V5: Adjustabe Votage Input 5 for LTC2939. High impedance comparator input with 0.5V typica threshod. Tie to if unused. V6: Adjustabe Votage Input 6 for LTC2939. High impedance comparator input with 0.5V typica threshod. Tie to if unused. LTC2938/LTC2939 V PG : Threshod Seect Input. Connect to an externa resistive divider between and GND to seect one of sixteen combinations of votage threshods (see Tabe 1). Do not add capacitance to the V PG input. : Buffered Reference Votage Output. A 1.210V nomina reference used for the mode seection votage (V PG ) and for the offset of negative adjustabe appications. The buffered reference can source and sink up to 1mA. The reference can drive a bypass capacitor of up to 1000pF without osciation. : Watchdog Input: A three-state input that contros the operation of the watchdog timer. Leaving the pin unconnected disabes the watchdog timer whie tying it ow or high enabes it. Whie is high, a transition between ow and high ogic eves (rising or faing edge) within the watchdog timeout period is required to inhibit from puing ow and a watchdog initiated reset. A capacitor attached to CWT sets the watchdog timeout period. A transition between the ow and high ogic eves on the input cears the votage on the CWT capacitor, preventing from going ow. Once is atched ow, must transition between ow and high ogic eves to cear Transitions between open and ogic ow or ogic high do not cear. : Watchdog Output. Logic output with weak 6μA puup to. May be pued greater than using externa pu-up. For confi gured to monitor 2.5V or beow, connect an externa pu-up resistor to the interface ogic suppy to ensure that the output high votage is above the V IH of the externa circuit. The watchdog timer is enabed when is high. The watchdog output pus ow if the watchdog timer expires and the output remains ow unti set high by the next transition or anytime an undervotage condition occurs. A watchdog faiure aso triggers a reset event. Leave open if unused. Exposed Pad (DE12 package ony): The Exposed Pad may be eft open or connected to device ground. 7

8 BLOCK DIAGRAM VREF BUFFER BANDGAP REFERENCE POWER DETECT V CC VPG A/D V5 RESISTIVE DIVIDERS WDFAIL ADJUSTABLE RESET PULSE GENERATOR 6μA + 0.5V LTC V6 CRT V CC 2μA 22μA 6μA GND TRANSITION DETECT 2μA UV WATCHDOG TIMER WDFAIL CWT V CC 22μA BD 8

9 TIMING DIAGRAM V n Monitor Timing Vn V RT t UV t TD01 Reset and Watchdog Timing V n t t t t t t t t WD t WD t WD t WD TD02 POWER-ON RESET FOLLOWED BY RESET CAUSED BY UNDERVOLTAGE EVENT. WATCHDOG OUTPUT SET HIGH, WATCHDOG INPUT = DON T CARE WATCHDOG INPUT NOT TOGGLED, WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT PULLS LOW. RESET OUTPUT PULLS LOW FOR ONE RESET TIMEOUT PERIOD. WATCHDOG INPUT REMAINS UNTOGGLED, WATCHDOG OUTPUT REMAINS LOW, RESET OUTPUT PULLS LOW AGAIN AFTER ONE WATCHDOG TIMEOUT PERIOD. WATCHDOG OUTPUT CLEARED BY UNDERVOLTAGE EVENT. WATCHDOG INPUT NOT TOGGLED, WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT PULLS LOW. RESET OUTPUT PULLS LOW. WATCHDOG OUTPUT LOW TIME SHORTENED BY UNDERVOLTAGE EVENT DURING RESET TIMEOUT. WATCHDOG INPUT NOT TOGGLED, WATCHDOG TIMER EXPIRES, WATCHDOG OUTPUT PULLS LOW. RESET OUTPUT PULLS LOW. WATCHDOG OUTPUT NOT CLEARED BY WATCHDOG INPUT DURING RESET TIMEOUT. AFTER RESET COMPLETED, WATCHDOG INPUT CLEARS WATCHDOG OUTPUT. 9

10 APPLICATIONS INFORMATION Suppy Monitoring The LTC2938 and LTC2939 are ow power, high accuracy confi gurabe four (LTC2938) and six (LTC2939) suppy monitoring circuits with reset output and watchdog functions. Both watchdog and reset timeouts are adjustabe using externa capacitors. Singe-pin configuration seects one of sixteen input votage monitor combinations. A four (LTC2938) or six (LTC2939) votage inputs must be above predetermined threshods for the reset not to be invoked. The LTC2938/LTC2939 assert the reset during power-up, power-down and brownout conditions on any one of the votage inputs. Power-Up The greater of or serves as the interna suppy votage (V CC ). On power-up, V CC powers the drive circuits for the output. This ensures that the output wi be ow as soon as or reaches 1V. The output remains ow unti the part is configured. After configuration, if any one of the suppy monitor inputs is beow its confi gured threshod, wi be at ogic ow. Once a the monitor inputs rise above their threshods, an interna timer is started and is reeased after the confi gured deay time. Threshod Accuracy Consider a 5V system with ±5% toerance. The 5V suppy may vary between 4.75V to 5.25V. System ICs powered by this suppy must operate reiaby within this band (and a itte more as subsequenty expained). A perfecty accurate supervisor for this suppy generates a reset at exacty 4.75V. However, no supervisor is perfect. The actua reset threshod of a supervisor varies over a specifi ed band. The LTC2938/LTC2939 varies ±1.5% around its nomina threshod votage (see Figure 1) over temperature. The reset threshod band and the power suppy toerance bands shoud not overap. This prevents fase or nuisance resets when the power suppy is actuay within its specified toerance band. The LTC2938 and LTC2939 have ±1.5% reset threshod accuracy, so a 5% threshod is typicay set to 6.5% beow the nomina input votage. Therefore, a typica 5V, 5% threshod is 4.675V. The threshod is guaranteed to ie in the band between 4.750V and 4.600V over temperature. The powered system must work reiaby down to the ow end of the threshod band, or risk mafunction before a reset signa is propery issued. 5V SUPPLY TOLERANCE NOMINAL SUPPLY VOLTAGE MINIMUM RELIABLE SYSTEM VOLTAGE IDEAL SUPERVISOR THRESHOLD ±1.5% THRESHOLD BAND 4.75V 4.675V 4.6V 5% 6.5% 8% REGION OF POTENTIAL MALFUNCTION F01 Figure % Threshod Accuracy Improves System Reiabiity 10

11 APPLICATIONS INFORMATION A ess accurate supervisor increases the required system votage margin and increases the probabiity of system mafunction. The LTC2938 and LTC2939 ±1.5% specification improves the reiabiity of the system over supervisors with wider threshod toerances. Monitor Confi guration Seect the LTC2938/LTC2939 input votage combination by pacing the recommended resistive divider from to GND and connect the tap point to V PG, as shown in Figure 2. Tabe 1 offers recommended resistor vaues for the various modes. The rightmost coumn in Tabe 1 specifi es optimum V PG / ratios (±0.01), when configuring with a ratiometric DAC. LTC2938/LTC2939 Upon power-up, the LTC2938 or LTC2939 enters a configuration period of approximatey 150μs during which the votage on the V PG input is samped and the monitor is configured to the desired input combination. Do not add capacitance to the V PG input. Immediatey after programming, the comparators are enabed and suppy monitoring begins. LTC2938/ LTC F02 V PG GND R1 R2 Figure 2. Monitor Programming Tabe 1. Votage Threshod Modes MODE (V) (V) (V) (V) R1 (kω) R2 (kω) V PG / ADJ ADJ Open Short ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ Short Open 1 11

12 APPLICATIONS INFORMATION Using the Adjustabe Threshods The reference inputs on the and/or comparators are set to 0.5V when the positive adjustabe modes are seected (Figure 3). The LTC2939 V5 and V6 comparators are aways in positive adjustabe mode with a 0.5V reference. The tap point on an externa resistive divider, connected between the positive votage being sensed and ground, is connected to the high impedance, adjustabe inputs (,, V5 and V6). Cacuate the trip votage from: R VTRIP = V R4 Figure 3. Setting the Positive Adjustabe Trip Point In the negative adjustabe mode, the high impedance, adjustabe input on the comparator is connected to ground (Figure 4). The tap point on an externa resistive divider, connected between the negative votage being sensed and the output, is connected to the high impedance adjustabe input (). provides the necessary eve shift required to operate at ground. The negative trip votage is cacuated from: V,, V5 OR V6 V TRIP R3 = V ; V = V Nomina R4 TRIP REF REF R4 R3 R3 R V LTC2938/LTC2939 LTC2938/LTC F03 In a negative adjustabe appication, the minimum vaue for R4 is imited by the sourcing capabiity of (±1mA). With no other oad on, R4 (minimum) is: V 1mA = k Tabes 2 and 3 offer suggested resistor vaues for various adjustabe appications assuming 5% monitor threshods. Tabe 2. Suggested Resistor Vaues for the ADJ Inputs V SUPPLY (V) V TRIP (V) R3 (kω) R4 (kω) Tabe 3. Suggested Resistor Vaues for the Negative ADJ Inputs V SUPPLY (V) V TRIP (V) R3 (kω) R4 (kω) Athough a of the suppy monitor comparators have buit-in gitch immunity, bypass capacitors on and are recommended because the greater of or is aso the suppy for the device. Fiter capacitors on the,, V5 and V6 inputs are aowed. V TRIP F04 12 Figure 4. Setting the Negative Adjustabe Trip Point

13 APPLICATIONS INFORMATION Power-Down On power-down, once any of the monitor inputs drops beow its threshod, is hed at a ogic ow. A ogic ow of 0.4V is guaranteed unti both and drop beow 1V. If the bandgap reference becomes invaid (V CC < 2V typica), the LTC2938/LTC2939 wi reconfigure when V CC rises above 2.4V (max). Seecting the Reset Timing Capacitor The reset timeout period is adjustabe in order to accommodate a variety of microprocessor appications. The reset timeout period, t, is adjusted by connecting a capacitor, C RT, between CRT and ground. The vaue of this capacitor is determined by: t pf CRT = = 500 t 2MΩ ms Leaving CRT unconnected generates a minimum reset timeout period of approximatey 20μs. The maximum reset timeout period is imited by the argest avaiabe ow eakage capacitor. The accuracy of the timeout period is affected by capacitor eakage (the nomina charging current is 2μA) and capacitor toerance. A ow eakage ceramic capacitor is recommended. Watchdog Timer The watchdog circuit typicay monitors a microprocessor s activity. The microprocessor is required to change the ogic state of the input on a periodic basis in order to cear the watchdog timer. Whenever an undervotage condition exists, the watchdog timer is ceared and is set high. The watchdog timer starts when pus high. Subsequent edges received on the input cear the watchdog timer. If unceared, the watchdog timer continues to run unti it times out. Once it times out, interna circuitry brings the and outputs ow. remains ow for at east one reset timeout period and can then be ceared by a new edge on the input or anytime an undervotage condition occurs. The watchdog timer may be disabed in three ways. One method is to simpy ground CWT. With CWT hed at ground, any undervotage event forces high indefinitey. A second method is to eave the input foating or in high LTC2938/LTC2939 impedance. The ast method is to continuousy drive between the ow and high threshods. Seecting the Watchdog Timing Capacitor The watchdog timeout period is adjustabe and can be optimized for software execution. The watchdog timeout period, t WD, is adjusted by connecting a capacitor, C WT, between CWT and ground. The vaue of this capacitor is determined by: t C WD pf WT = = 50 twd 20MΩ ms Leaving CWT unconnected generates a minimum watchdog timeout period of approximatey 200μs. The maximum watchdog timeout period is imited by the argest avaiabe ow eakage capacitor. The accuracy of the timeout period is affected by capacitor eakage (the nomina charging current is 2μA) and capacitor toerance. A ow eakage ceramic capacitor is recommended. Pu-Up Resistors for and The and pins provide weak pu-up currents to. This current is typicay greater than 6μA when is greater than 3.3V. The magnitude of the pu-up current decreases as decreases. For configured to monitor 2.5V, 1.8V, 1.5V and 1.2V suppies, externa pu-up resistors are required from both pins to the interface ogic suppy to ensure that the output high votage is above the V OH input threshod of the externa circuit. The and pins can be pued to votages higher than by externa pu-up resistors. Watchdog Appication Figure 5 shows a typica appication for the LTC2938/ LTC2939. The C WT timing capacitor adjusts the watchdog timeout period for optima software execution. If the software mafunctions and the state of the pin is unchanged before the end of the watchdog timeout period (t WD ), the LTC2938/LTC2939 pin is atched to a ow state. At the same time, is pued ow to reset the microprocessor. Whie is ow, the pin does not affect or. The system therefore resets for at east t. 13

14 APPLICATIONS INFORMATION After returns high, the microprocessor can po the state of the pin to determine if the reset was caused by an undervotage condition or by a watchdog timeout. high means that the reset was caused by undervotage since this condition aso resets the atch (and the watchdog timer). If the pin is ow, the system reset was caused by watchdog timeout. The microprocessor can then change the state of to cear the atch. If the microprocessor fais to do so, the LTC2938/ LTC2939 wi aternate between t and t WD timeout and wi be pued ow for t after every watchdog timeout. remains ow unti the microprocessor fips the state of. Some microprocessors force their I/O pins into high impedance during reset which in turn, foats the pin. This affects the response of the LTC2938/LTC2939. When the pin is foated, the watchdog timer is reset and C WT is discharged towards ground but remains unchanged. Putting in high impedance does not affect t. Once goes high again, and is driven from high impedence to a high or ow state, the watchdog timer starts a compete t WD timeout period. A high-to-ow or ow-to-high transition at cears if it was previousy atched ow. The and pins shoud not be tied together to generate the master reset signa since a watchdog timeout forces ow together with and the master reset signa wi remain ow indefinitey. 5V 3.3V 2.5V 1.8V 12V 1.2V 124k 2150k V5 V6 LTC2939 MICROPROCESSOR 100k 100k R1 59k R2 40.2k V PG GND CRT CWT C RT C WT t = 94ms t WD = 940ms F05 Figure 5. 6-Suppy Monitor, 12V (ADJ), 5V, 3.3V, 2.5V, 1.8V, 1.2V (ADJ) with Watchdog Enabed 14

15 TYPICAL APPLICATIONS Quad-Suppy Monitor (Mode 14) with Watchdog Disabed LTC2938/LTC2939 5V 3.3V 1.8V 12V V TRIP = 11.25V R3 2.15MΩ R4 100k R1 9.53k R2 93.1k V PG LTC2938 C RT GND CRT CWT SYSTEM LOGIC TA02 ±5V Suppy Monitor (Mode 1) with Watchdog Disabed and Unused Inputs Tied High 5V 5V V TRIP = 4.64V R3 464k R4 121k R1 93.1k R2 9.53k LTC2938 V PG GND CRT CWT C RT SYSTEM LOGIC TA03 15

16 TYPICAL APPLICATIONS Suppy and Temperature Monitor (Mode 1, 5V, 3.3V, 28V, 5.2V, 12V, 100 C) 5V 3.3V 10k 12V 2150k 28V 5110k 5.2V 467k RBIAS 93.1k RHYST 280k 121k R1 93.1k V5 V6 LTC2939 SYSTEM LOGIC 100k 100k RNTC* 470k R2 9.53k V PG GND CRT CWT C RT TA04 *PANASONIC ERTJOE74J Buffered to Power High Current Circuits 5V 3.3V 2.5V 1.8V 12V 1.2V 2150k 124k 100k 100k V5 V6 GND LTC2939 CRT C RT CWT V PG C WT MICROPROCESSOR R1 59k R2 40.2k + 5V LT V ±10mA TAO5 16

17 PACKAGE DESCRIPTION UE/DE Package 12-Lead Pastic DFN (4mm 3mm) (Reference LTC DWG # ) LTC2938/LTC PACKAGE OUTLINE BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED (2 SIDES) R = 0.05 TYP 7 R = TYP PIN 1 TOP MARK (NOTE 6) REF (2 SIDES) BSC 2.50 REF BOTTOM VIEW EXPOSED PAD PIN 1 NOTCH R = 0.20 OR CHAMFER (UE12/DE12) DFN 0806 REV D NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 17

18 PACKAGE DESCRIPTION MS Package 12-Lead Pastic MSOP (Reference LTC DWG # Rev Ø) ( ) 5.23 (.206) MIN ( ) ( ) TYP 0.65 (.0256) BSC RECOMMENDED SOLDER PAD LAYOUT ( ) (NOTE 3) ( ) REF (.010) DETAIL A 0 6 TYP ( ) ( ) (NOTE 4) GAUGE PLANE 0.18 (.007) DETAIL A ( ) SEATING PLANE 1.10 (.043) MAX (.034) REF ( ) TYP NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS (.0256) BSC MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX ( ) MSOP (MS12) 1107 REV Ø 18

19 PACKAGE DESCRIPTION LTC2938/LTC2939 MS Package 16-Lead Pastic MSOP (Reference LTC DWG # Rev Ø) ( ) 5.23 (.206) MIN ( ) ( ) TYP 0.50 (.0197) BSC RECOMMENDED SOLDER PAD LAYOUT ( ) (NOTE 3) ( ) REF (.010) DETAIL A 0 6 TYP ( ) ( ) (NOTE 4) GAUGE PLANE 0.18 (.007) DETAIL A NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE ( ) SEATING PLANE 1.10 (.043) MAX ( ) TYP (.0197) BSC 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF ( ) MSOP (MS16) 1107 REV Ø Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 19

20 TYPICAL APPLICATION Quad-Suppy Monitor (Mode 14) with Pushbutton Reset C RT 1μF SYSTEM LOGIC 1.8V 5V CRT LTC2938 V PG GND CWT 3.3V 1μF C WT R1 9.53k R2 93.1k R3 2.15MΩ R4 100k 10k* 12V V TRIP = 11.25V MANUAL RESET PUSHBUTTON TAO6 *OPTIONAL RESISTOR FOR ADDED ESD PROTECTION RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2900 Programmabe Quad-Suppy Monitor Adjustabe Reset, 10-Lead MSOP and DFN Packages LTC2901 Programmabe Quad-Suppy Monitor Adjustabe Reset and Watchdog Timer LTC2902 Programmabe Quad-Suppy Monitor Adjustabe Reset and Toerance LTC2908 Precision 6-Suppy Monitor (Four Fixed and Two Adjustabe) 8-Lead TSOT-23 and DFN Packages LTC2930 Confi gurabe 6-Suppy Monitor with Adjustabe Reset Timer, H-Grade Temperature Range, 3mm 3mm DFN-12 Package Manua Reset LTC2931 Confi gurabe 6-Suppy Monitor with Adjustabe Reset and Watchdog Timers H-Grade Temperature Range, Individua Suppy Comparator Outputs, TSSOP-20 Package LTC2932 Confi gurabe 6-Suppy Monitor with Individua Comparator Outputs Adjustabe Reset Timer and Toerance, Pin-Seectabe Toerance (5%, 7.5%, 10% or 12.5%), Reset Disabe for Margining, TSSOP-20 Package 20 LT 0709 PRINTED IN USA Linear Technoogy Corporation 1630 McCarthy Bvd., Mipitas, CA (408) FAX: (408) LINEAR TECHNOLOGY CORPORATION 2009

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