Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Charger APPLICATIONS TYPICAL APPLICATION

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1 FEATURES nn nn nn nn nn nn nn nn nn nn Dua Input, Singe Output DC/DCs with Input Prioritizer nn Energy Harvesting Input: 3. to 19 Buck DC/DC nn Battery Input: Up to 4.2 Buck-Boost DC/DC 1mA Shunt Battery Charger with Programmabe Foat otages: 3.45, 4., 4.1, 4.2 Low Battery Disconnect Utra Low Quiescent Current: 95nA at no Load Integrated Supercapacitor Baancer Up to 5mA of Output Current Programmabe DC/DC Output otage, Buck ULO, and Buck-Boost Peak Input Current Integrated Low-Loss Fu-Wave Bridge Rectifier Input Protective Shunt: Up to 25mA at IN 2 5mm 5mm QFN-32 Package APPLICATIONS nn nn nn Energy Harvesting Soar Powered Systems with Battery Backup Wireess HAC Sensors and Security Devices TYPICAL APPLICATION Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Charger DESCRIPTION The LTC 3331 integrates a high votage energy harvesting power suppy pus a buck-boost DC/DC powered from a rechargeabe battery to create a singe output suppy for aternative energy appications. A 1mA shunt aows simpe charging of the battery with harvested energy whie a ow battery disconnect function protects the battery from deep discharge. The energy harvesting power suppy, consisting of an integrated fu-wave bridge rectifier and a high votage buck DC/DC, harvests energy from piezoeectric, soar, or magnetic sources. Either DC/DC converter can deiver energy to a singe output. The buck operates when harvested energy is avaiabe, reducing the quiescent current draw on the battery to the 2nA required by the shunt charger, thereby extending the ife of the battery. The buck-boost powers OUT ony when harvested energy is unavaiabe. A supercapacitor baancer is aso integrated, aowing for increased energy storage. otage and current settings for both inputs and outputs are programmabe via pinstrapped ogic inputs. The is avaiabe in a 5mm 5mm QFN-32 package. nn Mobie Asset Tracking L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and PowerPath is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. + SOLAR PANEL + Li-Ion BATTERY 3 TO µF, 4.7µF 4.7µF 1k AC1 IN 1µF CAP IN2 CHARGE BB_IN BAT_OUT BAT_IN AC2 SW SWA SWB OUT SCAP BAL EH_ON PGOUT 2 FLOAT[1:] OUT[2:] 3 LBSEL IPK[2:] 3 SHIP U[3:] 4 GND IN3 22µH 22µH.1µF 1mF 2.7 1mF 2.7 OPTIONAL PIEZO MIDE 25W 1.8 TO 5 5mA 47µF OUT 5m/DI AC-COUPLED Charging a Battery with Harvested Energy EH_ON 4/DI I BB_IN 2mA/DI A A I CHARGE 1mA/DI BAT = 3.6 OUT = 1.8 I LOAD = 5mA ACTIE ENERGY HARESTER ENABLES CHARGING OF THE BATTERY IN SLEEP 1µs/DI 3331 TA1b 3331 TA1a 1

2 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Low Impedance Source....3 to 19* Current-Fed, I SW = A...25mA AC1, AC2... to IN BB_IN, OUT, IN3, BAT_IN, SCAP, PGOUT, CHARGE, SHIP....3 to 6 BAT_OUT....3 to [Lesser of (BAT_IN +.3) or 6] IN to [Lesser of ( IN +.3)] or 6 CAP... [Higher of.3 or ( IN 6)] to IN BAL....3 to (SCAP +.3) OUT[2:]....3 to [Lesser of ( IN3 +.3) or 6] IPK[2:]....3 to [Lesser of ( IN3 +.3) or 6] EH_ON....3 to [Lesser of ( IN3 +.3) or 6] FLOAT[1:]....3 to [Lesser of (BB_IN +.3) or 6] LBSEL....3 to [Lesser of (BB_IN +.3) or 6] U[3:]....3 to [Lesser of ( IN2 +.3) or 6] I AC1, I AC2...±5mA I SWA, I SWB, I OUT...35mA I SW...5mA Operating Junction Temperature Range (Notes 2, 3)... 4 C to 125 C Storage Temperature Range C to 15 C * IN has an interna 2 camp PIN CONFIGURATION BAL SCAP IN2 U3 U2 U1 U AC TOP IEW OUT2 OUT1 OUT EH_ON PGOUT CHARGE IN3 SHIP FLOAT 23 FLOAT1 22 LBSEL 33 GND 21 2 BAT_IN BAT_OUT 19 IPK2 18 IPK1 17 IPK AC2 IN CAP SW OUT SWB SWA BB_IN UH PACKAGE 32-LEAD (5mm 5mm) PLASTIC QFN T JMAX = 125 C, θ JA = 44 C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE EUH#PBF EUH#TRPBF Lead (5mm 5mm) Pastic QFN 4 C to 85 C IUH#PBF IUH#TRPBF Lead (5mm 5mm) Pastic QFN 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2

3 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C (Note 2). IN = 5, BAT_IN = BAT_OUT = BB_IN = 3.6, SHIP = O, SCAP = uness otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN Buck Input otage Range 19 BB_IN Buck-Boost Input otage Range (Note 7) I IN IN Quiescent Current IN Input in ULO IN Input in ULO Buck Enabed, Seeping Buck Enabed, Seeping Buck Enabed, Not Seeping I BB_IN BB_IN Quiescent Current (Note 6) BB_IN Input with IN Active Buck-Boost Enabed, Seeping Buck-Boost Enabed, Not Seeping IN = 2.5, BB_IN = IN = 16, BB_IN = IN = 4, BB_IN = IN = 18, BB_IN = IN = 5, BB_IN =, I SW = A (Note 4) BB_IN = 3.6, IN = 5 BB_IN = 3.6, IN = BB_IN = 3.6, IN =, I SWA = I SWB = A (Note 4) I OUT OUT Leakage Current 5 Output Seected, Seeping 1 15 na IN Undervotage Lockout Threshods 3 Leve Seected (Rising or Faing) 4 Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected Leve Seected SHUNT IN Shunt Reguator otage I IN = 1mA I SHUNT Maximum Protective Shunt Current 25 ma Interna Bridge Rectifier Loss ( AC1 AC2 IN ) Interna Bridge Rectifier Reverse Leakage Current Interna Bridge Rectifier Reverse Breakdown otage I BRIDGE = 1µA I BRIDGE = 5mA REERSE = 18 2 na I REERSE = 1µA SHUNT 3 na na na na µa na na µa m m 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C (Note 2). IN = 5, BAT_IN = BAT_OUT = BB_IN = 3.6, SHIP = O, SCAP = uness otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OUT Reguated Buck/Buck-Boost Output otage 1.8 Output Seected Seep Threshod Wake-Up Threshod 2.5 Output Seected Seep Threshod Wake-Up Threshod 2.8 Output Seected Seep Threshod Wake-Up Threshod 3. Output Seected Seep Threshod Wake-Up Threshod 3.3 Output Seected Seep Threshod Wake-Up Threshod 3.6 Output Seected Seep Threshod Wake-Up Threshod 4.5 Output Seected Seep Threshod Wake-Up Threshod 5. Output Seected Seep Threshod Wake-Up Threshod PGOUT Faing Threshod As a Percentage of OUT Target (Note 5) % I PEAK_BB Buck-Boost Peak Switch Current 25mA Target Seected ma 15mA Target Seected ma 1mA Target Seected ma 5mA Target Seected ma 25mA Target Seected ma 15mA Target Seected ma 1mA Target Seected ma 5mA Target Seected ma Avaiabe Buck-Boost Current I PEAK_BB = 25mA, OUT = ma Buck-Boost PMOS Input and Output Switch On-Resistance Buck-Boost NMOS Input and Output Switch On-Resistance IPK[2:] = 111 IPK[2:] = 11 IPK[2:] = 11 IPK[2:] = 1 IPK[2:] = 11 IPK[2:] = 1 IPK[2:] = 1 IPK[2:] = IPK2 = 1 IPK2 = Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω 4

5 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C (Note 2). IN = 5, BAT_IN = BAT_OUT = BB_IN = 3.6, SHIP = O, SCAP = uness otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PMOS Switch Leakage Buck/Buck-Boost Reguators 2 2 na NMOS Switch Leakage Buck/Buck-Boost Reguators 2 2 na Maximum Buck Duty Cyce Buck/Buck-Boost Reguators 1 % I PEAK_BUCK Buck Peak Switch Current ma Avaiabe Buck Output Current 1 ma Buck PMOS Switch On-Resistance 1.4 Ω Buck NMOS Switch On-Resistance 1.2 Ω Maximum Battery Shunt Current 1 ma I BAT_IN Battery Disconnect Leakage Current Battery Disconnected SHIP Mode Engaged FLOAT LBD LBC_BAT_IN LBC_BAT_ OUT Shunt Charger Foat otage (BAT_OUT otage) Low Battery Disconnect Threshod, BAT_IN otage (Faing) Low Battery Connect Threshod, BAT_IN otage (Rising) Low Battery Connect Threshod, BAT_OUT otage (Rising) FLOAT[1:] =, I BB_IN = 1mA FLOAT[1:] = 1, I BB_IN = 1mA FLOAT[1:] = 1, I BB_IN = 1mA FLOAT[1:] = 11, I BB_IN = 1mA FLOAT[1:] =, I BB_IN = 1mA FLOAT[1:] = 1, I BB_IN = 1mA FLOAT[1:] = 1, I BB_IN = 1mA FLOAT[1:] = 11, I BB_IN = 1mA LBSEL =, FLOAT[1:] =, I BAT_IN = 1mA LBSEL = 1, FLOAT[1:] =, I BAT_IN = 1mA LBSEL =, FLOAT[1:] = 1, 1, 11, I BAT_IN = 1mA LBSEL = 1, FLOAT[1:] = 1, 1, 11, I BAT_IN = 1mA LBSEL =, FLOAT[1:] =, I BAT_IN = 1mA LBSEL = 1, FLOAT[1:] =, I BAT_IN = 1mA LBSEL =, FLOAT[1:] = 1, 1, 11, I BAT_IN = 1mA LBSEL = 1, FLOAT[1:] = 1, 1, 11, I BAT_IN = 1mA LBSEL =, FLOAT[1:] = LBSEL = 1, FLOAT[1:] = LBSEL =, FLOAT[1:] = 1, 1, 11 LBSEL = 1, FLOAT[1:] = 1, 1, Battery Disconnect PMOS On-Resistance BAT_IN = 3.3, I BAT_IN = 1mA 5 Ω Charge Pin Current Current Out of CHARGE Pin 1 2 ma ma CHARGE Pin otage PMOS On-Resistance 2mA Out of CHARGE Pin 6 Ω SCAP Supercapacitor Baancer Input Range I SCAP Supercapacitor Baancer Quiescent Current SCAP = na Supercapacitor Baancer Source SCAP = 5., BAL = ma Current Supercapacitor Baancer Sink Current SCAP = 5., BAL = ma na na 5

6 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C (Note 2). IN = 5, BAT_IN = BAT_OUT = BB_IN = 3.6, SHIP = O, SCAP = uness otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS BAL Supercapacitor Baance Point Percentage of SCAP otage % IH Digita Input High otage Pins: OUT[2:], SHIP, FLOAT[1:], LBSEL, IPK[2:], 1.2 U[3:] IL Digita Input Low otage Pins: OUT[2:], SHIP, FLOAT[1:], LBSEL, IPK[2:],.4 U[3:] I IH Digita Input High Current Pins: OUT[2:], SHIP, FLOAT[1:], LBSEL, IPK[2:], 1 na U[3:] I IL Digita Input Low Current Pins: OUT[2:], SHIP, FLOAT[1:], LBSEL, IPK[2:], 1 na U[3:] OH PGOUT, Output High otage EH_ON Output High otage BB_IN = 5, 1µA Out of Pin IN = 6, 1µA Out of Pin OL PGOUT, EH_ON Output Low otage BB_IN = 5, 1µA into Pin.4 Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The is tested under pused oad conditions such that T J T A. The E is guaranteed to meet specifications from C to 85 C. The I is guaranteed over the 4 C to 125 C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board ayout, the rated package therma impedance and other environmenta factors. Note 3: T J is cacuated from the ambient T A and power dissipation PD according to the foowing formua: T J = T A + (P D θ JA ). Note 4: Dynamic suppy current is higher due to gate charge being deivered at the switching frequency. Note 5: The PGOUT Rising threshod is equa to the seep threshod. See OUT specification. Note 6: These quiescent currents incude the contribution from the interna resistor divider at the BAT_OUT pin as BAT_OUT must be tied to BB_IN for a appications. Note 7: The buck-boost operating votage is further constrained to a narrower range by the programmed foat votage and the seected ow battery disconnect and connect threshods. TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. I IN (na) IN Quiescent Current in ULO vs IN 25 C 125 C 4 C 85 C IN () G1 I IN (na) IN Quiescent Current in Seep vs IN 125 C 25 C 85 C IN () 4 C G2 I BB_IN (na) Buck-Boost Quiescent Current in Seep vs BB_IN BAT_OUT TIED TO BB_IN 125 C 85 C 25 C 4 C BB_IN () 3331 G3 6

7 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. I OUT (na) OUT Quiescent Current vs Temperature OUT IN REGULATION, SLEEPING PERCENTAGE OF TARGET SETTING (%) ULO Threshod vs Temperature APPLIES TO EACH ULO SETTING SHUNT () SHUNT vs Temperature I SHUNT = 25mA 2. I SHUNT = 1mA G G G6 BRIDGE DROP (m) OUT () Tota Bridge Rectifier Drop vs Bridge Current Bridge Leakage vs Temperature Bridge Frequency Response AC1 AC2 IN 85 C 25 C 125 C 4 C 1µ 1µ 1µ 1m 1m BRIDGE CURRENT (A) G7 BRIDGE LEAKAGE (na) 2 IN = 18, LEAKAGE AT AC1 OR AC G8 IN () P-P APPLIED TO AC1/AC2 INPUT 1.8 MEASURED IN ULO k 1k 1k 1M 1M 1M FREQUENCY (Hz) 1.8 Output vs Temperature 2.5 Output vs Temperature 2.8 Output vs Temperature 25 SLEEP THRESHOLD WAKE-UP THRESHOLD PGOUT FALLING G1 OUT () SLEEP THRESHOLD WAKE-UP THRESHOLD PGOUT FALLING G11 OUT () SLEEP THRESHOLD WAKE-UP THRESHOLD PGOUT FALLING G G12 7

8 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. OUT () Output vs Temperature 3.3 Output vs Temperature 3.6 Output vs Temperature SLEEP THRESHOLD WAKE-UP THRESHOLD PGOUT FALLING OUT () 3.35 SLEEP THRESHOLD 3.3 WAKE-UP THRESHOLD PGOUT FALLING OUT () 3.65 SLEEP THRESHOLD 3.6 WAKE-UP THRESHOLD PGOUT FALLING G G G15 OUT () 4.5 Output vs Temperature 5 Output vs Temperature SLEEP THRESHOLD WAKE-UP THRESHOLD PGOUT FALLING OUT () 5.1 SLEEP THRESHOLD 5. WAKE-UP THRESHOLD PGOUT FALLING G G17 I PEAK_BB (ma) Buck-Boost Peak Current vs Temperature, 25mA I PEAK Setting 25 BB_IN = G18 I PEAK_BB (ma) Buck-Boost Peak Current vs Temperature, 5mA I PEAK Setting BB_IN = 3.6 R DS(ON) (Ω) R DS(ON) of Buck-Boost PMOS/NMOS vs Temperature, 25mA I PEAK Setting PMOS, BB_IN = 2.1 NMOS, BB_IN = 2.1 PMOS, BB_IN = 4.2 NMOS, BB_IN = 4.2 R DS(ON) (Ω) R DS(ON) of Buck-Boost PMOS/NMOS vs Temperature, 5mA I PEAK Setting PMOS, BB_IN = 2.1 NMOS, BB_IN = 2.1 PMOS, BB_IN = 4.2 NMOS, BB_IN = G G G21 8

9 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. IPEAK_BUCK (ma) OUT () Buck Peak Current vs Temperature 25 IN = G22 RDS(ON) (Ω) R DS(ON) of Buck PMOS/NMOS vs Temperature IN = 5 25 PMOS Buck-Boost Load Reguation, OUT = 3.3 Buck-Boost Line Reguation, OUT = 3.3 Buck-Boost Switching Waveforms Buck Load Reguation, 3.3 C OUT = 1µF L = 22µH IPK[2:] = 111 LOAD = 1mA LOAD = 5mA BB_IN () G25 OUTPUT OLTAGE 5m/DI AC-COUPLED SWA OLTAGE 2/DI SWB OLTAGE 2/DI INDUCTOR CURRENT 2mA/DI ma NMOS 8µs/DI BAT = 2.1, OUT = 3.3 I LOAD = 1mA L = 22µH, C OUT = 1µF G G26 OUT () OUT () µ 1µ C OUT = 1µF L = 22µH IPK[2:] = 111 IN = 4 C OUT = 1µF L = 22µH 1µ 1m 1m 1m I LOAD (A) BB_IN = 4.1 BB_IN = G µ 1µ 1µ 1m 1m 1m I LOAD (A) 3331 G27 OUT () Buck Line Reguation, LOAD = 1mA LOAD = 1mA C OUT = 1µF L = 22µH IN () G28 OUTPUT OLTAGE 5m/DI AC-COUPLED SW OLTAGE 1/DI Buck Switching Waveforms INDUCTOR CURRENT 2mA/DI ma 8µs/DI IN = 18, OUT = 3.3 I LOAD = 1mA L = 22µH, C OUT = 1µF 3331 G29 OUTPUT OLTAGE 5m/DI DC-COUPLED, OFFSET = 3.3 EH_ON 5/DI Prioritizer Buck to Buck-Boost Transition BUCK INDUCTOR CURRENT 2mA/DI BUCK-BOOST ma INDUCTOR CURRENT 2mA/DI ma 1µs/DI 3331 G3 IN TRANSITIONS 18 TO 17, U[3:] = 111 BB_IN = 4.1, OUT = 3.3 I LOAD = 5mA, C OUT = 1µF, L BUCK = 22µH, L BUCK-BOOST = 22µH 9

10 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. OUTPUT OLTAGE 2m/DI AC-COUPLED LOAD CURRENT 25mA/DI Buck-Boost Load Step Response 1mA 2ms/DI BB_IN = 3, OUT = 3.3 C OUT = 1µF, L = 22µH LOAD STEP FROM 1mA TO 5mA 3331 G31 OUTPUT OLTAGE 2m/DI AC-COUPLED LOAD CURRENT 25mA/DI Buck Load Step Response 1mA 2ms/DI IN = 18, OUT = 3.3 C OUT = 1µF, L = 22µH LOAD STEP FROM 1mA TO 5mA 3331 G32 OUTPUT OLTAGE 5m/DI DC-COUPLED, OFFSET = 3.3 Prioritizer Buck-Boost to Buck Transition EH_ON 5/DI BUCK INDUCTOR CURRENT 2mA/DI ma BUCK-BOOST INDUCTOR CURRENT ma 2mA/DI 1µs/DI IN TRANSITIONS 17 TO 18, U[3:] = 111 BB_IN = 4.1, OUT = 3.3 I LOAD = 5mA, C OUT = 1µF, L BUCK = 22µH, L BUCK-BOOST = 22µH 3331 G33 EFFICIENCY (%) Buck Efficiency vs I LOAD 3 OUT = 1.8 OUT = OUT = OUT = 5 IN = 6, L = 22µH, DCR =.19Ω 1µ 1µ 1µ 1m 1m 1m I LOAD (A) 3331 G34 EFFICIENCY (%) Buck Efficiency vs IN for I LOAD = 1mA, L = 22µH OUT = 1.8 OUT = 2.5 OUT = 2.8 OUT = 3 OUT = 3.3 OUT = 3.6 OUT = 4.5 OUT = 5 DCR =.19Ω IN () 3331 G35 EFFICIENCY (%) Buck Efficiency vs IN for I LOAD = 1mA, L = 1µH OUT = 1.8 OUT = 2.5 OUT = 2.8 OUT = 3 OUT = 3.3 OUT = 3.6 OUT = 4.5 OUT = 5 DCR =.45Ω IN () 3331 G36 EFFICIENCY (%) Buck Efficiency vs IN, for OUT = L = 22µH, DCR =.19Ω I LOAD = 1mA I LOAD =1µA I LOAD =2µA I LOAD =1µA 1 I LOAD =5µA I LOAD =5µA I LOAD =3µA IN () 3331 G37 EFFICIENCY (%) Buck-Boost Efficiency vs I LOAD, 25mA I PEAK Setting 2 BAT = L = 22µH R L =.36Ω 1µ 1µ 1µ 1m I LOAD (A) OUT = 1.8 OUT = 2.5 OUT = 3.3 OUT = 5. 1m 3331 G39 EFFICIENCY (%) µ Buck-Boost Efficiency vs I LOAD, 5mA I PEAK Setting BAT = 3.6 L = 22µH DCR = 5.1Ω OUT = 1.8 OUT = 2.5 OUT = 3.3 OUT = 5. 1µ 1µ 1m I LOAD (A) 3331 G38 1

11 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. 1 9 Buck-Boost Efficiency vs BB_IN for OUT = 1.8, 25mA I PEAK Setting L = 22µH DCR =.36Ω 1 9 Buck-Boost Efficiency vs BB_IN for OUT = 3.3, 25mA I PEAK Setting L = 22µH DCR =.36Ω 1 9 Buck-Boost Efficiency vs BB_IN for OUT = 5, 25mA I PEAK Setting L = 22µH DCR =.36Ω EFFICIENCY (%) I LOAD = 5mA I LOAD = 1µA I LOAD = 5µA I LOAD = 2µA I LOAD = 1µA I LOAD = 5µA BB_IN () EFFICIENCY (%) I LOAD = 5mA I LOAD = 1µA I LOAD = 5µA I LOAD = 2µA I LOAD = 1µA I LOAD = 5µA BB_IN () EFFICIENCY (%) I LOAD = 5mA I LOAD = 1µA I LOAD = 5µA I LOAD = 2µA I LOAD = 1µA I LOAD = 5µA BB_IN () 3331 G G G Buck-Boost Efficiency vs BB_IN for OUT = 1.8, 5mA I PEAK Setting L = 1µH DCR = 5.1Ω 1 9 Buck-Boost Efficiency vs BB_IN for OUT = 3.3, 5mA I PEAK Setting L = 1µH DCR = 5.1Ω 1 9 Buck-Boost Efficiency vs BB_IN for OUT = 5, 5mA I PEAK Setting L = 1µH DCR = 5.1Ω EFFICIENCY (%) I LOAD = 1mA I LOAD = 1µA I LOAD = 5µA I LOAD = 2µA I LOAD = 1µA I LOAD = 5µA BB_IN () EFFICIENCY (%) I LOAD = 1mA I LOAD = 1µA I LOAD = 5µA I LOAD = 2µA I LOAD = 1µA I LOAD = 5µA BB_IN () EFFICIENCY (%) I LOAD = 1mA I LOAD = 1µA I LOAD = 5µA I LOAD = 2µA I LOAD = 1µA I LOAD = 5µA BB_IN () 3331 G G G45 FLOAT OLTAGE () Foat otage vs Temperature 3.65 IBB_IN = 1mA FLOAT OLTAGE () 4, 4.1, 4.2 Foat otage vs Temperature 4.3 IBB_IN = 1mA FLOAT OLTAGE DEIATION (m) Shunt Foat otage Load Reguation ALL FLOAT SETTINGS IN SLEEP µ 1µ 1µ 1m 1m I BB_IN (A) 3331 G G G48 11

12 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. PMOS BODY DIODE DROP (m) Disconnect PMOS Body Diode Drop vs Current 4 C 25 C 85 C 125 C 1µ 1µ 1µ 1m 1m I D (A) 3331 G49 BAT_IN OLTAGE () Battery Connect otage at BAT_IN vs I BAT_OUT , 4.1, 4.2 FLOAT, LBSEL = , 4.1, 4.2 FLOAT, LBSEL = FLOAT, LBSEL = FLOAT, LBSEL = µ 1µ 1µ 1m 1m I BAT_OUT (A) 3331 G51 BAT_OUT OLTAGE () Battery Connect otage at BAT_OUT vs I BAT_OUT , 4.1, 4.2 FLOAT, LBSEL = 1 4., 4.1, 4.2 FLOAT, LBSEL = FLOAT, LBSEL = FLOAT, LBSEL = 1µ 1µ 1µ 1m 1m I BAT_OUT (A) 3331 G52 R DS(ON) (Ω) R DS(ON) of Disconnect PMOS vs Temperature BAT_IN = 2.1 BAT_IN = 3.1 BAT_IN = 4.1 BAT_IN OLTAGE () Battery Disconnect otage at BAT_IN vs I BAT_IN 4., 4.1, 4.2 FLOAT, LBSEL = 1 4., 4.1, 4.2 FLOAT, LBSEL = 3.45 FLOAT, LBSEL = FLOAT, LBSEL = BAT_OUT OLTAGE () Battery Disconnect otage at BAT_OUT vs I BAT_IN 4., 4.1, 4.2 FLOAT, LBSEL = 1 4., 4.1, 4.2 FLOAT, LBSEL = 3.45 FLOAT, LBSEL = FLOAT, LBSEL = µ 1µ 1µ 1m 1m I BAT_IN (A) 1.8 1µ 1µ 1µ 1m 1m I BAT_IN (A) 3331 G G G54 OLTAGE () Battery Connect/Disconnect vs Temperature 3.45 FLOAT LBSEL = I BAT_OUT = 1mA CONNECT, BAT_OUT CONNECT, BAT_IN DISCONNECT, BAT_OUT, BAT_IN G55 OLTAGE () Battery Connect/Disconnect vs Temperature 3.6 CONNECT, BAT_OUT CONNECT, BAT_IN DISCONNECT, BAT_OUT, BAT_IN 3.45 FLOAT LBSEL = 1 I BAT_OUT = 1mA G /DI Battery Connect Transient BAT_IN BAT_OUT BATTERY CONNECTED 2.5ms/DI IN = 18, OUT IN REGULATION, SLEEPING 1mA CHARGES BB_IN/BAT_OUT C BB_IN = FLOAT[1:] = 11, LBSEL = 3331 G57 12

13 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. OLTAGE () Battery Connect/Disconnect vs Temperature 4., 4.1, 4.2 FLOAT LBSEL = I BAT_OUT = 1mA CONNECT, BAT_OUT CONNECT, BAT_IN DISCONNECT, BAT_OUT, BAT_IN G58 OLTAGE () Battery Connect/Disconnect vs Temperature CONNECT, BAT_OUT CONNECT, BAT_IN DISCONNECT, BAT_OUT, BAT_IN 4., 4.1, 4.2 FLOAT LBSEL = 1 I BAT_OUT = 1mA G59 5m/DI Battery Connect Transient OUT BATTERY DISCONNECTED BAT_IN BAT_OUT 5ms/DI C BAT_IN = 1mF C BB_IN =, BB_IN TIED TO BAT_OUT 1mA LOAD AT OUT FLOAT[1:] = 11, LBSEL = 3331 G6 25 Supercapacitor Baancer Quiescent Current vs SCAP 5 Supercapacitor Baancer Source/Sink Current I SCAP (na) C 85 C 25 C 4 C BALANCER SOURCE/SINK CURRENT (ma) SCAP = 5 SCAP = SCAP () 333 G BAL / SCAP (%) 333 G62 PIN FUNCTIONS BAL (Pin 1): Supercapacitor Baance Point. The common node of a stack of two supercapacitors is connected to BAL. A source/sink baancing current of up to 1mA is avaiabe. Tie BAL aong with SCAP to GND to disabe the baancer and its associated quiescent current. SCAP (Pin 2): Suppy and Input for Supercapacitor Baancer. Tie the top of a 2-capacitor stack to SCAP and the midde of the stack to BAL to activate baancing. Tie SCAP aong with BAL to GND to disabe the baancer and its associated quiescent current. IN2 (Pin 3): Interna Low otage Rai to Serve as Gate Drive for Buck NMOS Switch. Connect a 4.7µF (or arger) capacitor from IN2 to GND. This pin is not intended for use as an externa system rai. U3, U2, U1, U (Pins 4, 5, 6, 7): ULO Seect Bits for the Buck Switching Reguator. Tie high to IN2 or ow to GND to seect the desired ULO rising and faing threshods (see Tabe 4). The ULO faing threshod must be greater than the seected OUT reguation eve. Do not foat. 13

14 PIN FUNCTIONS AC1 (Pin 8): Input Connection for piezoeectric eement, other AC source, or current imited DC source (used in conjunction with AC2 for differentia AC inputs). AC2 (Pin 9): Input Connection for piezoeectric eement, other AC source, or current imited DC source (used in conjunction with AC1 for differentia AC inputs). IN (Pin 1): Rectified Input otage. A capacitor on this pin serves as an energy reservoir and input suppy for the buck reguator. The IN votage is internay camped to a maximum of 2 (typica). CAP (Pin 11): Interna Rai Referenced to IN to Serve as Gate Drive for Buck PMOS Switch. Connect a 1μF (or arger) capacitor between CAP and IN. This pin is not intended for use as an externa system rai. SW (Pin 12): Switch Node for the Buck Switching Reguator. Connect a 22µH or greater externa inductor between this node and OUT. OUT (Pin 13): Reguated Output otage Derived from the Buck or Buck-Boost Switching Reguator. SWB (Pin 14): Switch Node for the Buck-Boost Switching Reguator. Connect an externa inductor (vaue in Tabe 3) between this node and SWA. SWA (Pin 15): Switch Node for the Buck-Boost Switching Reguator. Connect an externa inductor (vaue in Tabe 3) between this node and SWB. BB_IN (Pin 16): Input for the Buck-Boost Switching Reguator. BB_IN must be tied to BAT_OUT for proper operation. IPK, IPK1, IPK2 (Pins 17, 18, 19): I PEAK_BB Seect Bits for the Buck-Boost Switching Reguator. Tie high to IN3 or ow to GND to seect the desired I PEAK_BB (see Tabe 3). Do not foat. BAT_OUT (Pin 2): This is the output side of the battery disconnect switch. BAT_OUT must be connected to BB_IN to power the buck-boost reguator. BAT_IN (Pin 21): Input for backup battery and the input side to the battery disconnect switch. When the battery is disconnected there wi be ess than 1nA of quiescent current draw at BAT_IN. LBSEL (Pin 22): Low Battery Disconnect Seect Pin. Connect LBSEL high to BB_IN or ow to GND to seect the ow battery disconnect eve. See Tabe 2. Do not foat. FLOAT1, FLOAT (Pins 23, 24): Foat otage Seect Pins. Connect high to BB_IN or ow to GND to seect battery foat votages of 3.45, 4., 4.1, and 4.2 (see Tabe 2). Do not foat. SHIP (Pin 25): Input to seect SHIP mode. Tie SHIP to at east 1.2 to seect SHIP mode in which the battery disconnect switch wi be forced off, ensuring there is no drain on the battery. Do not foat. IN3 (Pin 26): Interna Low otage Rai Used by the Prioritizer. Logic high reference for IPK[2:] and OUT[2:]. Connect a.1µf capacitor from IN3 to GND. This pin is not intended for use as an externa system rai. CHARGE (Pin 27): Connect a resistor from CHARGE to the common BAT_OUT = BB_IN node to enabe charging of the battery. The CHARGE pin is controed to provide excess energy from the energy harvesting input when the output is in reguation and the BUCK converter is in SLEEP mode. PGOUT (Pin 28): Power Good Output for OUT. Logic eve output referenced to an interna maximum rai (see Operation). PGOUT transitioning high indicates reguation has been reached on OUT ( OUT = Seep Rising). PGOUT remains high unti OUT fas to 92% (typica) of the programmed reguation point. EH_ON (Pin 29): Switcher Status. Logic eve output referenced to IN3. EH_ON is high when the buck switching reguator is in use (energy harvesting input). It is pued ow when the buck-boost switching reguator is in use (battery input). OUT, OUT1, OUT2 (Pins 3, 31, 32): OUT otage Seect Bits. Tie high to IN3 or ow to GND to seect the desired OUT (see Tabe 1). Do not foat. GND (Exposed Pad Pin 33): Ground. The Exposed Pad shoud be connected to a continuous ground pane on the second ayer of the printed circuit board by severa vias directy under the. 14

15 BLOCK DIAGRAM 1 IN 2 8 AC1 ULO_SET ULO INTERNAL RAIL GENERATION CAP 11 9 AC2 SW IN IN3 REF BANDGAP REFERENCE PRIORITIZER SLEEP BUCK CONTROL GND BB_IN IN3 EH_ON CHARGE SLEEP-ULO IN2 REF + ILIM_SET SLEEP BUCK-BOOST CONTROL SWA SWB OUT IN2 BB_IN OUT SHUNT PMOS EA + REF SLEEP.925* REF + PGOUT 28 2 BAT_OUT SCAP 2 BODY DIODE + REF + BAL 1 21 BAT_IN ULO_SET ILIM_SET BB_IN BB_IN IN3 IN2 IN SHIP FLOAT[1:] LBSEL OUT[2:] U[3:] IPK[2:] 23, 24 32, 31, 3 4, 5, 6, 7 19, 18, BD 15

16 OPERATION Modes of Operation The foowing four tabes detai a programmabe settings on the. Tabe 1. Output otage Seection OUT2 OUT1 OUT OUT Tabe 2. FLOAT Seection LBSEL FLOAT1 FLOAT FLOAT CONNECT DISCONNECT Tabe 3. I PEAK_BB Seection IPK2 IPK1 IPK I LIM L MIN 5mA 1µH 1 1mA 47µH 1 15mA 33µH mA 22µH 1 5mA 1µH 1 1 1mA 47µH mA 33µH mA 22µH Tabe 4.ULO Seection U3 U2 U1 U ULO RISING ULO FALLING

17 OPERATION Overview The combines a buck switching reguator and a buck-boost switching reguator to produce an energy harvesting soution with battery backup. The converters are controed by a prioritizer that seects which converter to use based on the avaiabiity of a battery and/or harvestabe energy. If harvested energy is avaiabe the buck reguator is active and the buck-boost is OFF. An onboard 1mA shunt battery charger with ow battery disconnect enabes charging of the backup battery to greaty extend the ife of the battery. An optiona supercapacitor baancer aows for significant energy storage at the output to hande a variety of oad requirements. Energy Harvester The energy harvester is an utraow quiescent current power suppy designed to interface directy to a piezoeectric or aternative A/C power source, rectify the input votage, and store harvested energy on an externa capacitor whie maintaining a reguated output votage. It can aso beed off any excess input power via an interna protective shunt reguator. It consists of an interna bridge rectifier, an undervotage ockout circuit, and a synchronous buck DC/DC. Interna Bridge Rectifier An interna fu-wave bridge rectifier accessibe via the differentia AC1 and AC2 inputs rectifies AC sources such as those from a piezoeectric eement. The rectified output is stored on a capacitor at the IN pin and can be used as an energy reservoir for the buck converter. The bridge rectifier has a tota drop of about 8m at typica piezo-generated currents (~1μA), but is capabe of carrying up to 5mA. Either side of the bridge can be operated independenty as a singe-ended AC or DC input. Buck Undervotage Lockout (ULO) When the votage on IN rises above the ULO rising threshod the buck converter is enabed and charge is transferred from the input capacitor to the output capacitor. When the input capacitor votage is depeted beow the ULO faing threshod the buck converter is disabed. These threshods can be set according to Tabe 4 which Figure 1. Idea IN, IN2 and CAP Reationship offers ULO rising threshods from 4 to 18 with arge or sma hysteresis windows. This aows for programming of the ULO window near the peak power point of the input source. Extremey ow quiescent current (45nA typica) in ULO aows energy to accumuate on the input capacitor in situations where energy must be harvested from ow power sources. Interna Rai Generation (CAP, IN2, IN3 ) Two interna rais, CAP and IN2, are generated from IN and are used to drive the high side PMOS and ow side NMOS of the buck converter, respectivey. Additionay the IN2 rai serves as ogic high for the ULO threshod seect bits U[3:]. The IN2 rai is reguated at 4.8 above GND whie the CAP rai is reguated at 4.8 beow IN. These are not intended to be used as externa rais. Bypass capacitors are connected to the CAP and IN2 pins to serve as energy reservoirs for driving the buck switches. When IN is beow 4.8, IN2 is equa to IN and CAP is hed at GND. Figure 1 shows the idea IN, IN2 and CAP reationship. IN3 is an interna rai used by the buck and the buck-boost. When the runs the buck IN3 wi be a Schottky diode drop beow IN2. When it runs the buck-boost IN3 is equa to BB_IN. OLTAGE () Buck Operation CAP IN 1 IN () IN F1 The buck reguator uses a hysteretic votage agorithm to contro the output through interna feedback from the OUT sense pin. The buck converter charges an output 17

18 OPERATION capacitor through an inductor to a vaue sighty higher than the reguation point. It does this by ramping the inductor current up to I PEAK_BUCK through an interna PMOS switch and then ramping it down to ma through an interna NMOS switch. This efficienty deivers energy to the output capacitor. The ramp rate is determined by IN, OUT, and the inductor vaue. When the buck brings the output votage into reguation the converter enters a ow quiescent current seep state that monitors the output votage with a seep comparator. During seep oad current is provided by the output capacitor. When the output votage fas beow the reguation point the buck reguator wakes up and the cyce repeats. This hysteretic method of providing a reguated output reduces osses associated with FET switching and maintains the output at ight oads. The buck deivers a minimum of 1mA of average oad current when it is switching. OUT can be set from 1.8 to 5 via the output votage seect bits, OUT[2:] (see Tabe 1). When the seep comparator senses that the output has reached the seep threshod the buck converter may be in the midde of a cyce with current sti fowing through the inductor. Normay both synchronous switches woud turn off and the current in the inductor woud freewhee to zero through the NMOS body diode. Instead, the NMOS switch is kept on to prevent the conduction oss that woud occur in the diode if the NMOS were off. If the PMOS is on when the seep comparator trips the NMOS wi turn on immediatey in order to ramp down the current. If the NMOS is on it wi be kept on unti the current reaches zero. Though the quiescent current when the buck is switching is much greater than the seep quiescent current, it is sti a sma percentage of the average inductor current which resuts in high efficiency over most oad conditions. The buck operates ony when sufficient energy has been accumuated in the input capacitor and the ength of time the converter needs to transfer energy to the output is much ess than the time it takes to accumuate energy. Thus, the buck operating quiescent current is averaged over a ong period of time so that the tota average quiescent current is ow. This feature accommodates sources that harvest sma amounts of ambient energy. Buck-Boost Converter The buck-boost uses the same hysteretic votage agorithm as the buck to contro the output, OUT, with the same seep comparator. The buck-boost has three modes of operation: buck, buck-boost, and boost. An interna mode comparator determines the mode of operation based on BB_IN and OUT. Figure 2 shows the four interna switches of the buck-boost converter. In each mode the inductor current is ramped up to I PEAK_BB, which is programmabe via the IPK[2:] bits and ranges from 5mA to 25mA (see Tabe 3). BB_IN M1 SWA M2 SWB Figure 2: Buck-Boost Power Switches 3331 F2 In BUCK mode M4 is aways on and M3 is aways off. The inductor current is ramped up through M1 to I PEAK_BB and down to ma through M2. In boost mode M1 is aways on and M2 is aways off. The inductor current is ramped up to I PEAK_BB when M3 is on and is ramped down to ma when M4 is on as OUT is greater than BB_IN in boost mode. Buck-boost mode is very simiar to boost mode in that M1 is aways on and M2 is aways off. If BB_IN is ess than OUT the inductor current is ramped up to I PEAK_BB through M3. When M4 turns on the current in the inductor wi start to ramp down. However, because BB_IN is cose to OUT and M1 and M4 have finite on-resistance the current ramp wi exhibit a sow exponentia decay, potentiay owering the average current deivered to OUT. For this reason the ower current threshod is set to I PEAK_BB /2 in buck-boost mode to maintain high average current to the oad. If BB_IN is greater than OUT in buck-boost mode the inductor current sti ramps up to I PEAK_BB and down to I PEAK_BB /2. It can sti ramp down if BB_IN is greater than OUT because the fina vaue of the current in the inductor woud be ( IN OUT )/(R ON1 + R ON4 ). If BB_IN is exacty I PEAK_BB /2 (R ON1 + R ON4 ) above OUT the inductor current wi not reach the I PEAK_BB /2 threshod and switches M1 and M4 wi stay on a the time. For higher BB_IN votages the mode comparator wi switch the converter to buck mode. M1 and M4 wi remain on for BB_IN votages up to OUT + I PEAK_BB (R ON1 + R ON4 ). At M3 M4 OUT 18

19 OPERATION this point the current in the inductor is equa to I PEAK_BB and the I PEAK_BB comparator wi trip turning off M1 and turning on M2 causing the inductor current to ramp down to I ZERO, competing the transition from buck-boost mode to buck mode. OUT Power Good A power good comparator is provided for the OUT output. It transitions high the first time the goes to seep, indicating that OUT has reached reguation. It transitions ow when OUT fas to 92% (typica) of its reguation vaue. The PGOUT output is referenced to an interna rai that is generated to be the highest of IN2, BB_IN, and OUT ess a Schottky diode drop. Shunt Battery Charger The provides a reiabe ow quiescent current shunt battery charger to faciitate charging a battery with harvested energy. A ow battery disconnect feature provides protection to the battery from overdischarge by disconnecting the battery from the buck-boost input at a programmabe eve. To use the charger connect the battery to the BAT_IN pin. An interna ow battery disconnect PMOS switch is connected between the BAT_IN pin and the BAT_OUT pin. The BAT_OUT pin must be connected to BB_IN for proper operation. A charging resistor connected from IN to BAT_OUT or from CHARGE to BAT_OUT wi charge the battery through the body diode of the disconnect PMOS unti the battery votage rises above the ow-battery connect threshod. Depending on the capacity of the battery and the input decouping capacitor, the common BAT_OUT = BB_IN node votage generay rises or fas to BAT_IN when the PMOS turns on. Once the PMOS is on the charge current is determined by the charging resistor, the battery votage, and the votage of the charging source. As the battery votage approaches the foat votage, the shunts current away from the battery thereby reducing the charging current. The can shunt up to 1mA. Foat votages of 3.45, 4., 4.1, and 4.2 are programmabe via the FLOAT[1:] pins (see Tabe 2). Charging can occur through a resistor connected to IN or the CHARGE pin. An interna set of back to back PMOS switches are connected between CHARGE and IN2 and are turned on ony when the energy harvesting buck converter is seeping. In this way charging of the battery ony happens when there is excess harvested energy avaiabe and the OUT output is prioritized over charging of the battery. The charge current avaiabe from this pin is imited by the strength of the IN2 LDO and an appropriate charging resistor must be seected to imit this current. The on resistance of the interna charge switches combined is approximatey 6Ω. To charge with higher currents connect a resistor directy to IN. Note that when charging from IN the battery is aways being charged. Care must be taken to ensure that enough power is avaiabe to bring up the OUT output. Low Battery Disconnect/Connect: LBD/LBC The ow battery disconnect ( LBD ) and connect ( LBC ) votage eves are programmed by the LBSEL and FLOAT[1:] pins (see Tabe 2). As shown in the Bock Diagram the battery disconnects from the common BAT_OUT = BB_IN node by shutting off the PMOS switch when the BAT_IN votage fas beow LBD. This disconnect function protects Li-Ion batteries from permanent damage due to deep discharge. Disconnecting the battery from the common BAT_OUT = BB_IN node prevents the oad as we as the quiescent current from further discharging the battery. Once disconnected the common BAT_OUT = BB_IN node votage coapses towards ground. When an input suppy is reconnected the battery charges through the interna body diode of the disconnect PMOS. The input suppy votage shoud be arger than LBC_BAT_OUT to ensure that the PMOS is turned on. When the votage reaches LBC_BAT_OUT, the PMOS turns on and connects the common BAT_OUT = BB_IN node to BAT_IN. Whie disconnected, the BAT_IN pin votage is indirecty sensed through the PMOS body diode. Therefore LBC_BAT_IN varies with charge current and junction temperature. See the Typica Performance Characteristics section for more information. Low Battery Seect The ow battery disconnect votage eve is programmed by the LBSEL pin for each foat setting. The LBSEL pin aows the user to trade-off battery run time and maximum shef ife. A ower battery disconnect threshod maximizes run 19

20 OPERATION time by aowing the battery to fuy discharge before the disconnect event. Conversey, by increasing the ow battery disconnect threshod more capacity remains foowing the disconnect event which extends the shef ife of the battery. For maximum run time, tie LBSEL to GND. For extended shef ife, tie LBSEL to the common BAT_OUT = BB_IN node. If a high peak current event is expected, users may temporariy seect the ower disconnect threshod. This avoids disconnecting the battery too eary when the oad works against the battery series resistance and temporariy reduces the common BAT_OUT = BB_IN node. Ship Mode A ship mode is provided which manuay disconnects the battery. This may be usefu to prevent discharge of the battery in situations when no harvestabe energy is expected for a ong period of time such as during shipping. Bring the SHIP pin high to engage ship mode. The ow battery disconnect PMOS wi turn off, disconnecting the battery at BAT_IN from the common BAT_OUT = BB_IN node. If no harvestabe energy is present to hod up the common BAT_OUT = BB_IN node that votage wi coapse. Typicay an additiona 1µA of quiescent current wi appear on BB_IN whie SHIP mode is engaged. To exit SHIP mode first bring the SHIP pin ow. If the BB_IN votage had coapsed whie in SHIP mode it must now be brought above the LBC threshod to reconnect the battery. This can be done manuay or from an energy harvesting charging source. If harvestabe energy had been propping up the common BAT_OUT = BB_IN node votage above the LBC threshod then the battery wi be connected immediatey. Prioritizer The input prioritizer on the decides whether to use the energy harvesting input or the battery input to power OUT. If a battery is powering the buck-boost converter and harvested energy causes a ULO rising transition on IN, the prioritizer wi shut off the buck-boost and turn on the buck, orchestrating a smooth transition that maintains reguation of OUT. 2 When harvestabe energy disappears, the prioritizer wi first po the BB_IN votage. If the BB_IN votage is above 1.8 the prioritizer wi switch back to the buck-boost whie maintaining reguation. If the BB_IN votage is beow 1.8 the buck-boost is not enabed and OUT cannot be supported unti harvestabe energy is again avaiabe. If the battery is connected then the BB_IN votage wi be above 1.8 for every foat and LBSEL combination. If the battery is disconnected the BB_IN votage wi have coapsed beow 1.8 and the prioritizer wi not switch to the buck-boost when harvestabe energy goes away. In the event that the battery is depeted and is disconnected whie powering the buck-boost the prioritizer wi not switch back to IN unti harvested energy is again avaiabe. If either BB_IN or IN is grounded, the prioritizer aows the other input to run if its input is high enough for operation. The specified quiescent current in ULO is vaid upon start-up of the IN input and when the battery has taken over reguation of the output. If the battery is ess than 1.8 when ULO is entered and the prioritizer does not enabe the buck-boost severa hundred nanoamperes of additiona quiescent current wi appear on IN. When the prioritizer seects the IN input the current on the BB_IN input drops to 2nA. However, if the votage on BB_IN is higher than IN2, a fraction of the IN quiescent current wi appear on BB_IN due to interna eve shifting. This ony affects a sma range of battery votages and ULO settings. A digita output, EH_ON, is ow when the prioritizer has seected the BB_IN input and is high when the prioritizer has seected the IN input. The EH_ON output is referenced to IN3. Supercapacitor Baancer An integrated supercapacitor baancer with 15nA of quiescent current is avaiabe to baance a stack of two supercapacitors. Typicay the input, SCAP, wi tie to OUT to aow for increased energy storage at OUT with supercapacitors. The BAL pin is tied to the midde of the stack and can source and sink 1mA to reguate the BAL pin s votage to haf that of the SCAP pin s votage. To disabe the baancer and its associated quiescent current the SCAP and BAL pins can be tied to ground.

21 APPLICATIONS INFORMATION The aows for energy harvesting from a variety of aternative energy sources in order to power a wireess sensor system and charge a battery. The extremey ow quiescent current of the faciitates harvesting from sources generating ony microamps of current. The onboard bridge rectifier is suitabe for AC piezoeectric or eectromagnetic sources as we as providing reverse protection for DC sources such as soar and thermoeectric generators. The powers the OUT output continuousy by seamessy switching between the energy harvesting and battery inputs. When harvestabe energy is avaiabe, it is transferred through the bridge rectifier where it accumuates on the IN capacitor. A ow quiescent current ULO mode aows the votage on the capacitor to increase towards a programmed ULO rising threshod. When the votage rises to this eve, the buck converter turns on and transfers energy to OUT. As energy is transferred the votage at IN may decrease to the ULO faing threshod. If this happens, the buck converter turns off and the buck-boost then turns on to service the oad from the battery input whie more energy is harvested. When the buck is running the quiescent current on the BB_IN pin drops to the 2nA required by the shunt battery charger. The is we suited to wireess systems which consume ow average power but occasionay need a higher concentrated burst of power to accompish a task. If these bursts occur with a ow duty cyce such that the tota energy needed for a burst can be accumuated between bursts then the output can be maintained entirey by the harvester. If the bursts need to happen more frequenty or if harvestabe energy goes away the battery wi be used. If enough energy is avaiabe the energy harvester wi bring the output up and enter the ow quiescent current seep state and excess energy can be used to charge the battery. Piezo Energy Harvesting Ambient vibrationa energy can be harvested with a piezoeectric transducer which produces a votage and current in response to strain. Common piezoeectric eements are PZT (ead zirconate titanate) ceramics, PDF (poyvinyidene fuoride) poymers, or other composites. Ceramic piezoeectric eements exhibit a piezoeectric effect when the crysta structure of the ceramic is compressed and interna dipoe movement produces a votage. Poymer eements comprised of ong-chain moecues produce a votage when fexed as moecues repe each other. Ceramics are often used under direct pressure whie a poymer is commony used as a cantievered beam. A wide range of piezoeectric eements are avaiabe and produce a variety of open-circuit votages and short-circuit currents. Typicay the open-circuit votage and short-circuit currents increase with avaiabe vibrationa energy as shown in Figure 3. Piezoeectric eements can be paced in series or in parae to achieve desired open-circuit votages. PIEZO OLTAGE () INCREASING IBRATION ENERGY 1 2 PIEZO CURRENT (µa) Figure 3. Typica Piezoeectric Load Lines for Piezo Systems T22-A4-53X Piezos produce the most power when they operate at approximatey haf the open circuit votage for a given vibration eve. The ULO window can be programmed to stradde this votage so that the piezo operates near the peak power point. In addition to the norma configuration of connecting the piezo across the AC1 and AC2 inputs, a piezo can be connected from either AC1 or AC2 to ground. The resuting configuration is a votage douber as seen in Figure 4 where the intrinsic capacitance of the piezo is used as the doubing capacitor F3 21

22 APPLICATIONS INFORMATION PIEZO MODEL I P sin(ωt) C P A second piezo may be connected from AC2 to ground. This may be of use if the second piezo is mechanicay tuned to a different resonant frequency present in the system than the first piezo. To achieve maximum power transfer from the piezo with the douber the ULO window shoud be set to the open circuit votage of the piezo. Piezoeectric eements are avaiabe from the manufacturers isted in Tabe 5. Tabe 5. Piezoeectric Eement Manufacturers Advanced Cerametrics Piezo Systems Measurement Speciaties PI (Physik Instrumente) MIDE Technoogy Corporation Morgan Technica Ceramics AC Eectromagnetic Energy Harvesting Another aternative AC source is an eectromagnetic vibration harvester in which a magnet vibrating inside a coi induces an AC votage and current in the coi that can then be rectified and harvested by the. The vibration coud be ambient to the system or it coud be caused by an impuse as in a spring oaded switch. Soar Energy Harvesting The can harvest soar energy as the bridge rectifier can be used to provide reverse protection for a soar pane. A soar ce produces current in proportion to the amount of ight faing on it. Figure 5 shows the reationship between current and votage for a soar pane iuminated with severa eves of ight. The maximum power output occurs near the knee of each curve where the ce transitions from a constant current device to a constant votage GND IN C IN 3331 F4 Figure 4. otage Douber Configuration I PANEL (µa) LUX 1 LUX 5 LUX PANEL CURRENT PANEL POWER 1 SANYO 1815 SOLAR PANEL 2 LUX PANEL () 3331 F5 Figure 5. Typica Soar Pane Characteristics device. Fortunatey, the peak power point doesn t change much with iumination and an appropriate ULO window can be seected so that the pane operates near the peak power point for a majority of ight conditions. Two soar panes can be connected to the, one from AC1 to ground and another from AC2 to ground. Each pane coud be aimed in a different direction to capture ight from different anges or at different times of the day as the sun moves. The panes shoud be simiar so that the seected ULO window is optima for both panes. BB_IN/BAT_OUT, BAT_IN, IN, and OUT Capacitors The input to the buck-boost, BB_IN, must be connected to BAT_OUT for proper operation. BAT_OUT is the output side of the ow battery disconnect switch. The series resistance of this switch must be considered when seecting a bypass capacitor for the common BAT_OUT = BB_IN node. At east 4.7μF to GND or greater shoud be used. For the higher I PEAK_BB settings the capacitor may need to be arger to smooth the votage at the common BAT_OUT = BB_IN node. The goa is to average the input current to the buck boost so that the votage droop at the common BAT_OUT = BB_IN node is minimized. A bypass capacitor of 1µF or greater can aso be paced at the BAT_IN pin. In cases where the series resistance of the battery is high, a arger capacitor may be desired to hande transients W PANEL (µw) 22