TO DIODE GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTV CC FBOUT INTV CC GATEV CC SRVO_FBIN SRVO_FBOUT SRVO_IIN SRVO_IOUT IMON_IN IMON_OUT

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1 Features nn nn nn nn nn nn nn nn nn nn Singe Inductor Aows Above, Beow, or Equa to Reguated Range 2.8V (Need EXTV CC > 6.4V) to 8V Range: 1.3V to 8V Quad N-Channe MOSFET Gate Drivers Synchronous Rectification: Up to 98% Efficiency Input and Output Current Monitor Pins Synchronizabe Fixed Frequency: 1kHz to 4kHz Integrated Input Current, Input Votage, Output Current and Output Votage Feedback Loops Cock Output Usabe To Monitor Die Temperature Avaiabe in 38-Lead (5mm 7mm) QFN and TSSOP Packages with the TSSOP Modified for Improved High Votage Operation Appications nn nn High Votage Buck-Boost Converters Input or Output Current Limited Converters 8V and Synchronous 4-Switch Buck- Boost DC/DC Controer Description The LT 875 is a high performance buck-boost switching reguator controer that operates from input votages above, beow or equa to the output votage. The part has integrated input current, input votage, output current and output votage feedback oops. With a wide 2.8V to 8V input and 1.3V to 8V output range, the is compatibe with most soar, automotive, teecom and battery-powered systems. The incudes servo pins to indicate which feedback oops are active. The MODE pin seects among Burst Mode operation, discontinuous or continuous conduction mode at ight oads. Additiona features incude a 3.3V/12mA LDO, a synchronizabe fixed operating frequency, onboard gate drivers, adjustabe UVLO, aong with input and output current monitoring with programmabe maximum eves. L, LT, LTC, LTM, Linear Technoogy, Burst Mode, µmodue and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Typica Appication 36V TO 8V 1µF k 2k 22µF 2 1k 215k 4.7µF 4 M1 2 V C 56.2k Teecom Votage Stabiizer 22µH M2 M3 TO 2 DIODE.22µF 1nF 1Ω 2Ω 1mΩ 1nF 1Ω 2 2Ω 2 TG1 BOOST1 SW1 BG1 CSP CSN CSNIN CSPIN SHDN SWEN LDO33 MODE FBIN RT SS CLKOUT TO DIODE.22µF M4 GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTV CC FBOUT INTV CC GATEV CC SRVO_FBIN SRVO_FBOUT SRVO_IIN SRVO_IOUT IMON_IN SYNC IMON_OUT 4.7µF 6 4Ω 4.7µF TO TO BOOST1 BOOST2 4.7µF + 392k 1k 22µF 2 EFFICIENCY (%) 48V 5A 95 9 Efficiency and Power Loss = 48V I LOAD = 2A (V) 875 TA1b POWER LOSS (W) 4.7µF 1µF 22pF 3.3nF 22kHz 875 TA1 1

2 Absoute Maximum Ratings V CSP -V CSN, V CSPIN -V CSNIN, V CSPOUT -V CSNOUT....3V to.3v SS, CLKOUT, CSP, CSN Votage....3V to 3V V C Votage (Note 2)....3V to 2.2V RT, LDO33, FBOUT Votage....3V to 5V IMON_IN, IMON_OUT Votage....3V to 5V SYNC Votage....3V to 5.5V INTV CC, GATEV CC Votage....3V to 7V V BOOST1 -V SW1, V BOOST2 -V SW2....3V to 7V SWEN, MODE Votage....3V to 7V SRVO_FBIN, SRVO_FBOUT Votage....3V to 3V SRVO_IIN, SRVO_IOUT Votage....3V to 3V FBIN, SHDN Votage....3V to 3V (Note 1) CSNIN, CSPIN, CSPOUT, CSNOUT Votage....3V to 8V, EXTV CC Votage....3V to 8V SW1, SW2 Votage...81V (Note 7) BOOST1, BOOST2 Votage....3V to 87V BG1, BG2, TG1, TG2... (Note 6) Operating Junction Temperature Range E (Notes 3, 8)... 4 C to 125 C I (Notes 3, 8)... 4 C to 125 C H (Notes 3, 8)... 4 C to 15 C MP (Notes 3, 8) C to 15 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec) FE Package...3 C Pin Configuration TOP VIEW SHDN CSN CSP LDO33 FBIN FBOUT IMON_OUT V C 8 SS 9 CLKOUT 1 SYNC 11 RT 12 TOP VIEW IMON_IN MODE SWEN INTVCC VIN CSPIN CSNIN GND GND BG GATEVCC BG2 BOOST2 TG2 SW UHF PACKAGE 38-LEAD (5mm 7mm) PLASTIC QFN T JMAX = 125 C, θ JA = 34 C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB CSPOUT CSNOUT EXTV CC SRVO_FBOUT SRVO_IOUT SRVO_IIN SRVO_FBIN NC BOOST1 TG1 SW1 NC INTV CC MODE IMON_IN SHDN CSN CSP LDO33 FBIN FBOUT IMON_OUT V C SS CLKOUT SYNC RT GND BG1 GATEV CC BG GND CSPIN 36 CSNIN FE PACKAGE VARIATION: FE38(31) 38-LEAD PLASTIC TSSOP T JMAX = 125 C, θ JA = 25 C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB CSPOUT CSNOUT EXTV CC BOOST1 TG1 SW1 22 SW2 21 TG2 2 BOOST2 2

3 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE EUHF#PBF EUHF#TRPBF Lead (5mm 7mm) Pastic QFN 4 C to 125 C IUHF#PBF IUHF#TRPBF Lead (5mm 7mm) Pastic QFN 4 C to 125 C EFE#PBF EFE#TRPBF FE 38-Lead Pastic TSSOP 4 C to 125 C IFE#PBF IFE#TRPBF FE 38-Lead Pastic TSSOP 4 C to 125 C HFE#PBF HFE#TRPBF FE 38-Lead Pastic TSSOP 4 C to 15 C MPFE#PBF MPFE#TRPBF FE 38-Lead Pastic TSSOP 55 C to 15 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. = 12V, SHDN = 3V uness otherwise noted. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Votage Suppies and Reguators Operating Votage Range EXTV CC = V EXTV CC = 7.5V Quiescent Current Not Switching, V EXTVCC = ma Quiescent Current in Shutdown V SHDN = V 1 µa EXTV CC Switchover Votage I INTVCC = 2mA, V EXTVCC Rising V EXTV CC Switchover Hysteresis.18 V INTV CC Current Limit Maximum Current Draw from INTV CC and LDO33 Pins Combined. Reguated from or EXTV CC (12V) INTV CC = 5.25V INTV CC = 4.5V ma ma INTV CC Votage Reguated from, I INTVCC = 2mA Reguated from EXTV CC (12V), I INTVCC = 2mA INTV CC Load Reguation I INTVCC = ma to 5mA % INTV CC, GATEV CC Undervotage Lockout INTV CC Faing, GATEV CC Connected to INTV CC V INTV CC, GATEV CC Undervotage Lockout Hysteresis GATEV CC Connected to INTV CC 16 mv INTV CC Reguator Dropout Votage -TVCC, I INTVCC = 2mA 245 mv LDO33 Pin Votage 5mA from LDO33 Pin V LDO33 Pin Load Reguation I LDO33 =.1mA to 5mA.25 1 % LDO33 Pin Current Limit ma LDO33 Pin Undervotage Lockout LDO33 Faing V LDO33 Pin Undervotage Lockout Hysteresis 35 mv Switching Reguator Contro Maximum Current Sense Threshod (V CSP V CSN ) Boost Mode, Minimum M3 Switch Duty Cyce (E, I) (H, MP) mv mv Maximum Current Sense Threshod (V CSN V CSP ) Buck Mode, Minimum M2 Switch Duty Cyce (E, I) (H, MP) V V V V mv mv 3

4 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. = 12V, SHDN = 3V uness otherwise noted. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Gain from V C to Maximum Current Sense Votage (V CSP -V CSN ) (A5 in the Bock Diagram) Boost Mode Buck Mode SHDN Input Votage High SHDN Rising to Enabe the Device V SHDN Input Votage High Hysteresis 5 mv SHDN Input Votage Low Device Disabed, Low Quiescent Current (E, I) (H, MP).35.3 V V SHDN Pin Bias Current V SHDN = 3V V SHDN = 12V SWEN Rising Threshod Votage (Note 5) V SWEN Threshod Votage Hysteresis (Note 5) 22 mv MODE Pin Forced Continuous Mode Threshod.4 V MODE Pin Burst Mode Range V MODE Pin Discontinuous Mode Threshod 2.3 V Soft-Start Charging Current V SS =.5V µa Soft-Start Discharge Current V SS =.5V 9.5 µa Votage Reguator Loops (Refer to Bock Diagram to Locate Ampifiers) Reguation Votage for FBOUT V C = 1.2V (E, I) V C = 1.2V (H, MP) V V Reguation Votage for FBIN V C = 1.2V (E, I) V C = 1.2V (H, MP) Line Reguation for FBOUT and FBIN Error Amp Reference = 12V to 8V; Not Switching.2.5 %/V Votage FBOUT Pin Bias Current Current Out of Pin 15 na FBOUT Error Amp EA4 g m 315 µmho FBOUT Error Amp EA4 Votage Gain 22 V/V FBIN Pin Bias Current Current Out of Pin 1 na FBIN Error Amp EA3 g m 13 µmho FBIN Error Amp EA3 Votage Gain 9 V/V SRVO_FBIN Activation Threshod (Note 5) (V FBIN Faing) (Reguation Votage for FBIN), mv V FBOUT = V IMON_IN = V IMON_OUT = V SRVO_FBIN Activation Threshod Hysteresis (Note 5) V FBOUT = V IMON_IN = V IMON_OUT = V 33 mv SRVO_FBOUT Activation Threshod (Note 5) (V FBOUT Rising) (Reguation Votage for FBOUT), mv V FBIN = 3V, V IMON_IN = V IMON_OUT = V SRVO_FBOUT Activation Threshod Hysteresis (Note 5) V FBIN = 3V, V IMON_IN = V, V IMON_OUT = V 15 mv SRVO_FBIN, SRVO_FBOUT Low Votage (Note 5) I = 1μA mv SRVO_FBIN, SRVO_FBOUT Leakage Current (Note 5) V SRVO_FBIN = V SRVO_FBOUT = 2.5V 1 µa Current Reguation Loops (Refer to Bock Diagram to Locate Ampifiers) Reguation Votages for IMON_IN and IMON_OUT V C = 1.2V V Line Reguation for IMON_IN and IMON_OUT Error Amp = 12V to 8V; Not Switching.2.5 %/V Reference Votage CSPIN, CSNIN Bias Current BOOST Capacitor Charge Contro Bock Not Active I CSPIN + I CSNIN, V CSPIN = V CSNIN = 12V 31 µa mv/v mv/v µa µa V V 4

5 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. = 12V, SHDN = 3V uness otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS CSPIN, CSNIN Common Mode Operating Votage Range V CSPIN, CSNIN Differentia Operating Votage Range 1 1 mv V CSPIN-CSNIN to IMON_IN Ampifier A7 g m V CSPIN V CSNIN = 5mV, V CSPIN = 5.25V (A Grades) (E, I) (H, MP) IMON_IN Maximum Output Current 1 µa IMON_IN Overvotage Threshod V IMON_IN Error Amp EA2 g m 185 µmho IMON_IN Error Amp EA2 Votage Gain 13 V/V CSPOUT, CSNOUT Bias Current BOOST Capacitor Charge Contro Bock Not Active I CSPOUT + I CSNOUT, V CSPOUT = V CSNOUT = 12V I CSPOUT + I CSNOUT, V CSPOUT = V CSNOUT = 1.5V 45 4 µa µa CSPOUT, CSNOUT Common Mode Operating Votage Range 8 V CSPOUT, CSNOUT Differentia Mode Operating Votage Range 1 1 mv V CSPOUT-CSNOUT to IMON_OUT Ampifier A6 g m V CSPOUT V CSNOUT = 5mV, V CSPOUT = 5.25V (A Grades) (E, I) (H, MP) V CSPOUT V CSNOUT = 5mV, V CSPOUT = 5.25V (A Grades) (E, I) (H, MP) IMON_OUT Maximum Output Current 1 µa IMON_OUT Overvotage Threshod V IMON_OUT Error Amp EA1 g m 185 µmho IMON_OUT Error Amp EA1 Votage Gain 13 V/V SRVO_IIN Activation Threshod (Note 5) (V IMON_IN Rising) (Reguation Votage for mv IMON_IN), V FBIN = 3V, V FBOUT = V, V IMON_OUT = V SRVO_IIN Activation Threshod Hysteresis (Note 5) V FBIN = 3V, V FBOUT = V, V IMON_OUT = V 22 mv SRVO_IOUT Activation Threshod (Note 5) (V IMON_OUT Rising) (Reguation Votage for IMON_ mv OUT), V FBIN = 3V, V FBOUT = V, V IMON_IN = V SRVO_IOUT Activation Threshod Hysteresis (Note 5) V FBIN = 3V, V FBOUT = V, V IMON_IN = V 22 mv SRVO_IIN, SRVO_IOUT Low Votage (Note 5) I = 1μA mv SRVO_IIN, SRVO_IOUT Leakage Current (Note 5) V SRVO_IIN = V SRVO_IOUT = 2.5V 1 µa NMOS Gate Drivers TG1, TG2 Rise Time C LOAD = 33pF (Note 4) 2 ns TG1, TG2 Fa Time C LOAD = 33pF (Note 4) 2 ns BG1, BG2 Rise Time C LOAD = 33pF (Note 4) 2 ns BG1, BG2 Fa Time C LOAD = 33pF (Note 4) 2 ns TG1 Off to BG1 On Deay C LOAD = 33pF Each Driver 1 ns BG1 Off to TG1 On Deay C LOAD = 33pF Each Driver 8 ns TG2 Off to BG2 On Deay C LOAD = 33pF Each Driver 1 ns mmho mmho mmho mmho mmho mmho mmho mmho mmho 5

6 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. = 12V, SHDN = 3V uness otherwise noted. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS BG2 Off to TG2 On Deay C LOAD = 33pF Each Driver 8 ns Minimum On-Time for Main Switch in Boost Operation Switch M3, C LOAD = 33pF 265 ns (t ON(M3,MIN) ) Minimum On-Time for Synchronous Switch in Buck Switch M2, C LOAD = 33pF 26 ns Operation (t ON(M2,MIN) ) Minimum Off-Time for Main Switch in Steady-State Boost Switch M3, C LOAD = 33pF 245 ns Operation Minimum Off-Time for Synchronous Switch in Switch M2, C LOAD = 33pF 245 ns Steady-State Buck Operation Osciator Switch Frequency Range SYNCing or Free Running 1 4 khz Switching Frequency, f OSC R T = 365k R T = 215k R T = 124K khz khz khz SYNC High Leve for Synchronization 1.3 V SYNC Low Leve for Synchronization.5 V SYNC Cock Puse Duty Cyce V SYNC = V to 2V 2 8 % Recommended Minimum SYNC Ratio f SYNC /f OSC 3/4 CLKOUT Output Votage High 1mA Out of CLKOUT Pin V CLKOUT Output Votage Low 1mA Into CLKOUT Pin 25 1 mv CLKOUT Duty Cyce T J = 4 C T J = 25 C T J = 125 C CLKOUT Rise Time C LOAD = 2pF 3 ns CLKOUT Fa Time C LOAD = 2pF 25 ns CLKOUT Phase Deay SYNC Rising to CLKOUT Rising, f OSC = 1kHz Deg % % % Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: Do not force votage on the V C pin. Note 3: The E is guaranteed to meet performance specifications from C to 125 C junction temperature. Specifications over the 4 C to 125 C operating junction temperature range are assured by design, characterization and correation with statistica process contros. The I is guaranteed over the fu 4 C to 125 C junction temperature range. The H is guaranteed over the fu 4 C to 15 C operating junction temperature range. The MP is guaranteed over the fu 55 C to 15 C operating junction temperature range. Operating ifetime is derated at junction temperatures greater than 125 C. Note 4: Rise and fa times are measured using 1% and 9% eves. Deay times are measured using 5% eves. Note 5: This specification not appicabe in the FE38 package. Note 6: Do not appy a votage or current source to these pins. They must be connected to capacitive oads ony, otherwise permanent damage may occur. Note 7: Negative votages on the SW1 and SW2 pins are imited, in an appication, by the body diodes of the externa NMOS devices, M2 and M3, or parae Schottky diodes when present. The SW1 and SW2 pins are toerant of these negative votages in excess of one diode drop beow ground, guaranteed by design. Note 8: This IC incudes overtemperature protection that is intended to protect the device during momentary overoad conditions. Junction temperature wi exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reiabiity. 6

7 Typica Performance Characteristics T A = 25 C uness otherwise specified. EFFICIENCY (%) Efficiency vs Output Current (Boost Region-Figure 14) 1 1 LOAD CURRENT (ma) = 36V = 48V BURST CCM DCM 875 G1 1 EFFICIENCY (%) Efficiency vs Output Current (Buck-Boost Region-Figure 14) 1 1 LOAD CURRENT (ma) = 48V = 48V BURST CCM DCM 875 G2 1 EFFICIENCY (%) Efficiency vs Output Current (Buck Region-Figure 14) 1 1 LOAD CURRENT (ma) = 72V = 48V BURST CCM DCM 875 G3 1 PIN VOLTAGE (V) Feedback Votages V C = 1.2V IMON_OUT IMON_IN FBOUT FBIN TEMPERATURE ( C) FBOUT VOLTAGE (V) FBOUT Votages (Five Parts) 1.23 V C = 1.2V TEMPERATURE ( C) FREQUENCY (khz) Osciator Frequency 4 R T = 124k R T = 215k R T = 365k TEMPERATURE ( C) G G5 875 G6 CSP-CSN (mv) Maximum Inductor Current Sense Votage vs Duty Cyce BUCK REGION BOOST REGION M2 OR M3 DUTY CYCLE (%) CSN-CSP (mv) Inductor Current Sense Votage at Minimum Duty Cyce BUCK REGION BOOST REGION V C (V) CSP-CSN (mv) CSP-CSN (mv) Maximum Inductor Current Sense Votage at Minimum Duty Cyce 4 BOOST REGION BUCK REGION TEMPERATURE ( C) 875 G7 875 G8 875 G9 7

8 Typica Performance Characteristics T A = 25 C uness otherwise specified. Minimum Inductor Current Sense Votage in Forced Continuous Mode 7. INTV CC Line Reguation (EXTV CC = V) 7. INTV CC Line Reguation ( = 12V) CSP-CSN (mv) BUCK REGION BOOST REGION INTV CC (V) INTV CC (V) EXTV CC RISING EXTV CC FALLING M2 OR M3 DUTY CYCLE (%) (V) EXTV CC (V) G1 875 G G12 MAXIMUM V C (V) Maximum V C vs SS 2. T J = 25 C 1.8 BOOST AND 1.6 BUCK BUCK-BOOST REGIONS REGION SS (V) 875 G13 I IN (ma) Suppy Current vs Votage (Not Switching) GATEV CC CONNECTED TO INTV CC (V) 125 C 25 C 4 C G14 IMON_OUT, IMON_IN (µa) IMON Output Currents CSPIN-CSNIN (mv) CSPOUT-CSNOUT (mv) 875 G15 1 CLKOUT Duty Cyce 3.5 LDO33 Pin Reguation (I LDO33 = 1mA) 1.3 SHDN and SWEN Pin Threshods vs Temperature 1.28 DUTY CYCLE (%) TEMPERATURE ( C) LDO (V) INTV CC (V) 125 C 25 C 4 C 6 PIN THRESHOLD VOLTAGE (V) RISING FALLING SHDN SWEN TEMPERATURE ( C) 875 G G G18 8

9 Typica Performance Characteristics T A = 25 C uness otherwise specified. CURRENT INTO PIN (µa) SHDN and MODE Pin Currents MODE SHDN UVLO (V) Interna UVLO V PIN -V REGULATION V PIN APPROACHING V REGULATION (mv) SRVO_xx Pin Activation Threshods FBIN FBOUT IMON_IN IMON_OUT PIN VOLTAGE (V) TEMPERATURE ( C) TEMPERATURE ( C) G G2 875 G21 PIN ACTIVATION THRESHOLD HYSTERSIS (mv) SRVO_xx Pin Activation Threshod Hysteresis 5 FBIN FBOUT IMON_IN IMON_OUT TEMPERATURE ( C) SW1 5V/DIV SW2 5V/DIV I L 2A/DIV Discontinuous Mode (Figure 14) = 72V = 48V 5µs/DIV 875 G23 SW1 2V/DIV SW2 2V/DIV I L 2A/DIV Forced Continuous Mode (Figure 14) = 36V = 48V 5µs/DIV 875 G G22 Forced Continuous Mode (Figure 14) Forced Continuous Mode (Figure 14) SW1 2V/DIV SW1 5V/DIV SW2 2V/DIV SW2 2V/DIV I L 2A/DIV I L 2A/DIV = 48V = 48V 5µs/DIV 875 G25 = 72V = 48V 5µs/DIV 875 G26 9

10 Typica Performance Characteristics T A = 25 C uness otherwise specified. Burst Mode Operation (Figure 14) Burst Mode Operation (Figure 14) Load Step (Figure 14) 1mV/DIV 1mV/DIV 5mV/DIV I L 1A/DIV I L 5A/DIV I L 2A/DIV = 36V = 48V 2ms/DIV 875 G27 = 72V = 48V 5ms/DIV 875 G28 = 36V 5µs/DIV = 48V LOAD STEP = 1A TO 3A 875 G29 Load Step (Figure 14) Load Step (Figure 14) 5mV/DIV 5mV/DIV I L 2A/DIV I L 2A/DIV = 48V 5µs/DIV = 48V LOAD STEP = 1A TO 3A 875 G3 = 72V 5µs/DIV = 48V LOAD STEP = 1A TO 3A 875 G31 Line Transient (Figure 14) Line Transient (Figure 14) 36V TO 72V 72V TO 36V V C.5V/DIV.5V/DIV I L 2A/DIV V C.5V/DIV.5V/DIV I L 2A/DIV 2ms/DIV 875 G32 2ms/DIV 875 G33 1

11 Pin Functions (QFN/TSSOP) SHDN (Pin 1/Pin 4): Shutdown Pin. Tie high to enabe device. Ground to shut down and reduce quiescent current to a minimum. Do not foat this pin. CSN (Pin 2/Pin 5): The ( ) Input to the Inductor Current Sense and Reverse-Current Detect Ampifier. CSP (Pin 3/Pin 6): The (+) Input to the Inductor Current Sense and Reverse-Current Detect Ampifier. The V C pin votage and buit-in offsets between CSP and CSN pins, in conjunction with the R SENSE resistor vaue, set the current trip threshod. LDO33 (Pin 4/Pin 7): 3.3V Reguator Output. Bypass this pin to ground with a minimum.1μf ceramic capacitor. FBIN (Pin 5/Pin 8): Input Feedback Pin. This pin is connected to the input error ampifier input. FBOUT (Pin 6/Pin 9): Output Feedback Pin. This pin connects the error ampifier input to an externa resistor divider from the output. IMON_OUT (Pin 7/Pin 1): Output Current Monitor Pin. The current out of this pin is proportiona to the output current. See the Operation and Appications Information sections. V C (Pin 8/Pin 11): Error Ampifier Output Pin. Tie externa compensation network to this pin. SS (Pin 9/Pin 12): Soft-Start Pin. Pace at east 1nF of capacitance here. Upon start-up, this pin wi be charged by an interna resistor to 2.5V. CLKOUT (Pin 1/Pin 13): Cock Output Pin. Use this pin to synchronize one or more compatibe switching reguator ICs to the. CLKOUT togges at the same frequency as the interna osciator or as the SYNC pin, but is approximatey 18 out of phase. CLKOUT may aso be used as a temperature monitor since the CLKOUT duty cyce varies ineary with the part s junction temperature. The CLKOUT pin can drive capacitive oads up to 2pF. SYNC (Pin 11/Pin 14): To synchronize the switching frequency to an outside cock, simpy drive this pin with a cock. The high votage eve of the cock needs to exceed 1.3V, and the ow eve shoud be ess than.5v. Drive this pin to ess than.5v to revert to the interna free-running cock. See the Appications Information section for more information. RT (Pin 12/Pin 15): Timing Resistor Pin. Adjusts the switching frequency. Pace a resistor from this pin to ground to set the free-running frequency. Do not foat this pin. BG1, BG2 (Pins 14, 16/Pins 17, 19): Bottom Gate Drive. Drives the gates of the bottom N-channe MOSFETs between ground and GATEV CC. GATEV CC (Pin 15/Pin 18): Power Suppy for Gate Drivers. Must be connected to the INTV CC pin. Do not power from any other suppy. Locay bypass to GND. BOOST1, BOOST2 (Pins 23, 17/Pins 28, 2): Boosted Foating Driver Suppy. The (+) termina of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode votage beow GATEV CC up to + GATEV CC. The BOOST2 pin swings from a diode votage beow GATEV CC up to + GATEV CC TG1, TG2 (Pins 22, 18/Pins 26, 21): Top Gate Drive. Drives the top N-channe MOSFETs with votage swings equa to GATEV CC superimposed on the switch node votages. SW1, SW2 (Pins 21, 19/Pins 24, 22): Switch Nodes. The ( ) terminas of the bootstrap capacitors connect here. SRVO_FBIN (Pin 25 QFN Ony): Open-Drain Logic Output. This pin is pued to ground when the input votage feedback oop is active. SRVO_IIN (Pin 26 QFN Ony): Open-Drain Logic Output. The pin is pued to ground when the input current oop is active. SRVO_IOUT (Pin 27 QFN Ony): Open-Drain Logic Output. The pin is pued to ground when the output current feedback oop is active. SRVO_FBOUT (Pin 28 QFN Ony): Open-Drain Logic Output. This pin is pued to ground when the output votage feedback oop is active. EXTV CC (Pin 29/Pin 3): Externa V CC Input. When EXTV CC exceeds 6.4V (typica), INTV CC wi be powered from this pin. When EXTV CC is ower than 6.22V (typica), INTV CC wi be powered from. CSNOUT (Pin 3/Pin 32): The ( ) Input to the Output Current Monitor Ampifier. Connect this pin to when not in use. See Appications Information section for proper use of this pin. 11

12 Pin Functions (QFN/TSSOP) CSPOUT (Pin 31/Pin 34): The (+) Input to the Output Current Monitor Ampifier. This pin and the CSNOUT pin measure the votage across the sense resistor, R SENSE2, to provide the output current signas. Connect this pin to when not in use. See Appications Information section for proper use of this pin. CSNIN (Pin 32/Pin 36): The ( ) Input to the Input Current Monitor Ampifier. This pin and the CSPIN pin measure the votage across the sense resistor, R SENSE1, to provide the input current signas. Connect this pin to when not in use. See Appications Information section for proper use of this pin. CSPIN (Pin 33/Pin 37): The (+) Input to the Input Current Monitor Ampifier. Connect this pin to when not in use. See Appications Information section for proper use of this pin. (Pin 34/Pin 38): Main Input Suppy Pin. It must be ocay bypassed to ground. INTV CC (Pin 35/Pin 1): Interna 6.35V Reguator Output. Must be connected to the GATEV CC pin. INTV CC is powered from EXTV CC when the EXTV CC votage is higher than 6.4V, otherwise INTV CC is powered from. Bypass this pin to ground with a minimum 4.7μF ceramic capacitor. SWEN (Pin 36 QFN Ony): Switch Enabe Pin. Tie high to enabe switching. Ground to disabe switching. Don t foat this pin. This pin is internay tied to INTV CC in the TSSOP package. IMON_IN (Pin 38/Pin 3): Input Current Monitor Pin. The current out of this pin is proportiona to the input current. See the Operation and Appications Information sections. MODE (Pin 37/Pin 2): Mode Pin. The votage appied to this pin sets the operating mode of the controer. When the appied votage is ess than.4v, the forced continuous current mode is active. When this pin is aowed to foat, Burst Mode operation is active. When the MODE pin votage is higher than 2.3V, discontinuous mode is active. GND (Pin 13, Exposed Pad Pin 39/Pin 16, Exposed Pad Pin 39): Ground. Tie directy to oca ground pane. 12

13 + + + Bock Diagram R SENSE1 R SENSE CSN CSP SWEN BOOST1 D B1 CSNIN CSPIN + A7 + A5 + A8 BUCK LOGIC TG1 C B1 D1 M1 (OPT) SW1 M2 GATEV CC BG1 IMON_IN GND MODE CLKOUT BOOST CAPACITOR CHARGE CONTROL BG2 SYNC RT OSC + A9 BOOST LOGIC SW2 TG2 BOOST2 C B2 D B2 M4 M3 D2 (OPT) SS 2.5V UV_INTV CC OT OI_IN OI_OUT STARTUP AND FAULT LOGIC FAULT_INT EA1 A6 CSPOUT CSNOUT IMON_OUT R SENSE2 VOUT UV_LDO33 UV_ UV_GATEV CC SHDN + R SHDN V FBIN R FBIN1 EXTV CC 6.4V + LDO REG 3.3V LDO REG R FBIN2 6.35V LDO REG EN EN 6.35TERNAL LDO SUPPLY2 REG EA4 FBOUT R FBOUT1 INTV CC INTERNAL SUPPLY1 LDO33 SRVO_IOUT SRVO_IIN SRVO_FBIN V R SHDN1 EA2 IMON_IN EA3 1.25V 1.27V SRVO_FBOUT V C R FBOUT2 875 F1 Figure 1. Bock Diagram 13

14 Operation Refer to the Bock Diagram (Figure 1) when reading the foowing sections about the operation of the. Main Contro Loop The is a current mode controer that provides an output votage above, equa to or beow the input votage. The LTC proprietary topoogy and contro architecture empoys a current-sensing resistor (R SENSE ) in buck or boost modes. The inductor current is controed by the votage on the V C pin, which is the diode-and of error ampifiers EA1-EA4. In the simpest form, where the output is reguated to a constant votage, the FBOUT pin receives the output votage feedback signa, which is compared to the interna reference votage by EA4. Low output votages woud create a higher V C votage, and thus more current woud fow into the output. Conversey, higher output votages woud cause V C to drop, thus reducing the current fed into the output. The contains four error ampifiers (EA1-EA4) aowing it to reguate or imit the output current (EA1), input current (EA2), input votage (EA3) and/or output votage (EA4). In a typica appication, the output votage might be reguated using EA4, whie the remaining error ampifiers are monitoring for excessive input or output current or an input undervotage condition. In other appications, such as a battery charger, the output current reguator (EA1) can faciitate constant current charging unti a predetermined votage is reached where the output votage (EA4) contro woud take over. INTV CC /EXTV CC /GATEV CC /LDO33 Power Power for the top and bottom MOSFET drivers, the LDO33 pin and most interna circuitry is derived from the INTV CC pin. INTV CC is reguated to 6.35V (typica) from either the or EXTV CC pin. When the EXTV CC pin is eft open or tied to a votage ess than 6.22V (typica), an interna ow dropout reguator reguates INTV CC from. If EXTV CC is taken above 6.4V (typica), another ow dropout reguator wi instead reguate INTV CC from EXTV CC. Reguating INTV CC from EXTV CC aows the power to be derived from the owest suppy votage (highest efficiency) such as the switching reguator output (see INTV CC Reguators and EXTV CC Connection in the Appications Information section for more detais). 14 The GATEV CC pin directy powers the bottom MOSFET drivers for switches M2 and M3. GATEV CC shoud aways be connected to INTV CC and shoud not be powered or connected to any other source. Undervotage ock outs (UVLOs) monitoring INTV CC and GATEV CC disabe the switching reguator when the pins are beow 4.65V (typica). The LDO33 pin is avaiabe to provide power to externa components such as a microcontroer and/or to provide an accurate bias votage. Load current is imited to 17.25mA (typica). As ong as SHDN is high the LDO33 output is ineary reguated from the INTV CC pin and is not affected by the INTV CC or GATEV CC UVLOs or the SWEN pin votage. LDO33 wi remain reguated as ong as SHDN is high and sufficient votage is avaiabe on INTV CC (typicay > 4.V). An undervotage ockout, monitoring LDO33, wi disabe the switching reguator when LDO33 is beow 3.4V (typica). Start-Up Figure 2 iustrates the start-up sequence for the. The master shutdown pin for the chip is SHDN. When driven beow.35v (E, I) or.3v (H, MP) the chip is disabed (chip off state) and quiescent current is minima. Increasing the SHDN votage can increase quiescent current but wi not enabe the chip unti SHDN is driven above 1.234V (typica) after which the INTV CC and LDO33 reguators are enabed (switcher off state). Externa devices powered by the LDO33 pin can become active at this time if enough votage is avaiabe on or EXTV CC to raise INTV CC, and thus LDO33, to an adequate votage. Starting up the switching reguator happens after SWEN (switcher enabe) is aso driven above 1.26V (typica), INTV CC and GATEV CC have risen above 4.81V (typica) and the LDO33 pin has risen above 3.8V (typica) (initiaize state). The SWEN pin is not avaiabe in the TSSOP package. In this package the SWEN pin is internay connected to INTV CC. Start-Up: Soft-Start of Switch Current In the initiaize state, the SS (soft-start) pin is pued ow to prepare for soft starting the reguator. If forced continuous mode is seected (MODE pin ow), the part is put into discontinuous mode during soft-start to prevent current

15 Operation SHDN < 1.184V OR < 2.5V OR T JUNCTION > 165 C TYPICAL VALUES T JUNCTION < 16 C AND SHDN > 1.234V AND > 2.5V AND (SWEN* < 1.184V OR (INTV CC AND GATEV CC < 4.65V) OR LDO33 < 3.4V) TYPICAL VALUES CHIP OFF SWITCHER OFF LDOs OFF SWITCHER OFF SWITCHER DISABLED INTV CC AND LDO33 OUTPUTS ENABLED INITIALIZE SS PULLED LOW FORCE DISCONTINOUS MODE UNLESS Burst Mode OPERATION SELECTED SHDN > 1.234V AND > 2.5V AND SWEN* > 1.26V AND (INTV CC AND GATEV CC > 4.81V) AND LDO33 > 3.75V FAULT TYPICAL VALUES SS < 5mV SOFT-START SS CHARGES UP SWITCHER ENABLED FAULT FAULT DETECTED SS CHARGES UP SWITCHER DISABLED CLKOUT DISABLED NORMAL MODE NORMAL OPERATION WHEN SS > 1.6V... CLKOUT ENABLED ENABLE FORCED CONTINUOUS MODE IF SELECTED SS > 1.6V AND NO FAULT CONDITIONS STILL DETECTED FAULT FAULT POST FAULT DELAY SS SLOWLY DISCHARGES SS < 5mV *SWEN IS CONNECTED TO INTV CC IN THE TSSOP PACKAGE FAULT = OVERVOLTAGE (IMON_IN OR IMON_OUT > 1.61V TYP) 875 F2 Figure 2. Start-Up and Faut Sequence from being drawn out of the output and forced into the input. After SS has been discharged to ess than 5mV, a soft-start of the switching reguator begins (soft-start state). The soft-start circuitry provides for a gradua ramp-up of the inductor current by graduay aowing the V C votage to rise (refer to V C vs SS Votage in the Typica Performance Characteristics). This prevents abrupt surges of current from being drawn out of the input power suppy. An integrated 1k resistor pus the SS pin to 2.5V. The ramp rate of the SS pin votage is set by this 1k resistor and the externa capacitor connected to this pin. Once SS gets to 1.6V, the CLKOUT pin is enabed, the part is aowed to enter forced continuous mode (if MODE is ow) and an interna reguator pus SS up quicky to 2.5V. Typica vaues for the externa soft-start capacitor range from 1nF to 1μF. A minimum of 1nF is recommended. Faut Conditions The activates a faut sequence under certain operating conditions. If any of these conditions occur (see Figure 2) the CLKOUT pin and interna switching activity are disabed. At the same time, a timeout sequence commences where the SS pin is charged up to a minimum of 1.6V (faut detected state). The SS pin wi continue 15

16 Operation charging up to 2.5V and be hed there in the case of a faut event that persists. After the faut condition had ended and SS is greater than 1.6V, SS wi then sowy discharge to 5mV (post faut deay state). This timeout period reieves the part and other downstream power components from eectrica and therma stress for a minimum amount of time as set by the votage ramp rate on the SS pin. After SS has discharged to < 5mV, the wi enter the soft-start state and restart switching activity. Power Switch Contro Figure 3 shows a simpified diagram of how the four power switches are connected to the inductor,, and ground. Figure 4 shows the regions of operation for the as a function of - or switch duty cyce DC. The power switches are propery controed so the transfer between modes is continuous. TG1 BG1 M1 SW1 M2 L R SENSE M4 SW2 M3 TG2 BG2 is turned on first. Inductor current is sensed by ampifier A5 whie switch M2 is on. A sope compensation ramp is added to the sensed votage which is then compared by A8 to a reference that is proportiona to V C. After the sensed inductor current fas beow the reference, switch M2 is turned off and switch M1 is turned on for the remainder of the cyce. Switches M1 and M2 wi aternate, behaving ike a typica synchronous buck reguator. CLOCK SWITCH M1 SWITCH M2 SWITCH M3 SWITCH M4 I L Figure 5. Buck Region ( >> ) OFF ON 875 F5 The part wi continue operating in the buck region over a range of switch M2 duty cyces. The duty cyce of switch M2 in the buck region is given by: DC (M2,BUCK) = 1 V OUT 1% - 16 BOOST REGION BUCK/BOOST REGION BUCK REGION 875 F3 Figure 3. Simpified Diagram of the Output Switches SWITCH M3 DC MAX M1 ON, M2 OFF PWM M3, M4 SWITCHES SWITCH M3 DC 4-SWITCH PWM MIN SWITCH M2 DC MIN M4 ON, M3 OFF PWM M1, M2 SWITCHES SWITCH 875 F4 M2 DC MAX Figure 4. Operating Regions vs - Power Switch Contro: Buck Region ( >> ) When is significanty higher than, the part wi run in the buck region. In this region switch M3 is aways off. Aso, switch M4 is aways on uness reverse current is detected whie in Burst Mode operation or discontinuous mode. At the start of every cyce, synchronous switch M2 As and get coser to each other, the duty cyce decreases unti the minimum duty cyce of the converter in buck mode reaches DC (ABSMIN,M2,BUCK). If the duty cyce becomes ower than DC (ABSMIN,M2,BUCK) the part wi move to the buck-boost region. DC (ABSMIN,M2,BUCK) t ON(M2,MIN) f 1% where: t ON(M2,MIN) is the minimum on-time for the synchronous switch in buck operation (26ns typica, see Eectrica Characteristics). f is the switching frequency When is much higher than the duty cyce of switch M2 wi increase, causing the M2 switch off-time to decrease. The M2 switch off-time shoud be kept above 245ns (typica, see Eectrica Characteristics) to maintain steady-state operation, avoid duty cyce jitter, increased output rippe and reduction in maximum output current.

17 Operation Power Switch Contro: Buck-Boost ( ) When is cose to, the controer enters the buckboost region. Figure 6 shows typica waveforms in this region. Every cyce, if the controer starts with switches M2 and M4 turned on, the controer first operates as if in the buck region. When A8 trips, switch M2 is turned off and M1 is turned on unti the midde of the cock cyce. Next, switch M4 turns off and M3 turns on. The then operates as if in boost mode unti A9 trips. Finay switch M3 turns off and M4 turns on unti the end of the cyce. If the controer starts with switches M1 and M3 turned on, the controer first operates as if in the boost region. When A9 trips, switch M3 is turned off and M4 is turned on unti the midde of the cock cyce. Next, switch M1 turns off and M2 turns on. The then operates as if in buck mode unti A8 trips. Finay switch M2 turns off and M1 turns on unti the end of the cyce. CLOCK Power Switch Contro: Boost Region ( << ) When is significanty higher than, the part wi run in the boost region. In this region switch M1 is aways on and switch M2 is aways off. At the start of every cyce, switch M3 is turned on first. Inductor current is sensed by ampifier A5 whie switch M3 is on. A sope compensation ramp is added to the sensed votage which is then compared (A9) to a reference that is proportiona to V C. After the sensed inductor current rises above the reference votage, switch M3 is turned off and switch M4 is turned on for the remainder of the cyce. Switches M3 and M4 wi aternate, behaving ike a typica synchronous boost reguator. The part wi continue operating in the boost region over a range of switch M3 duty cyces. The duty cyce of switch M3 in the boost region is given by: DC (M3,BOOST) = 1 V IN 1% SWITCH M1 SWITCH M2 SWITCH M3 SWITCH M4 As and get coser to each other, the duty cyce decreases unti the minimum duty cyce of the converter in boost mode reaches DC (ABSMIN,M3,BOOST). If the duty cyce becomes ower than DC (ABSMIN,M3,BOOST) the part wi move to the buck-boost region: I L (6a) Buck-Boost Region ( ) 875 F6a DC (ABSMIN,M3,BOOST) t ON(M3,MIN) f 1% where: CLOCK SWITCH M1 t ON(M3,MIN) is the minimum on-time for the main switch in boost operation (265ns typica, see Eectrica Characteristics) f is the switching frequency SWITCH M2 SWITCH M3 SWITCH M4 I L 875 F6b CLOCK SWITCH M1 SWITCH M2 ON OFF (6b) Buck-Boost Region ( ) SWITCH M3 Figure 6. Buck-Boost Region SWITCH M4 I L 875 F7 Figure 7. Boost Region ( << ) 17

18 Operation When is much higher than the duty cyce of switch M3 wi increase, causing the M3 switch off-time to decrease. The M3 switch off-time shoud be kept above 245ns (typica, see Eectrica Characteristics) to maintain steady-state operation, avoid duty cyce jitter, increased output rippe and reduction in maximum output current. Light Load Current Operation (MODE Pin) Under ight current oad conditions, the can be set to operate in discontinuous mode, forced continuous mode, or Burst Mode operation. To seect forced continuous mode, tie the MODE pin to a votage beow.4v (i.e., ground). To seect discontinuous mode, tie MODE to a votage above 2.3V (i.e., LDO33). To seect Burst Mode operation, foat the MODE pin or tie it between 1.V and 1.7V. Discontinuous Mode: When the is in discontinuous mode, synchronous switch M4 is hed off whenever reverse current in the inductor is detected. This is to prevent current draw from the output and/or feeding current to the input suppy. Under very ight oads, the current comparator may aso remain tripped for severa cyces and force switches M1 and M3 to stay off for the same number of cyces (i.e., skipping puses). Synchronous switch M2 wi remain on during the skipped cyces, but since switch M4 is off, the inductor current wi not reverse. Burst Mode Operation: Burst Mode operation sets a V C eve, with about 25mV of hysteresis, beow which switching activity is inhibited and above which switching activity is re-enabed. A typica exampe is when, at ight output currents, rises and forces the V C pin beow the threshod that temporariy inhibits switching. After drops sighty and V C rises ~25mV the switching is resumed, initiay in the buck-boost region. Burst Mode operation can increase efficiency at ight oad currents by eiminating unnecessary switching activity and reated power osses. Burst Mode operation handes reverse-current detection simiar to discontinuous mode. The M4 switch is turned off when reverse current is detected. Forced Continuous Mode: The forced continuous mode aows the inductor current to reverse directions without any switches being forced off to prevent this from happening. At very ight oad currents the inductor current wi swing positive and negative as the appropriate average current is deivered to the output. During soft-start, when the SS pin is beow 1.6V, the part wi be forced into discontinuous mode to prevent puing current from the output to the input. After SS rises above 1.6V, forced continuous mode wi be enabed. Votage Reguation Loops The provides two constant-votage reguation oops, one for output votage and one for input votage. A resistor divider between, FBOUT and GND senses the output votage. As with traditiona votage reguators, when FBOUT rises near or above the reference votage of EA4 (1.27V typica, see Bock Diagram), the V C votage is reduced to command the amount of current that keeps reguated to the desired votage. The input votage can aso be sensed by connecting a resistor divider between, FBIN and GND. When the FBIN votage fas near or beow the reference votage of EA3 (1.25V typica, see Bock Diagram), the V C votage is reduced to aso reduce the input current. For appications with a high input source impedance (i.e., a soar pane), the input votage reguation oop can prevent the input votage from becoming too ow under high output oad conditions. For appications with a ower input source impedance (i.e., batteries and votage suppies), the FBIN pin can be used to stop switching activity when the input power suppy votage gets too ow for proper system operation. See the Appications Information section for more information about setting up the votage reguation oops. Current Monitoring and Reguation The provides two constant-current reguation oops, one for input current and one for output current. A sensing resistor cose to the input capacitor, sensed by CSPIN and CSNIN, monitors the input current. A current, ineary proportiona to the sense votage (V CSPIN -V CSNIN ), is forced out of the IMON_IN pin and into an externa resistor. The resuting votage V IMON_IN is therefore ineary proportiona to the input current. Simiary, a sensing resistor cose to the output capacitor, and sensed by CSPOUT and CSNOUT wi monitor the output current and generate a votage V IMON_OUT that is ineary proportiona to the output current. 18

19 Operation When the input or output current causes the respective IMON_IN or IMON_OUT votage to rise near or above 1.28V (typica), the V C pin votage wi be pued down to maintain the desired maximum input and/or output current (see EA1 and EA2 on the Bock Diagram). The input current imit function prevents overoading the DC input source, whie the output current imit provides a buiding bock for battery charger or LED driver appications. It can aso serve as short-circuit protection for a constant-votage reguator. See the Appications Information section for more information about setting up the current reguation oops. SRVO Pins The QFN package has four open-drain SRVO pins: SRVO_FBIN, SRVO_FBOUT, SRVO_IIN, SRVO_IOUT. Pace pu-up resistors from the desired SRVO pin(s) to a power suppy ess than 3V (i.e., the LDO33 pin) to enabe reading of their ogic states. The SRVO_FBOUT, SRVO_IIN and SRVO_IOUT pins are pued ow when their associated error amp (EA4, EA2, EA1) input votages are near or greater than their reguation votages ( 1.2V typica). SRVO_FBIN is pued ow when FBIN is near or ower than its reguation votage ( 1.2V typica). The SRVO pins can therefore be used as indicators of when their respective feedback oops are active. For exampe, the SRVO_FBOUT pin pus ow when FBOUT rises to within 29mV (typica, see Eectrica Characteristics) of its reguation votage (1.27V typica). The pu-down turns off after FBOUT fas to more than 44mV (typica) ower than its reguation votage. As another exampe, the SRVO_IOUT pin can be read to determine when the output current has neary reached its predetermined imit. A ogic 1 on SRVO_IOUT indicates that the output current has not reached the current imit and a ogic indicates that it has. CLKOUT and Temperature Sensing The CLKOUT pin togges at the s interna cock frequency whether the interna cock is synchronized to an externa source or is free-running based on the externa R T resistor. The CLKOUT pin can be used to synchronize other devices to the s switching frequency. Aso, the duty cyce of CLKOUT is proportiona to the die temperature and can be used to monitor the die for therma issues. 19

20 Appications Information The first page shows a typica appication circuit. After the switching frequency is seected, externa component seection continues with the seection of R SENSE and the inductor vaue. Next, the power MOSFETs are seected. Finay, C IN and C OUT are seected. The foowing exampes and equations assume continuous conduction mode uness otherwise specified. The circuit can be configured for operation up to an input and/or output votage of 8V. Operating Frequency Seection The uses a constant frequency architecture between 1kHz and 4kHz. The frequency can be set using the interna osciator or can be synchronized to an externa cock source. Seection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching osses, but requires more inductance and/or capacitance to maintain ow output rippe votage. For high power appications, consider operating at ower frequencies to minimize MOSFET heating from switching osses. The switching frequency can be set by pacing an appropriate resistor from the RT pin to ground and tying the SYNC pin ow. The frequency can aso be synchronized to an externa cock source driven into the SYNC pin. The foowing sections provide more detais. Interna Osciator The operating frequency of the can be set using the interna free-running osciator. When the SYNC pin is driven ow (<.5V), the frequency of operation is set by the vaue of a resistor from the RT pin to ground. An internay trimmed timing capacitor resides inside the IC. The osciator frequency is cacuated using the foowing formua: f OSC = 43,75 khz R T +1 where f OSC is in khz and R T is in kω. Conversey, R T (in kω) can be cacuated from the desired frequency (in khz) using: R T = 43,75 1kΩ f OSC 2 SYNC Pin and Cock Synchronization The operating frequency of the can be synchronized to an externa cock source. To synchronize to the externa source, simpy provide a digita cock signa into the SYNC pin. The wi operate at the SYNC cock frequency. The duty cyce of the SYNC signa must be between 2% and 8% for proper operation. Aso, the frequency of the SYNC signa must meet the foowing two criteria: 1. SYNC may not togge outside the frequency range of 1kHz to 4kHz uness it is stopped ow to enabe the free-running osciator. 2. The SYNC pin frequency can aways be higher than the free-running osciator set frequency, f OSC, but shoud not be ess than 25% beow f OSC. After SYNC begins togging, it is recommended that switching activity is stopped before the SYNC pin stops togging. Excess inductor current can resut when SYNC stops togging as the transitions from the externa SYNC cock source to the interna free-running osciator cock. Switching activity can be stopped by driving either the SWEN or SHDN pin ow. CLKOUT Pin and Cock Synchronization The CLKOUT pin can drive up to 2pF and togges at the s interna cock frequency whether the interna cock is synchronized to the SYNC pin or is free-running based on the externa R T resistor. The rising edge of CLKOUT is approximatey 18 out of phase from the interna cock s rising edge or the SYNC pin s rising edge if it is togging. CLKOUT togges ony in norma mode (see Figure 2). The CLKOUT pin can be used to synchronize other devices to the s switching frequency. For exampe, the CLKOUT pin can be tied to the SYNC pin of another reguator which wi operate approximatey 18 out of phase of the master due to the CLKOUT phase shift. The frequency of the master can be set by the externa R T resistor or by togging the SYNC pin. CLKOUT wi begin osciating after the master enters norma mode (see Figure 2). Note that the RT pin of the save must have a resistor tied to ground. In genera, use the same vaue R T resistor for a of the synchronized s.

21 Appications Information The duty cyce of CLKOUT is proportiona to the die temperature and can be used to monitor the die for therma issues. See the Junction Temperature Measurement section for more information. Inductor Current Sensing and Sope Compensation The operates using inductor current mode contro. As described previousy in the Power Switch Contro section, the measures the peak of the inductor current waveform in the boost region and the vaey of the inductor current waveform in the buck region. The inductor current is sensed across the R SENSE resistor with pins CSP and CSN. During any given cyce, the peak (boost region) or vaey (buck region) of the inductor current is controed by the V C pin votage. Sope compensation provides stabiity in constantfrequency current mode contro architectures by preventing subharmonic osciations at high duty cyces. This is accompished internay by adding a compensating ramp to the inductor current signa in the boost region, or subtracting a ramp from the inductor current signa in the buck region. At higher duty cyces, this resuts in a reduction of maximum inductor current in the boost region, and an increase of the maximum inductor current in the buck region. For exampe, refer to the Maximum Inductor Current Sense Votage vs Duty Cyce graph in the Typica Performance Characteristics section. The graph shows that, with V C at its maximum votage, the maximum inductor sense votage V RSENSE is between 78mV and 117mV depending on the duty cyce. It aso shows that the maximum inductor vaey current in the buck region is 86mV increasing to ~13mV at higher duty cyces. R SENSE Seection and Maximum Current The R SENSE resistance must be chosen propery to achieve the desired amount of output current. Too much resistance can imit the output current beow the appication requirements. Start by determining the maximum aowed R SENSE resistance in the boost region, R SENSE(MAX,BOOST). Foow this by finding the maximum aowed R SENSE resistance in the buck region, R SENSE(MAX,BUCK). The seected R SENSE resistance must be smaer than both. Boost Region: In the boost region, the maximum output current capabiity is the east when is at its minimum and is at its maximum. Therefore R SENSE must be chosen to meet the output current requirements under these conditions. Start by finding the boost region duty cyce when is minimum and is maximum using: DC (MAX,M3,BOOST) 1 V IN(MIN) V 1% OUT(MAX) For exampe, an appication with a range of 12V to 48V and set to 36V wi have: DC (MAX,M3,BOOST) 1 12V 1%=67% 36V Referring to the Maximum Inductor Current Sense Votage graph in the Typica Performance Characteristics section, the maximum R SENSE votage at 67% duty cyce is 93mV, or: V RSENSE(MAX,BOOST, MAX) 93mV for = 12V, = 36V. Next, the inductor rippe current in the boost region must be determined. If the main inductor L is not known, the maximum rippe current I L(MAX,BOOST) can be estimated by choosing I L(MAX,BOOST) to be 3% to 5% of the maximum inductor current in the boost region as foows: I L(MAX,BOOST) (MAX) I OUT(MAX,BOOST) A 1% (MIN) %Rippe.5 where: I OUT(MAX,BOOST) is the maximum output oad current required in the boost region %Rippe is 3% to 5% For exampe, using (MAX) = 36V, (MIN) = 12V, I OUT(MAX,BOOST) = 2A and %Rippe = 4% we can estimate: 36V 2A I L(MAX,BOOST) 12V 1% =3A 4%.5 21