LT3070 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION

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1 FEATURES Output Current: 5A Dropout Votage: 85mV Typica Digitay Programmabe :.8V to 1.8V Digita Output Margining: ±1%, ±3% or ±5% Low Output Noise: 25µV RMS (1Hz to 1kHz) Parae Mutipe Devices for 1A or More Precision Current Limit: ±2% n n ±1% Accuracy Over Line, Load and Temperature Stabe with Low ESR Ceramic Output Capacitors (15µF Minimum) High Frequency PSRR: 3dB at 1MHz Enabe Function Turns Output On/Off VIOC Pin Contros Buck Converter to Maintain Low Power Dissipation and Optimize Efficiency PWRGD/UVLO/Therma Shutdown Fag Current Limit with Fodback Protection Therma Shutdown 28-Lead (4mm 5mm.75mm) QFN Package APPLICATIONS FPGA and DSP Suppies ASIC and Microprocessor Suppies Servers and Storage Devices Post Buck Reguation and Suppy Isoation DESCRIPTION LT37 5A, Low Noise, Programmabe Output, 85mV Dropout Linear Reguator The LT 37 is a ow votage, UtraFast transient response inear reguator. The device suppies up to 5A of output current with a typica dropout votage of 85mV. A.1µF reference bypass capacitor decreases output votage noise to 25µV RMS. The LT37 s high bandwidth permits the use of ow ESR ceramic capacitors, saving buk capacitance and cost. The LT37 s features make it idea for high performance FPGAs, microprocessors or sensitive communication suppy appications. Output votage is digitay seectabe in 5mV increments over a.8v to 1.8V range. A margining function aows the user to adjust system output votage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function to contro a buck reguator powering the LT37 s input. This tracking function drives the buck reguator to maintain the LT37 s input votage to + 3mV, minimizing power dissipation. Interna protection incudes UVLO, reverse-current protection, precision current imiting with power fodback and therma shutdown. The LT37 reguator is avaiabe in a thermay enhanced 28-ead, 4mm 5mm QFN package. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and UtraFast and VLDO are trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Patents pending. TYPICAL APPLICATION.9V, 5A Reguator V BIAS 5k 2.2V TO 3.6V 2.2µF V IN BIAS 1.2V IN PWRGD 33µF EN SENSE V O V O1 LT37 OUT V O2 MARGSEL MARGTOL VIOC REF/BYP 1nF 2.2µF*.1µF 4.7µF* *X5R OR X7R CAPACITORS 37 TA1a PWRGD 1µF*.9V 5A For more information DROPOUT VOLTAGE (mv) Dropout Votage V IN = (NOMINAL) = 1.8V V BIAS = 3.3V =.8V V BIAS = 2.5V OUTPUT CURRENT (A) 37 TA1b 37fc 1

2 LT37 ABSOLUTE MAXIMUM RATINGS (Note 1) IN, OUT....3V to 3.3V BIAS....3V to 4V V O2, V O1, V O Inputs....3V to 4V MARGSEL, MARGTOL Input....3V to 4V EN Input....3V to 4V SENSE Input....3V to 4V VIOC, PWRGD Outputs....3V to 4V REF/BYP Output....3V to 4V Output Short-Circuit Duration...Indefinite Operating Junction Temperature (Note 2) LT37E/LT37I... 4 C to 125 C LT37MP C to 125 C Storage Temperature Range C to 15 C PIN CONFIGURATION 9 1 TOP VIEW EN BIAS VO2 V O1 V O VIOC 1 22 MARGTOL PWRGD 2 21 MARGSEL REF/BYP 3 2 IN SENSE OUT IN 6 17 OUT IN 7 16 OUT IN 8 15 OUT UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN T JMAX = 125 C, θ JA = 3 C/W TO 35 C/W EXPOSED PAD (PIN 29) IS, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT37EUFD#PBF LT37EUFD#TRPBF Lead (4mm 5mm) Pastic QFN 4 C to 125 C LT37IUFD#PBF LT37IUFD#TRPBF Lead (4mm 5mm) Pastic QFN 4 C to 125 C LT37MPUFD#PBF LT37MPUFD#TRPBF Lead (4mm 5mm) Pastic QFN 55 C to 125 C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT37EUFD LT37EUFD#TR Lead (4mm 5mm) Pastic QFN 4 C to 125 C LT37IUFD LT37IUFD#TR Lead (4mm 5mm) Pastic QFN 4 C to 125 C LT37MPUFD LT37MPUFD#TR Lead (4mm 5mm) Pastic QFN 55 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2 For more information 37fc

3 LT37 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. C OUT = 15µF (Note 9), V IN = +.3V (Note 5), V BIAS = 2.5V uness otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS IN Pin Votage Range V IN + 15mV, I OUT = 5A V BIAS Pin Votage Range (Note 3) V Reguated Output Votage =.8V, 1mA I OUT 5A, 1.5V V IN 1.25V =.9V, 1mA I OUT 5A, 1.15V V IN 1.35V = 1V, 1mA I OUT 5A, 1.25V V IN 1.45V = 1.1V, 1mA I OUT 5A, 1.35V V IN 1.55V = 1.2V, 1mA I OUT 5A, 1.45V V IN 1.65V, V BIAS = 3.3V = 1.5V, 1mA I OUT 5A, 1.75V V IN 1.95V, V BIAS = 3.3V = 1.8V, 1mA I OUT 5A, 2.5V V IN 2.25V, V BIAS = 3.3V Reguated Output Votage Margining (Note 3) Line Reguation to V IN Line Reguation to V BIAS Load Reguation, I OUT = 1mA to 5A Dropout Votage, V IN = (NOMINAL) (Note 6) MARGTOL = V, MARGSEL = V BIAS MARGTOL = V, MARGSEL = V, I OUT = 1mA MARGTOL = FLOAT, MARGSEL = V BIAS MARGTOL = FLOAT, MARGSEL = V, I OUT = 1mA MARGTOL = V BIAS, MARGSEL= V BIAS MARGTOL = V BIAS, MARGSEL = V, I OUT = 1mA =.8V, V IN = 1.5V to 2.7V, V BIAS = 3.3V, I OUT = 1mA = 1.8V, V IN = 2.5V to 2.7V, V BIAS = 3.3V, I OUT = 1mA =.8V, V BIAS = 2.2V to 3.6V, V IN = 1.1V, I OUT = 1mA = 1.8V, V BIAS = 3.25V to 3.6V, V IN = 2.1V, I OUT = 1mA V BIAS = 2.5V, V IN = 1.5V, =.8V V BIAS = 2.5V, V IN = 1.25V, = 1.V V BIAS = 3.3V, V IN = 1.45V, = 1.2V V BIAS = 3.3V, V IN = 1.75V, = 1.5V V BIAS = 3.3V, V IN = 2.5V, = 1.8V I OUT = 1A, = 1V 2 35 mv I OUT = 2.5A, = 1V 5 65 mv 85 mv I OUT = 5A, = 1V mv 15 mv SENSE Pin Current V IN = 1.1V, V SENSE =.8V V BIAS = 3.3V, V IN = 2.1V, V SENSE = 1.8V V V V V V V V % % % % % % mv mv mv mv mv mv mv mv mv mv mv mv mv mv µa µa For more information 37fc 3

4 LT37 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. C OUT = 15µF (Note 9), V IN = +.3V (Note 5), V BIAS = 2.5V uness otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Ground Pin Current, V IN = 1.3V, = 1V I OUT = 1mA I OUT = 5A BIAS Pin Current in Nap Mode EN = Low µa BIAS Pin Current, V IN = 1.3V, = 1V I OUT = 1mA I OUT = 1mA I OUT = 5mA I OUT = 1A I OUT = 2.5A I OUT = 5A Current Limit (Note 5) V IN <.3V, V BIAS = 3.3V V IN = 1.V, V BIAS = 3.3V V IN = 1.7V, V BIAS = 3.3V Reverse Output Current (Note 8) V IN = V, = 1.8V 3 45 µa PWRGD Threshod Percentage of (NOMINAL), Rising Percentage of (NOMINAL), Faing % % PWRGD V OL I PWRGD = 2µA (Faut Condition) 5 15 mv V BIAS Undervotage Lockout V BIAS Rising V BIAS Faing V IN - Servo Votage by VIOC mv VIOC Output Current V IN = (NOMINAL) + 15mV, Sourcing Out of the Pin V IN = (NOMINAL) + 45mV, Sinking Into the Pin µa µa V IL Input Threshod (Logic- State), Input Faing.25 V V O2, V O1, V O, MARGSEL, MARGTOL V IZ Input Range (Logic-Z State),.75 V BIAS.9 V V O2, V O1, V O, MARGSEL, MARGTOL V IH Input Threshod (Logic-1 State), Input Rising V BIAS.25 V V O2, V O1, V O, MARGSEL, MARGTOL Input Hysteresis (Both Threshods), 6 mv V O2, V O1, V O, MARGSEL, MARGTOL Input Current High, V IH = V BIAS = 2.5V, Current Fows Into Pin 25 4 µa V O2, V O1, V O, MARGSEL, MARGTOL Input Current Low, V IL = V, V BIAS = 2.5V, Current Fows Out of Pin 25 4 µa V O2, V O1, V O, MARGSEL, MARGTOL EN Pin Threshod = Off to On, V BIAS = 2.5V = On to Off, V BIAS = 2.5V = Off to On, V BIAS =2.2V to 3.6V = On to Off, V BIAS =2.2V to 3.6V.9.36 V BIAS V BIAS V V V V EN Pin Logic High Current V EN = V BIAS = 2.5V µa ma ma ma ma ma ma ma ma A A A V V 4 For more information 37fc

5 LT37 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. C OUT = 15µF (Note 9), V IN = +.3V (Note 5), V BIAS = 2.5V uness otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS EN Pin Logic Low Current V EN = V.1 µa V BIAS Rippe Rejection V IN Rippe Rejection (Notes 3, 4, 5) Reference Votage Noise (REF/BYP Pin) Output Votage Noise V BIAS = + 1.5V AVG, V RIPPLE =.5V P-P, f RIPPLE = 12Hz, V IN = 3mV, I OUT = 2.5A 75 db V BIAS = 2.5V, V RIPPLE = 5mV P-P, f RIPPLE = 12Hz, 66 db V IN = 3mV, I OUT = 2.5A C REF/BYP = 1nF, BW = 1Hz to 1kHz 1 µv RMS = 1V, I OUT = 5A, C REF/BYP = 1nF, C OUT = 15µF, BW = 1Hz to 1kHz Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The LT37 reguators are tested and specified under puse oad conditions such that T J T A. The LT37E is 1% tested at T A = 25 C. Performance at 4 C and 125 C is assured by design, characterization and correation with statistica process contros. The LT37I is guaranteed over the 4 C to 125 C operating junction temperature range. The LT37MP is 1% tested and guaranteed over the 55 C to 125 C operating junction temperature range. Note 3: To maintain proper performance and reguation, the BIAS suppy votage must be higher than the IN suppy votage. For a given, the BIAS votage must satisfy the foowing conditions: 2.2V V BIAS 3.6V and V BIAS ( V). For.95V, the minimum BIAS votage is imited to 2.2V. Note 4: Operating conditions are imited by maximum junction temperature. The reguated output votage specification does not appy for a possibe combinations of input votage and output current. When operating at maximum output current, imit the input votage range to V IN < + 5mV. 25 µv RMS Note 5: The LT37 incorporates safe operating area protection circuitry. Current imit decreases as the V IN - votage increases. Current imit fodback starts at V IN > 5mV. See the Typica Performance Characteristics for a graph of Current Limit vs V IN votage. The current imit fodback feature is independent of the therma shutdown circuity. Note 6: Dropout votage, V DO, is the minimum input to output votage differentia at a specified output current. In dropout, the output votage equas V IN V DO. Note 7: pin current is tested with V IN = (NOMINAL) + 3mV and a current source oad. VIOC is a buffered output determined by the vaue of as programmed by the V O2 -V O pins. VIOC s output is independent of the margining function. Note 8: Reverse output current is tested with the IN pins grounded and the OUT + SENSE pins forced to the rated output votage. This is measured as current into the OUT + SENSE pins. Note 9: Frequency Compensation: The LT37 must be frequency compensated at its OUT pins with a minimum C OUT of 15µF configured as a custer of (15 ) 1µF ceramic capacitors or as a graduated custer of 1µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear Technoogy ony recommends X5R or X7R dieectric capacitors. For more information 37fc 5

6 LT37 TYPICAL PERFORMAE CHARACTERISTICS DROPOUT VOLTAGE (mv) Dropout Votage vs I OUT V IN = (NOMINAL) T J = 25 C = 1.8V V BIAS = 3.3V =.8V V BIAS = 2.5V OUTPUT CURRENT (A) DROPOUT VOLTAGE (mv) Dropout Votage vs Temperature V IN = (NOMINAL) I OUT = 1A 5 = 1.8V, V BIAS = 3.3V =.8V, V BIAS = 2.5V = 1.2V, V BIAS = 3.3V DROPOUT VOLTAGE (mv) Dropout Votage vs Temperature V IN = (NOMINAL) I OUT = 2.5A = 1.8V, V BIAS = 3.3V =.8V, V BIAS = 2.5V = 1.2V, V BIAS = 3.3V G1 37 G2 37 G3 DROPOUT VOLTAGE (mv) Dropout Votage vs Temperature V IN = (NOMINAL) I OUT = 5A 3 = 1.8V, V BIAS = 3.3V =.8V, V BIAS = 2.5V = 1.2V, V BIAS = 3.3V G4 DROPOUT VOLTAGE (mv) Dropout Votage vs V BIAS I OUT = 5A T J = 25 C OUT = 1.8V OUT = 1.5V OUT =.8V BIAS VOLTAGE (V) 37 G5 OUTPUT VOLTAGE (V) Output Votage (.8V) vs Temperature I LOAD = 1mA G6 OUTPUT VOLTAGE (V) Output Votage (1V) vs Temperature I LOAD = 1mA G7 OUTPUT VOLTAGE (V) Output Votage (1.2V) vs Temperature I LOAD = 1mA G8 OUTPUT VOLTAGE (V) Output Votage (1.5V) vs Temperature I LOAD = 1mA G9 6 For more information 37fc

7 TYPICAL PERFORMAE CHARACTERISTICS LT37 OUTPUT VOLTAGE (V) Output Votage (1.8V) vs Temperature I LOAD = 1mA G1 PIN CURRENT (ma) Pin Current vs I OUT V IN = + 3mV T J = 25 C = 1.8V, V BIAS = 3.3V = 1.2V, V BIAS = 3.3V =.8V, V BIAS = 2.5V OUTPUT CURRENT (A) 37 G11 5 REF/BYP VOLTAGE (mv) REF/BYP Pin Votage vs Temperature C REF/BYP =.1µF G12 BIAS PIN CURRENT (µa) BIAS Pin Current in Nap Mode V BIAS = 2.5V V EN = V BIAS PIN CURRENT (ma) BIAS Pin Current vs I OUT V IN = + 3mV T J = 25 C = 1.8V V BIAS = 3.3V =.8V V BIAS = 2.5V UVLO THRESHOLD VOLTAGE (V) BIAS Pin Undervotage Lockout Threshod V BIAS FALLING V BIAS RISING OUTPUT CURRENT (A) G13 37 G14 37 G15 ENABLE PIN THRESHOLD (V) EN Pin Threshods V BIAS = 2.5V EN PIN RISING EN PIN FALLING ENABLE/DISABLE THRESHOLD (V) Enabe Pin Threshod and Hysteresis vs V BIAS T J = 55 C TO 125 C TYPICAL HYSTERESIS = 15mV V BIAS TYP ENABLE MAX ENABLE MIN DISABLE TYP DISABLE PWRGD TRESHOLD VOLTAGE (V) PWRGD Threshod Votage V BIAS = 2.5V = 1V RISING FALLING G BIAS VOLTAGE (V) 4 37 G G18 For more information 37fc 7

8 LT37 TYPICAL PERFORMAE CHARACTERISTICS PWRGD V OL VOLTAGE (mv) PWRGD V OL vs Temperature V BIAS = 2.5V I PWRGD = 2µA LOGIC INPUT THRESHOLD VOLTAGE (V) Logic Input Threshod Votages Logic Low to Hi-Z State Transitions SEE APPLICATIONS INFORMATION FOR MORE DETAILS INPUT RISING LOGIC LOW TO Hi-Z INPUT FALLING LOGIC Hi-Z TO LOW LOGIC INPUT THRESHOLD VOLTAGE (V) Logic Input Threshod Votages Logic Hi-Z to High State Transitions V BIAS = 3.3V LOGIC Hi-Z TO HIGH THRESHOLD IS RELATIVE TO V BIAS VOLTAGE SEE APPLICATIONS INFORMATION FOR MORE DETAILS INPUT FALLING LOGIC HIGH TO Hi-Z INPUT RISING LOGIC Hi-Z TO HIGH G19 37 G2 37 G21 EN PIN LOGIC HIGH CURRENT (µa) EN Pin Logic High Current V EN = V BIAS = 2.5V G22 LOGIC PIN INPUT CURRENT (µa) Logic Pin Input Current, High State V LOGIC = V BIAS = 2.5V CURRENT FLOWS INTO THE PIN G23 LOGIC PIN INPUT CURRENT (µa) Logic Pin Input Current, Low State V BIAS = 2.5V V LOGIC = V CURRENT FLOWS OUT OF THE PIN G24 SENSE PIN CURRENT (µa) SENSE Pin Current V BIAS = 2.5V =.8V CURRENT FLOWS INTO SENSE SENSE PIN CURRENT (µa) SENSE Pin Current V BIAS = 3.3V = 1.8V CURRENT FLOWS INTO SENSE CURRENT LIMIT (A) Current Limit vs Temperature 7.5 V IN (NOMINAL) = 3mV = 1.8V, V BIAS = 3.3V 5.25 = 1.2V, V BIAS = 3.3V =.8V, V BIAS = 2.5V G25 37 G26 37 G27 8 For more information 37fc

9 TYPICAL PERFORMAE CHARACTERISTICS LT37 CURRENT LIMIT (A) Current Limit vs V IN V BIAS = 3.3V T J = 25 C = 1.8V = 1.2V =.8V IN-TO-OUT VOLTAGE DIFFERENTIAL (V) 2. BIAS PIN RIPPLE REJECTION (db) BIAS Pin Rippe Rejection V IN = 1.3V = 1V I OUT = 5A C OUT = 1µF + 4.7µF + 2.2µF 2 V BIAS = 2.5V + 5mV P-P 1 V BIAS = 2.7V + 5mV P-P V BIAS = 3.3V + 5mV P-P 1 1 1k 1k 1k 1M 1M FREQUEY (Hz) IN PIN RIPPLE REJECTION (db) IN Pin Rippe Rejection 1 1 C OUT = 117µF C OUT = 16.9µF = 1V V IN = 1.3V + 5mV P-P RIPPLE V BIAS = 2.5V I OUT = 1A 1k 1k 1k 1M 1M FREQUEY (Hz) 37 G28 37 G29 37 G3 IN PIN RIPPLE REJECTION (db) PSRR (db) IN Pin Rippe Rejection 3 C OUT = 117µF C OUT = 16.9µF 2 = 1V 1 V IN = 1.3V + 5mV P-P RIPPLE V BIAS = 2.5V I OUT = 5A 1 1 1k 1k 1k 1M 1M FREQUEY (Hz) IN Pin Rippe Rejection vs V IN, 1V/1A 37 G mV 11 P-P RIPPLE ON V IN C OUT = 16.9μF 1 V BIAS = 2.5V RIPPLE AT f = 1kHz 9 T A = 25 C 8 7 RIPPLE AT f = 1kHz RIPPLE AT f = 1MHz AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 37 G34 PSRR (db) PSRR (db) IN Pin Rippe Rejection vs V IN, 1V/5A 12 5mV 11 P-P RIPPLE ON V IN C OUT = 16.9μF 1 V BIAS = 2.5V 9 T A = 25 C 8 RIPPLE AT f = 1kHz RIPPLE AT f = 1kHz 3 2 RIPPLE AT f = 1MHz AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) IN Pin Rippe Rejection vs V IN, 1V/5A 37 G mV P-P RIPPLE ON V IN C OUT = 117μF 1 V BIAS = 2.5V 9 T A = 25 C 8 RIPPLE AT f = 1kHz 7 6 RIPPLE AT f = 1MHz 5 4 RIPPLE AT f = 1kHz AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 37 G35 PSRR (db) PSRR (db) IN Pin Rippe Rejection vs V IN, 1V/2.5A mV P-P RIPPLE ON V IN 1 C OUT = 16.9μF V BIAS = 2.5V 9 T A = 25 C RIPPLE AT f = 1kHz RIPPLE AT f = 1kHz RIPPLE AT f = 1MHz AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) IN Pin Rippe Rejection vs V IN, 1V/2.5A 37 G mV P-P RIPPLE ON V IN C OUT = 117μF 1 V BIAS = 2.5V 9 T A = 25 C 8 RIPPLE AT f = 1kHz RIPPLE AT f = 1MHz 4 RIPPLE AT f = 1kHz AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 37 G36 For more information 37fc 9

10 LT37 TYPICAL PERFORMAE CHARACTERISTICS PSRR (db) IN Pin Rippe Rejection vs V IN, 1V/1A mV P-P RIPPLE ON V IN C OUT = 117μF 1 V BIAS = 2.5V 9 T A = 25 C 8 RIPPLE AT f = 1kHz 7 6 RIPPLE AT f = 1MHz 5 4 RIPPLE AT f = 1kHz AVERAGE INPUT/OUTPUT DIFFERENTIAL (V) 37 G37 MINIMUM BIAS VOLTAGE (V) Minimum BIAS Votage vs Temperature I OUT = 5A = 1.8V = 1.2V =.8V G38 MINIMUM BIAS VOLTAGE (V) Minimum BIAS Votage vs I OUT V IN = (NOMINAL) + 3mV = 1%, T J = 25 C = 1.8V = 1.5V = 1.2V =.8V TO 1V OUTPUT CURRENT (A) 37 G39 MINIMUM BIAS VOLTAGE (V) Minimum BIAS Votage vs I OUT = 5A T J = 25 C OUTPUT VOLTAGE (V) 37 G4 LOAD REGULATION (mv) 2 4 Load Reguation 6 V IN = (NOMINAL) + 3mV V BIAS = 3.3V I OUT = 1mA TO 5A 8 =.8V = 1.2V = 1.8V G41 BIAS VOLTAGE LINE REGULATION (µv) Bias Votage Line Reguation V BIAS = 2.2V TO 3.6V V IN = 1.1V =.8V I OUT = 1mA G42 BIAS VOLTAGE LINE REGULATION (µv) Bias Votage Line Reguation V BIAS = 3.25V TO 3.6V V IN = 2.1V = 1.8V I OUT = 1mA G43 INPUT VOLTAGE LINE REGULATION (µv) Input Votage Line Reguation V BIAS = 3.3V V IN = 1.5V TO 2.7V =.8V I OUT = 1mA G44 INPUT VOLTAGE LINE REGULATION (µv) Input Votage Line Reguation V BIAS = 3.3V V IN = 2.5V TO 2.7V = 1.8V I OUT = 1mA G45 1 For more information 37fc

11 TYPICAL PERFORMAE CHARACTERISTICS OUTPUT VOLTAGE START-UP TIME (ms) Output Votage Start-Up Time vs C REF/BYP V BIAS = 2.5V TO 3.3V I OUT = 1mA C OUT = 1µF + 4.7µF + 2.2µF T J = 25 C SEE APPLICATIONS INFORMATION FOR START-UP DETAILS REF/BYP CAPACITAE (µf) 37 G46 NAP MODE RECOVERY TIME (µs) Nap Mode Recovery Time vs I OUT 4 VBIAS = 3.3V 35 V IN = (NOM) + 3mV EN = LOW TO HIGH 3 I OUT = 5A (SET BY A RESISTOR LOAD) T J = 25 C 25 = 1.8V, C OUT = 117µF 2 = 1.2V, C OUT = 117µF 15 =.8V, C OUT = 117µF OUTPUT CURRENT (A) 37 G47 NOISE SPECTRAL DENSITY (µv/ Hz) LT37 Output Noise Spectra Density V BIAS = 2.5V = 1V I OUT = 5A C OUT = 16.9µF C REF/BYP =.1µF k 1k 1k FREQUEY (Hz) 37 G48 RMS Output Noise vs Output Current Output Noise (1Hz to 1kHz) Input Votage Line Transient Response OUTPUT NOISE (µv RMS ) V IN = (NOMINAL) + 3mV V BIAS = 3.3V C OUT = 16.9µF = 1.8V = 1.2V =.8V OUTPUT CURRENT (A) 1µV/DIV = 1V I OUT = 5A C OUT = 16.9µF 1ms/DIV 37 G5 1mV/DIV V IN 5mV/DIV V IN = 1.3V = 1V I OUT = 5A C OUT = 16.9µF 2µs/DIV 37 G51 37 G49 Bias Votage Line Transient Response VIOC Ampifier IN-to-OUT Servo Votage VIOC Ampifier Output Current vs Temperature 1mV/DIV V BIAS 2mV/DIV V IN = 1.3V V BIAS = 2.5V = 1V I OUT = 5A C OUT = 16.9µF 2µs/DIV 37 G52 VIOC IN-TO-OUT SERVO VOLTAGE (mv) V BIAS = 2.5V VIOC AMPLIFIER OUTPUT CURRENT (µa) I VIOC SOURCING I VIOC SINKING G53 37 G54 For more information 37fc 11

12 LT37 TYPICAL PERFORMAE CHARACTERISTICS Transient Load Response Transient Load Response 5mV/DIV AC-COUPLED 5mV/DIV AC-COUPLED I OUT 2A/DIV I = 5mA TO 5A = 1V 2µs/DIV C OUT = 1µF + 4.7µF + 2.2µF I OUT t RISE /t FALL = 1ns 37 G55 I OUT 2A/DIV I = 5mA TO 5A = 1V 2µs/DIV C OUT = 117µF I OUT t RISE /t FALL = 1ns 37 G56 Transient Load Response Transient Load Response 5mV/DIV AC-COUPLED 5mV/DIV AC-COUPLED I OUT 2A/DIV I = 5mA TO 5A = 1V 2µs/DIV C OUT = 1µF + 4.7µF + 2.2µF I OUT t RISE /t FALL = 1µs 37 G57 I OUT 2A/DIV I = 5mA TO 5A = 1V 2µs/DIV C OUT = 117µF I OUT t RISE /t FALL = 1µs 37 G58 12 For more information 37fc

13 PIN FUTIONS VIOC (Pin 1): Votage for In-to-Out Contro. The IC incorporates a unique tracking function to contro a buck reguator powering the LT37 s input. The VIOC pin is the output of this tracking function that drives the buck reguator to maintain the LT37 s input votage at + 3mV. This function maximizes efficiency and minimizes power dissipation. See the Appications Information section for more information on proper contro of the buck reguator. PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that activey pus ow if any one of these faut modes is detected: is ess than 9% of (NOMINAL) on the rising edge of. drops beow 85% of (NOMINAL) for more than 25µs. Junction temperature typicay exceeds 145 C. V BIAS is ess than its undervotage ockout threshod. The OUT-to-IN reverse-current detector activates. See the Appications Information section for more information on PWRGD faut modes. REF/BYP (Pin 3): Reference Fiter. The pin is the output of the bandgap reference and has an impedance of approximatey 19kΩ. This pin must not be externay oaded. Bypassing the REF/BYP pin to with a 1nF capacitor decreases output votage noise and provides a soft-start function to the reference. LTC recommends the use of a high quaity, ow eakage capacitor. See the Appications Information section for more information on noise and output votage margining considerations. (Pins 4, 9-14, 2, 26, 29): Ground. The exposed pad (Pin 29) of the QFN package is an eectrica coection to. To ensure proper eectrica and therma performance, soder Pin 29 to the PCB ground and tie to a pins of the package. These pins are fused to the interna die attach padde and the exposed pad to optimize heat sinking and therma resistance characteristics. See the Appications Information section for therma considerations and cacuating junction temperature. LT37 IN (Pins 5, 6, 7, 8): Input Suppy. These pins suppy power to the high current pass transistor. Tie a IN pins together for proper performance. The LT37 requires a bypass capacitor at IN to maintain stabiity and ow input impedance over frequency. A 47µF input bypass capacitor suffices for most battery and power pane impedances. Minimizing input trace inductance optimizes performance. Appications that operate with ow V IN - differentia votages and that have arge, fast oad transients may require much higher input capacitor requirements to prevent the input suppy from drooping and aowing the reguator to enter dropout. See the Appications Information section for more information on input capacitor requirements. OUT (Pins 15, 16, 17, 18): Output. These pins suppy power to the oad. Tie a OUT pins together for proper performance. A minimum output capacitance of 15µF is required for stabiity. LTC recommends ow ESR, X5R or X7R dieectric ceramic capacitors for best performance. A parae ceramic capacitor combination of 1µF + 4.7µF + 2.2µF or 15 1µF ceramic capacitors in parae provide exceent stabiity and oad transient response. Large oad transient appications require arger output capacitors to imit peak votage transients. See the Appications Information section for more information on output capacitor requirements. SENSE (Pin 19): Kevin Sense for OUT. The SENSE pin is the inverting input to the error ampifier. Optimum reguation is obtained when the SENSE pin is coected to the OUT pins of the reguator. In critica appications, the resistance (R P ) of PCB traces between the reguator and the oad cause sma votage drops, creating a oad reguation error at the point of oad. Coecting the SENSE pin at the oad instead of directy to OUT eiminates this votage error. Figure 1 iustrates this Kevin-Sense coection method. Note that the votage drop across the externa PCB traces adds to the dropout votage of the reguator. The SENSE pin input bias current depends on the seected output votage. SENSE pin input current varies from 5µA typicay at =.8V to 3µA typicay at = 1.8V. For more information 37fc 13

14 LT37 PIN FUTIONS + V BIAS + V IN BIAS EN SENSE IN OUT V O2 LT37 V O1 PWRGD V O MARGSEL MARGTOL VIOC REF/BYP MARGSEL (Pin 21): Margining Enabe and Poarity Seection. This three-state pin determines both the poarity and the active state of the margining function. The ogic ow threshod is ess than 25mV referenced to and enabes negative votage margining. The ogic high threshod is greater than V BIAS 25mV and enabes positive votage margining. The votage range between these two ogic threshods as set by a window comparator defines the ogic Hi-Z state and disabes the margining function. MARGTOL (Pin 22): Margining Toerance. This threestate pin seects the absoute vaue of margining (1%, 3% or 5%) if enabed by the MARGSEL input. The ogic ow threshod is ess than 25mV referenced to and enabes either ±1% change in depending on the state of the MARGSEL pin. The ogic high threshod is greater than V BIAS 25mV and enabes either ±5% change in depending on the state of the MARGSEL pin. The votage range between these two ogic threshods as set by a window comparator defines the ogic Hi-Z state and enabes either ±3% change in depending on the state of the MARGSEL pin. R P R P Figure 1. Kevin Sense Coection 37 F1 LOAD V O, V O1 and V O2 (Pins 23, 24, 25): Output Votage Seect. These three-state pins combine to seect a nomina output votage from.8v to 1.8V in increments of 5mV. Output votage is imited to 1.8V maximum by an interna override of V O1 when V O2 = high. The input ogic ow threshod is ess than 25mV referenced to and the ogic high threshod is greater than V BIAS 25mV. The range between these two threshods as set by a window comparator defines the ogic Hi-Z state. See Tabe 1 in the Appications Information section that defines the V O2, V O1 and V O settings versus. BIAS (Pin 27): Bias Suppy. This pin suppies current to the interna contro circuitry and the output stage driving the pass transistor. The LT37 requires a minimum 2.2µF bypass capacitor for stabiity and proper operation. To ensure proper operation, the BIAS votage must satisfy the foowing conditions: 2.2V V BIAS 3.6V and V BIAS ( V). For.95V, the minimum BIAS votage is imited to 2.2V. EN (Pin 28): Enabe. This pin enabes/disabes the output device ony. The interna reference and a support functions are active if V BIAS is above its UVLO threshod. Puing EN ow keeps the reference circuit active, but disabes the output pass transistor and puts the LT37 into a ow power nap mode. The maximum rising EN threshod is ratioed to.56 % of V BIAS and the minimum faing ENx threshod is.36 % of V BIAS. Drive the EN pin with either a digita ogic port or an open-coector NPN or an opendrain NMOS terminated with a pu-up resistor to V BIAS. The pu-up resistor must be ess than 35k to meet the V IH condition of the EN pin. If unused, coect EN to BIAS. 14 For more information 37fc

15 + BLOCK DIAGRAM LT37 27 BIAS IN 5-8 UVLO AND THERMAL SHUTDOWN I SENSE REF/BYP + EAMP LDO CORE BUF OUT SENSE 19 DETECT PWRGD 2 1 VIOC 4,9-14,2,26,29 + (NOM) + 3mV PROGRAM CONTROL V REF REF/BYP 6mV 3 28 EN O2 O1 O MARGSEL MARGTOL 25V 24V 23V BD LOGIC HIGH STATE EN 1k TO INTERNAL ENABLE SEE ENABLE THRESHOLD CURVE V BIAS.25V + V O2, V O1, VO MARGSEL OR MARGTOL V BIAS 1k 1k V BIAS.9V.75V LOGIC Hi-Z STATE + + TO LOGIC HIGH IF IN > V BIAS.25V HIGH IF IN < V BIAS.9V AND IN >.75V HIGH IF IN <.25V LOGIC LOW STATE.25V + For more information 37fc 15

16 LT37 APPLICATIONS INFORMATION Introduction Current generation FPGA and ASIC processors pace stringent demands on the power suppies that power the core, I/O and transceiver chaes. These microprocessors may cyce oad current from near zero to amps in tens of nanoseconds. Output votage specifications, especiay in the 1V range, require tight toerances incuding transient response as part of the requirement. Some ASIC processors require ony a singe output votage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power suppy votages for the processor core, the I/O, and the transceivers. Often, these suppy votages must be ow noise and high bandwidth to achieve the owest bit-error rates. These requirements mandate the need for very accurate, ow noise, high current, very high speed reguator circuits that operate at ow input and output votages. The LT37 is a ow votage, UtraFast transient response inear reguator. The device suppies up to 5A of output current with a typica dropout votage of 85mV. A.1µF reference bypass capacitor decreases output votage noise to 25µV RMS (BW = 1Hz to 1kHz). The LT37 s high bandwidth provides UtraFast transient response using ow ESR ceramic output capacitors (15µF minimum), saving buk capacitance, PCB area and cost. The LT37 s features permit state-of-the-art inear reguator performance. The LT37 is idea for high performance FPGAs, microprocessors, sensitive communication suppies, and high current ogic appications that aso operate over ow input and output votages. Output votage for the LT37 is digitay seectabe in 5mV increments over a.8v to 1.8V range. A margining function aows the user to adjust system output votage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function, which if enabed by the user, contros an upsteam reguator powering the LT37 s input (see Figure 8). This tracking function drives the buck reguator to maintain the LT37 s input votage to + 3mV. This input-to-output votage contro aows the user to change the reguator output votage, and have the switching reguator powering the LT37 s input to track to the optimum input votage with no component changes. 16 For more information This combines the efficiency of a switching reguator with superior inear reguator response. It aso permits therma management of the system even with a maximum 5A output oad. LT37 interna protection incudes input undervotage ockout (UVLO), reverse-current protection, precision current imiting with power fodback and therma shutdown. The LT37 reguator is avaiabe in a thermay enhanced 28-ead, 4mm 5mm QFN package. The LT37 s architecture drives an interna N-chae power MOSFET as a source foower. This configuration permits a user to obtain an extremey ow dropout, Utra- Fast transient response reguator with exceent high frequency PSRR performance. The LT37 achieves superior reguator bandwidth and transient oad performance by eiminating expensive buk tantaum or eectroytic capacitors in the most modern and demanding microprocessor appications. Users reaize significant cost savings as a additiona buk capacitance is removed. The additiona savings of insertion cost, purchasing/inventory cost and board space are readiy apparent. Precision incrementa output votage contro accommodates egacy and future microprocessor power suppy votages. Output capacitor networks simpify to direct parae combinations of ceramic capacitors. Often, the high frequency ceramic decouping capacitors required by these various FPGA and ASIC processors are sufficient to stabiize the system (see Stabiity and Output Capacitance section). This reguator design provides ampe bandwidth and responds to transient oad changes in a few hundred nanoseconds versus reguators that respond in many microseconds. The LT37 aso incorporates precision current imiting, enabe/disabe contro of output votage and integrated overvotage and therma shutdown protection. The LT37 s unique design combines the benefits of ow dropout votage, high functiona integration, precision performance and UtraFast transient response, as we as providing significant cost savings on the output capacitance needed in fast oad transient appications. As ower votage appications become increasingy prevaent with higher frequency switching power suppies, the LT37 offers superior reguation and an appreciabe 37fc

17 LT37 APPLICATIONS INFORMATION component cost savings. The LT37 steps to the next eve of performance for the atest generation FPGAs, DSPs and microprocessors. The simpe versatiity and benefits derived from these circuits exceed the power suppy needs of today s high performance microprocessors. Programming Output Votage Three tri-eve input pins, V O2, V O1 and V O, seect the vaue of output votage. Tabe 1 iustrates the 3-bit digita word to output votage resuting from setting these pins high, ow or aowing them to foat. These pins may be tied high or ow by either pin-strapping them to V BIAS or driving them with digita ports. Pins that foat may either actuay foat or require ogic that has Hi-Z output capabiity. This aows output votage to be dynamicay changed if necessary. Output votage is seectabe from a minimum of.8v to a maximum of 1.8V in increments of 5mV. The MSB, V O2, sets the pedesta votage, and the LSB s, V O1 and V O increment. Output votage is imited to 1.8V maximum by an interna override of V O1 (defaut to ow) when V O2 = high. Tabe 1: V O2 to V O Settings vs Output Votage V O2 V O1 V O (NOM) V O2 V O1 V O (NOM).8V Z V Z.85V Z Z 1.4V 1.9V Z Z Z 1.45V Z.95V Z Z 1 1.5V Z Z 1.V Z V Z 1 1.5V Z 1 Z 1.6V 1 1.1V Z V 1 Z 1.15V 1 X 1.7V V 1 X Z 1.75V Z 1.25V 1 X 1 1.8V Z Z 1.3V X = Don t Care, = Low, Z = Foat, 1 = High The input ogic ow threshod is ess than 25mV referenced to and the ogic high threshod is greater than V BIAS 25mV. The range between these two threshods as set by a window comparator defines the ogic Hi-Z state. REF/BYP Votage Reference This pin is the buffered output of the interna bandgap reference and has an output impedance of 19kΩ. The design incudes an interna compensation poe at f C = 4kHz. A 1nF REF/BYP capacitor to creates a owpass poe at f LP = 84Hz. The 1nF capacitor decreases reference votage noise to about 1µV RMS and soft-starts the reference. The LT37 ony soft-starts the reference votage during an initia turn-on sequence. If the EN pin is togged ow after initia turn-on, the reference remains powered-up. Therefore, togging the EN pin from ow to high does not soft-start the reference. Ony by turning the BIAS suppy votage on and off wi the reference be soft-started. Output votage noise is the RMS sum of the reference votage noise in addition to the ampifier noise. The REF/BYP pin must not be DC oaded by anything except for appications that parae other LT37 reguators for higher output currents. Consut the Appications Section on Paraeing for further detais. Output Votage Margining Two tri-eve input pins, MARGSEL (poarity) and MARGTOL (scae), seect the poarity and amount of output votage margining. Margining is programmabe in increments of ±1%, ±3% and ±5%. Margining is internay impemented as a scaing of the reference votage. Tabe 2 iustrates the 2-bit digita word to output votage margining resuting from setting these pins high, ow or aowing them to foat. These pins may be set high or ow by either pin-strapping them to V BIAS or driving them with digita ports. Pins that foat may either actuay foat or require ogic that has Hi-Z output capabiity. This aows output votage to be dynamicay margined if necessary. The MARGSEL pin determines both the poarity and the active state of the margining function. The ogic ow threshod is ess than 25mV referenced to and enabes negative votage margining. The ogic high threshod is greater than V BIAS 25mV and enabes positive votage margining. The votage range between these two ogic threshods as set by a window comparator defines the ogic Hi-Z state and disabes the margining function. For more information 37fc 17

18 LT37 APPLICATIONS INFORMATION The MARGTOL pin seects the absoute vaue of margining (1%, 3% or 5%) if enabed by the MARGSEL input. The ogic ow threshod is ess than 25mV referenced to and enabes either ±1% change in depending on the state of the MARGSEL pin. The ogic high threshod is greater than V BIAS 25mV and enabes either ±5% change in depending on the state of the MARGSEL pin. The votage range between these two ogic threshods as set by a window comparator defines the ogic Hi-Z state and enabes either ±3% change in depending on the state of the MARGSEL pin. Tabe 2: Programming Margining MARGSEL MARGTOL % OF (NOM) 1 Z Z Z Z Z Z Enabe Function Turning On and Off The EN pin enabes/disabes the output device ony. The LT37 reference and a support functions remain active if V BIAS is above its UVLO threshod. Puing the EN pin ow puts the LT37 into nap mode. In nap mode, the reference circuit is active, but the output is disabed and quiescent current decreases. Drive the EN pin with either a digita ogic port or an opencoector NPN or an open-drain NMOS terminated with a pu-up resistor to V BIAS. The pu-up resistor must be ess than 35k to meet the V IH condition of the EN pin. If unused, coect EN to BIAS. Input Undervotage Lockout on BIAS Pin An interna undervotage ockout (UVLO) comparator monitors the BIAS suppy votage. If V BIAS drops beow the UVLO threshod, a functions shut down, the pass transistor is gated off and output current fas to zero. The typica BIAS pin UVLO threshod is 1.55V on the rising edge of V BIAS. The UVLO circuit incorporates about 15mV of hysteresis on the faing edge of V BIAS. High Efficiency Linear Reguator Input-to-Output Votage Contro The VIOC (votage input-to-output contro) pin is a function to contro a switching reguator and faciitate a design soution that maximizes system efficiency at high oad currents and sti provides ow dropout votage performance. The VIOC pin is the output of an integrated transconductance ampifier that sources and sinks about 25µA of current. It typicay reguates the output of most LTC switching reguators or LTM power modues, by sinking current from the ITH compensation node. The VIOC function contros a buck reguator powering the LT37 s input by maintaining the LT37 s input votage to + 3mV. This 3mV V IN - differentia votage is chosen to provide fast transient response and good high frequency PSRR whie minimizing power dissipation and maximizing efficiency. For exampe, 1.5V to 1.2V conversion and 1.3V to 1V conversion yied 1.5W maximum power dissipation at 5A fu output current. Figure 2 depicts that the switcher s feedback resistor network sets the maximum switching reguator output votage if the inear reguator is disabed. However, once the LT37 is enabed, the VIOC feedback oop decreases the switching reguator output votage back to + 3mV. Using the VIOC function creates a feedback oop between the LT37 and the switching reguator. As such, the feedback oop must be frequency compensated for stabiity. Fortunatey, the coection of VIOC to many LTC switching reguator ITH pins represents a high impedance characteristic which is the optimum circuit node to frequency compensate the feedback oop. Figure 2 iustrates the typica frequency compensation network used at the VIOC node to. The VIOC ampifier characteristics are: g m = 3.2mS, I OUT = ±25µA, BW = 1MHz. If the VIOC function is not used, terminate the VIOC pin to with a sma capacitor (1pF) to prevent osciations. 18 For more information 37fc

19 APPLICATIONS INFORMATION LT37 REF SWITCHING REGULATOR + PWM + FB I TH IN REFEREE LT37 V REF + 3mV OUT VIOC LOAD 37 F2 Figure 2. VIOC Contro Bock Diagram PWRGD Power Good PWRGD pin is an open-drain NMOS digita output that activey pus ow if any one of these faut modes is detected: is ess than 9% of (NOMINAL) on the rising edge of. drops beow 85% of (NOMINAL) for more than 25µs. V BIAS is ess than its undervotage ockout threshod. The OUT-to-IN reverse-current detector activates. Junction temperature exceeds 145 C typicay.* *The junction temperature detector is an eary warning indicator that trips approximatey 2 C before therma shutdown engages. Stabiity and Output Capacitance The LT37 s feedback oop requires an output capacitor for stabiity. Choose C OUT carefuy and mount it in cose proximity to the LT37 s OUT and pins. Incude wide routing panes for OUT and to minimize inductance. If possibe, mount the reguator immediatey adjacent to the appication oad to minimize distributed inductance for optima oad transient performance. Point-of-Load appications present the best case ayout scenario for extracting fu LT37 performance. Low ESR, X5R or X7R ceramic chip capacitors are the LTC recommended choice for stabiizing the LT37. Additiona buk capacitors distributed beyond the immediate decouping capacitors are acceptabe as their parasitic ESL and ESR, combined with the distributed PCB inductance isoates them from the primary compensation poe provided by the oca surface mount ceramic capacitors. The LT37 requires a minimum output capacitance of 15µF for stabiity. LTC strongy recommends that the output capacitor network consist of severa ow vaue ceramic capacitors in parae. Why Do Mutipe, Sma-Vaue Output Capacitors Coected in Parae Work Better? The LT37 s unity-gain bandwidth with C OUT of 15µF is about 1MHz at its fu-oad current of 5A. Surface mounted MLCC capacitors have a sef-resonance frequency of f R = 1/(2π LC), which must be pushed to a frequency higher than the reguator bandwidth. Standard MLCC capacitors are acceptabe. To keep the resonant frequency greater than 1MHz, the product 1/(2π LC) must be greater than 1MHz. At this bandwidth, PCB vias can add significant inductance, thus the fundamenta decouping capacitors must be mounted on the same pane as the LT37. Typica 63 or 85 case-size capacitors have an ESL of ~8pH and PCB mounting can contribute up to ~2pH. Thus, it becomes necessary to reduce the parasitic inductance by using a parae capacitor combination. A For more information 37fc 19

20 LT37 APPLICATIONS INFORMATION suitabe methodoogy must contro this paraeing as capacitors with the same sef-resonant frequency, f R, wi form a tank circuit that can induce ringing of their own accord. Sma amounts of ESR (5mΩ to 2mΩ) have some benefit in dampening the resonant oop, but higher ESRs degrade the capacitor response to transient oad steps with rise/fa times ess than 1µs. The most area efficient parae capacitor combination is a graduated 4/2/1 scae of f R of the same case size. Under these conditions, the individua ESLs are reativey uniform, and the resonance peaks are deconstructivey spread beyond the reguator bandwidth. The recommended parae combination that approximates 15µF is 1µF + 4.7µF + 2.2µF. Capacitors with case sizes arger than 85 have higher ESL and ower ESR (<5mΩ). Therefore, more capacitors with smaer vaues (<1µF) must be chosen. Users shoud consider new generation, ow inductance capacitors to push out f R and maximize stabiity. Refer to the surface mount ceramic capacitor manufacturer s data sheets for capacitor specifications. Figure 3 iustrates an optimum PCB ayout for the parae output capacitor combination, but aso iustrates the coection between the IN capacitor and the OUT capacitors to minimize the AC oop for fast oad transients. This tight bypassing coection minimizes EMI and optimizes bypassing. Many of the appications in which the LT37 exces, such as FPGA, ASIC processor or DSP suppies, typicay require a high frequency decouping capacitor network for the device being powered. This network generay consists of many ow vaue ceramic capacitors in parae. In some appications, this tota vaue of capacitance may be cose Lo-Z INPUT 47µF LT37 SENSE IN OUT 2.2µF 4.7µF 1µF LOAD PLANE to the LT37 s minimum 15µF capacitance requirement. This may reduce the required vaue of capacitance directy at the LT37 s output. Mutipe ow vaue capacitors in parae present a favorabe frequency characteristic that pushes many of the parasitic poes/zeroes beyond the LT37 s unity-gain crossover frequency. This technique iustrates the method that extracts the fu bandwidth performance of the LT37. Give additiona consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dieectrics, each with different behavior across temperature and appied votage. The most common dieectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dieectrics are good for providing high capacitances in a sma package, but they tend to have strong votage and temperature coefficients as shown in Figures 4 and 5. When used with a 5V reguator, a 16V 1µF Y5V capacitor can exhibit an effective vaue as ow as 1µF to 2µF for the DC bias votage appied and over the operating temperature range. The X5R and X7R dieectrics resut in more stabe characteristics and are more suitabe for use as the output capacitor. The X7R type has better stabiity across temperature, whie the X5R is ess expensive and is avaiabe in higher vaues. Care sti must be exercised when using X5R and X7R capacitors; the X5R and X7R codes ony specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can sti be significant enough to drop capacitor vaues beow appropriate eves. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating votage shoud be verified. Votage and temperature coefficients are not the ony sources of probems. Some ceramic capacitors have a piezoeectric response. A piezoeectric device generates votage across its terminas due to mechanica stress, simiar to the way a piezoeectric microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or therma transients. 37 F3 Figure 3. Exampe PCB Layout 2 For more information 37fc

21 APPLICATIONS INFORMATION CHANGE IN VALUE (%) BOTH CAPACITORS ARE 16V, 121 CASE SIZE, 1µF DC BIAS VOLTAGE (V) 37 F4 Stabiity and Input Capacitance The LT37 is stabe with a minimum capacitance of 47µF coected to its IN pins. Use ow ESR capacitors to minimize instantaneous votage drops under arge oad transient conditions. Large V IN droops during arge oad transients may cause the reguator to enter dropout with corresponding degradation in oad transient response. Increased vaues of input and output capacitance may be necessary depending on an appication s requirements. Sufficient input capacitance is critica as the circuit is intentionay operated cose to dropout to minimize power. Ideay, the output impedance of the suppy that powers IN shoud be ess than 1mΩ to support a 5A oad with arge transients. In cases where wire is used to coect a power suppy to the input of the LT37 (and aso from the ground of X5R Y5V Figure 4. Ceramic Capacitor DC Bias Characteristics CHANGE IN VALUE (%) BOTH CAPACITORS ARE 16V, 121 CASE SIZE, 1µF X5R Y5V F5 Figure 5. Ceramic Capacitor Temperature Characteristics For more information LT37 the LT37 back to the power suppy ground), arge input capacitors are required to avoid an unstabe appication. This is due to the inductance of the wire forming an LC tank circuit with the input capacitor and not a resut of the LT37 being unstabe. The sef inductance, or isoated inductance, of a wire is directy proportiona to its ength. However, the diameter of a wire does not have a major infuence on its sef inductance. For exampe, one inch of 18-AWG,.4 inch diameter wire has 28nH of sef inductance. The sef inductance of a 2-AWG isoated wire with a diameter of.26 inch is about haf the inductance of a 18-AWG wire. The overa sef inductance of a wire can be reduced in two ways. One is to divide the current fowing towards the LT37 between two parae conductors which fows in the same direction in each. In this case, the farther the wires are paced apart from each other, the more inductance wi be reduced, up to a 5% reduction when paced a few inches apart. Spitting the wires basicay coects two equa inductors in parae. However, when paced in cose proximity from each other, mutua inductance is added to the overa sef inductance of the wires. The most effective way to reduce overa inductance is to pace the forward and return-current conductors (the wire for the input and the wire for the return ground) in very cose proximity. Two 18-AWG wires separated by.5 inch reduce the overa sef inductance to about onefourth of a singe isoated wire. If the LT37 is powered by a battery mounted in cose proximity with ground and power panes on the same circuit board, a 47µF input capacitor is sufficient for stabiity. However, if the LT37 is powered by a distant suppy, use a ow ESR, arge vaue input capacitor on the order of 33µF. As power suppy output impedance varies, the minimum input capacitance needed for appication stabiity aso varies. Bias Pin Capacitance Requirements The BIAS pin suppies current to most of the interna contro circuitry and the output stage driving the pass transistor. The LT37 requires a minimum 2.2µF bypass capacitor for stabiity and proper operation. To ensure proper operation, the BIAS votage must satisfy the foowing conditions: 2.2V V BIAS 3.6V and V BIAS ( V). For.95V, the minimum BIAS votage is imited to 2.2V. 37fc 21