LT1498/LT MHz, 6V/µs, Dual/Quad Rail-to-Rail Input and Output Precision C-Load Op Amps FEATURES DESCRIPTION APPLICATIONS

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1 FEATURES n Rai-to-Rai Input and Output n 475 Max V OS from V + to V n Gain-Bandwidth Product: MHz n Sew Rate: 6V/μs n Low Suppy Current per Ampifi er: 1.7mA n Input Offset Current: 65 Max n Input Bias Current: 65 Max n Open-Loop Gain: Min n Low Input Noise Votage: 12nV/ Hz Typ n Wide Suppy Range: 2.2V to ±V n Large Output Drive Current: 3mA n Stabe for Capacitive Loads Up to,pf n Dua in 8-Pin PDIP and SO Package n Quad in Narrow 14-Pin SO APPLICATIONS n Driving A-to-D Converters n Active Fiters n Rai-to-Rai Buffer Ampifi ers n Low Votage Signa Processing n Battery-Powered Systems L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and C-Load is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. DESCRIPTION MHz, 6V/µs, Dua/Quad Rai-to-Rai Input and Output Precision C-Load Op Amps The LT 1498/LT1499 are dua/quad, rai-to-rai input and output precision C-Load op amps with a MHz gainbandwidth product and a 6V/μs sew rate. The are designed to maximize input dynamic range by deivering precision performance over the fu suppy votage. Using a patented technique, both input stages of the are trimmed, one at the negative suppy and the other at the positive suppy. The resuting guaranteed common mode rejection is much better than other rai-to-rai input op amps. When used as a unity-gain buffer in front of singe suppy 12-bit A-to-D converters, the are guaranteed to add ess than 1LSB of error even in singe 3V suppy systems. With 1 of suppy rejection, the maintain their performance over a suppy range of 2.2V to 36V and are specified for 3V, 5V and ±V suppies. The inputs can be driven beyond the suppies without damage or phase reversa of the output. These op amps remain stabe whie driving capacitive oads up to,pf. The LT1498 is avaiabe with the standard dua op amp configuration in 8-pin PDIP and SO packaging. The LT1499 features the standard quad op amp configuration and is avaiabe in a 14-pin pastic SO package. These devices can be used as pug-in repacements for many standard op amps to improve input/output range and precision. TYPICAL APPLICATION V IN V + /2 6.81k Singe Suppy khz 4th Order Butterworth Fiter 6.81k 11.3k 33pF pf 1/2 LT k 5.23k 47pF.2k pf + V + 1/2 LT TA1 V OUT 1 GAIN () Frequency Response 1k k k 1M M FREQUENCY (Hz) V IN = 2.7V P-P V + = 3V 1498 TA2 1

2 ABSOLUTE MAXIMUM RATINGS Tota Suppy Votage (V + to V )...36V Input Current... ±ma Output Short-Circuit Duration (Note 2)...Continuous Operating Temperature Range... 4 C to 85 C LT1498H/LT1499H... 4 C to 125 C LT1498MP C to 125 C (Note 1) Specifi ed Temperature Range (Note 4)... 4 C to 85 C LT1498H/LT1499H... 4 C to 125 C LT1498MP C to 125 C Junction Temperature... C Storage Temperature Range C to C Lead Temperature (Sodering, sec)...3 C PIN CONFIGURATION TOP VIEW TOP VIEW OUT A IN A 1 2 A 8 7 V + OUT B +IN A V 3 4 B 6 5 IN B +IN B N8 PACKAGE 8-LEAD PLASTIC DIP T JMAX = C, θ JA = 13 C/W TOP VIEW OUT A IN A V + OUT B A +IN A 3 6 IN B B V 4 5 +IN B S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = 13 C/W OUTA 1 IN A 2 +IN A 3 V + 4 +IN B 5 IN B 6 OUT B 7 A D B C 14 OUT D 13 IN D 12 +IN D 11 V +IN C 8 IN C 8 OUT C S PACKAGE 14-LEAD PLASTIC SO T JMAX = C, θ JA = C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1498CN8#PBF LT1498CN8#TRPBF LT1498CN8 8-Lead Pastic PDIP C to 7 C LT1498CS8#PBF LT1498CS8#TRPBF Lead Pastic SO C to 7 C LT1498IN8#PBF LT1498IN8#TRPBF LT1498IN8 8-Lead Pastic PDIP 4 C to 85 C LT1498IS8#PBF LT1498IS8#TRPBF 1498I 8-Lead Pastic SO 4 C to 85 C LT1498HS8#PBF LT1498HS8#TRPBF 1498H 8-Lead Pastic SO 4 C to 125 C LT1498MPS8#PBF LT1498MPS8#TRPBF 1498MP 8-Lead Pastic SO 55 C to 125 C LT1499CS#PBF LT1499CS#TRPBF LT1499CS 14-Lead Pastic SO C to 7 C LT1499IS#PBF LT1499IS#TRPBF LT1499IS 14-Lead Pastic SO 4 C to 85 C LT1499HS#PBF LT1499HS#TRPBF LT1499HS 14-Lead Pastic SO 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based fi nish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2

3 ELECTRICAL CHARACTERISTICS T A = 25 C, V S = 5V, V; V S = 3V, V; V CM = V OUT = haf suppy, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V + V CM = V ΔV OS Input Offset Votage Shift V CM = V to V Input Offset Votage Match (Channe-to-Channe) V CM = V +, V (Note 5) 2 75 I B Input Bias Current V CM = V + V CM = V 65 ΔI B Input Bias Current Shift V CM = V to V Input Bias Current Match (Channe-to-Channe) V CM = V + (Note 5) V CM = V (Note 5) I OS Input Offset Current V CM = V + 5 V CM = V 5 ΔI OS Input Offset Current Shift V CM = V to V + 13 Input Noise Votage.1Hz to Hz 4 nv P-P e n Input Noise Votage Density f = 1kHz 12 nv/ Hz i n Input Noise Current Density f = 1kHz.3 pa/ Hz C IN Input Capacitance 5 pf A VOL Large-Signa Votage Gain V S = 5V, V O = 75 to 4.8V, R L = k V S = 3V, V O = 75 to 2.8V, R L = k CMRR Common Mode Rejection Ratio V S = 5V, V CM = V to V + 81 V S = 3V, V CM = V to V + 76 CMRR Match (Channe-to-Channe) (Note 5) V S = 5V, V CM = V to V + 75 V S = 3V, V CM = V to V + 7 PSRR Power Suppy Rejection Ratio V S = 2.2V to 12V, V CM = V O =.5V 88 5 PSRR Match (Channe-to-Channe) (Note 5) V S = 2.2V to 12V, V CM = V O =.5V 82 3 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = 2.5mA V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = 2.5mA I SC Short-Circuit Current V S = 5V V S = 3V I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate (Note 8) V S = 5V, A V = 1, R L = Open, V O = 4V V S = 3V, A V = 1, R L = Open 6 5 ±12.5 ± ±24 ± ma ma V/μs V/μs 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range C < T A < 7 C. V S = 5V, V; V S = 3V, V; V CM = V OUT = haf suppy, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V + V CM = V +.1V V OS TC Input Offset Votage Drift (Note 3) V CM = V + ΔV OS Input Offset Votage Shift V CM = V +.1V to V Input Offset Votage Match (Channe-to-Channe) V CM = V +.1V, V + (Note 5) 2 9 I B Input Bias Current V CM = V + V CM = V +.1V ΔI B Input Bias Current Shift V CM = V +.1V to V Input Bias Current Match (Channe-to-Channe) V CM = V + (Note 5) V CM = V +.1V (Note 5) I OS Input Offset Current V CM = V + V CM = V +.1V ΔI OS Input Offset Current Shift V CM = V +.1V to V A VOL Large-Signa Votage Gain V S = 5V, V O = 75 to 4.8V, R L = k V S = 3V, V O = 75 to 2.8V, R L = k CMRR Common Mode Rejection Ratio V S = 5V, V CM = V +.1V to V + V S = 3V, V CM = V +.1V to V + CMRR Match (Channe-to-Channe) (Note 5) V S = 5V, V CM = V +.1V to V + V S = 3V, V CM = V +.1V to V + PSRR Power Suppy Rejection Ratio V S = 2.3V to 12V, V CM = V O =.5V 86 2 PSRR Match (Channe-to-Channe) (Note 5) V S = 2.3V to 12V, V CM = V O =.5V 8 2 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = 2.5mA V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = 2.5mA I SC Short-Circuit Current V S = 5V V S = 3V I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate (Note 8) V S = 5V, A V = 1, R L = Open, V O = 4V V S = 3V, A V = 1, R L = Open ±12 ± ±23 ± / C / C ma ma V/μs V/μs 4

5 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range 4 C < T A < 85 C. V S = 5V, V; V S = 3V, V; V CM = V OUT = haf suppy, uness otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V + V CM = V +.1V V OS TC Input Offset Votage Drift (Note 3) V CM = V + ΔV OS Input Offset Votage Shift V CM = V +.1V to V Input Offset Votage Match (Channe-to-Channe) V CM = V +.1V, V + (Note 5) 3 I B Input Bias Current V CM = V + V CM = V +.1V ΔI B Input Bias Current Shift V CM = V +.1V to V Input Bias Current Match (Channe-to-Channe) V CM = V + (Note 5) V CM = V +.1V (Note 5) I OS Input Offset Current V CM = V + V CM = V +.1V ΔI OS Input Offset Current Shift V CM = V +.1V to V A VOL Large-Signa Votage Gain V S = 5V, V O = 75 to 4.8V, R L = k V S = 3V, V O = 75 to 2.8V, R L = k CMRR Common Mode Rejection Ratio V S = 5V, V CM = V +.1V to V + V S = 3V, V CM = V +.1V to V + CMRR Match (Channe-to-Channe) (Note 5) V S = 5V, V CM = V +.1V to V + V S = 3V, V CM = V +.1V to V + PSRR Power Suppy Rejection Ratio V S = 2.5V to 12V, V CM = V O =.5V 86 PSRR Match (Channe-to-Channe) (Note 5) V S = 2.5V to 12V, V CM = V O =.5V 8 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = 2.5mA V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = 2.5mA I SC Short-Circuit Current V S = 5V V S = 3V I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate (Note 8) V S = 5V, A V = 1, R L = Open, V O = 4V V S = 3V, A V = 1, R L = Open ±7.5 ± ± ± / C / C ma ma V/μs V/μs 5

6 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range 4 C < T A < 125 C. V S = 5V, V; V S = 3V, V; V CM = V OUT = haf suppy, uness otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V +.5V V CM = V +.5V V OS TC Input Offset Votage Drift (Note 3) V CM = V +.5V ΔV OS Input Offset Votage Shift V CM = V +.5V to V +.5V Input Offset Votage Match (Channe-to-Channe) V CM = V +.5V, V +.5V (Note 5) 3 19 I B Input Bias Current V CM = V +.5V V CM = V +.5V ΔI B Input Bias Current Shift V CM = V +.5V to V +.5V 9 22 Input Bias Current Match (Channe-to-Channe) V CM = V +.5V (Note 5) V CM = V +.5V (Note 5) I OS Input Offset Current V CM = V +.5V V CM = V +.5V ΔI OS Input Offset Current Shift V CM = V +.5V to V +.5V 8 6 A VOL Large-Signa Votage Gain V S = 5V, V O =.5V to 4.5V, R L = k V S = 3V, V O =.5V to 2.5V, R L = k CMRR Common Mode Rejection Ratio V S = 5V, V CM = V +.5V to V +.5V V S = 3V, V CM = V +.5V to V +.5V CMRR Match (Channe-to-Channe) (Note 5) V S = 5V, V CM = V +.5V to V +.5V V S = 3V, V CM = V +.5V to V +.5V PSRR Power Suppy Rejection Ratio V S = 2.5V to 12V, V CM = V O =.5V 86 PSRR Match (Channe-to-Channe) (Note 5) V S = 2.5V to 12V, V CM = V O =.5V 8 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = 2.5mA V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = 2.5mA I SC Short-Circuit Current V S = 5V V S = 3V I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate (Note 8) V S = 5V, A V = 1, R L = Open, V O = 4V V S = 3V, A V = 1, R L = Open ±5 ± ± ± / C / C ma ma V/μs V/μs 6

7 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range 55 C < T A < 125 C. V S = 5V, V; V S = 3V, V; V CM = V OUT = haf suppy, uness otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V +.5V V CM = V +.5V V OS TC Input Offset Votage Drift (Note 3) V CM = V +.5V ΔV OS Input Offset Votage Shift V CM = V +.5V to V +.5V Input Offset Votage Match (Channe-to-Channe) V CM = V +.5V, V +.5V (Note 5) 3 19 I B Input Bias Current V CM = V +.5V V CM = V +.5V ΔI B Input Bias Current Shift V CM = V +.5V to V +.5V 9 22 Input Bias Current Match (Channe-to-Channe) V CM = V +.5V (Note 5) V CM = V +.5V (Note 5) I OS Input Offset Current V CM = V +.5V V CM = V +.5V ΔI OS Input Offset Current Shift V CM = V +.5V to V +.5V 8 6 A VOL Large-Signa Votage Gain V S = 5V, V O =.5V to 4.5V, R L = k V S = 3V, V O =.5V to 2.5V, R L = k CMRR Common Mode Rejection Ratio V S = 5V, V CM = V +.5V to V +.5V V S = 3V, V CM = V +.5V to V +.5V CMRR Match (Channe-to-Channe) (Note 5) V S = 5V, V CM = V +.5V to V +.5V V S = 3V, V CM = V +.5V to V +.5V PSRR Power Suppy Rejection Ratio V S = 2.5V to 12V, V CM = V O =.5V 86 PSRR Match (Channe-to-Channe) (Note 5) V S = 2.5V to 12V, V CM = V O =.5V 8 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = 2.5mA V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = 2.5mA I SC Short-Circuit Current V S = 5V V S = 3V I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate (Note 8) V S = 5V, A V = 1, R L = Open, V O = 4V V S = 3V, A V = 1, R L = Open ±5 ± ± ± / C / C ma ma V/μs V/μs 7

8 ELECTRICAL CHARACTERISTICS T A = 25 C. V S = ±V, V CM = V, V OUT = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V + 2 V CM = V 2 ΔV OS Input Offset Votage Shift V CM = V to V + 65 Input Offset Votage Match (Channe-to-Channe) V CM = V +, V (Note 5) I B Input Bias Current V CM = V + V CM = V 7 ΔI B Input Bias Current Shift V CM = V to V Input Bias Current Match (Channe-to-Channe) V CM = V + (Note 5) V CM = V (Note 5) I OS Input Offset Current V CM = V + 6 V CM = V 6 ΔI OS Input Offset Current Shift V CM = V to V Input Noise Votage.1Hz to Hz 4 nv P-P e n Input Noise Votage Density f = 1kHz 12 nv/ Hz i n Input Noise Current Density f = 1kHz.3 pa/ Hz A VOL Large-Signa Votage Gain V O = 14.5V to 14.5V, R L = k V O = V to V, R L = 2k Channe Separation V O = V to V, R L = 2k CMRR Common Mode Rejection Ratio V CM = V to V CMRR Match (Channe-to-Channe) (Note 5) V CM = V to V PSRR Power Suppy Rejection Ratio V S = ±5V to ±V 89 1 PSRR Match (Channe-to-Channe) (Note 5) V S = ±5V to ±V 83 5 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = ma V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = ma I SC Short-Circuit Current ± ±3 ma I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate A V = 1, R L = Open, V O = ±V Measure at V O = ±5V V/μs

9 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range C < T A < 7 C. V S = ±V, V CM = V, V OUT = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V + V CM = V +.1V V OS TC Input Offset Votage Drift (Note 3) V CM = V + ΔV OS Input Offset Votage Shift V CM = V +.1V to V Input Offset Votage Match (Channe-to-Channe) V CM = V +.1V, V + (Note 5) 35 I B Input Bias Current V CM = V + V CM = V +.1V ΔI B Input Bias Current Shift V CM = V +.1V to V Input Bias Current Match (Channe-to-Channe) V CM = V + (Note 5) V CM = V +.1V (Note 5) I OS Input Offset Current V CM = V + V CM = V +.1V ΔI OS Input Offset Current Shift V CM = V +.1V to V A VOL Large-Signa Votage Gain V O = 14.5V to 14.5V, R L = k V O = V to V, R L = 2k Channe Separation V O = V to V, R L = 2k CMRR Common Mode Rejection Ratio V CM = V +.1V to V CMRR Match (Channe-to-Channe) (Note 5) V CM = V +.1V to V PSRR Power Suppy Rejection Ratio V S = ±5V to ±V 88 3 PSRR Match (Channe-to-Channe) (Note 5) V S = ±5V to ±V 82 3 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = ma V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = ma I SC Short-Circuit Current ±12 ±28 ma I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate A V = 1, R L = Open, V O = ±V Measured at V O = ±5V V/μs / C / C 9

10 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range 4 C < T A < 85 C. V S = ±V, V CM = V, V OUT = V, uness otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V + V CM = V +.1V V OS TC Input Offset Votage Drift (Note 3) V CM = V + ΔV OS Input Offset Votage Shift V CM = V +.1V to V Input Offset Votage Match (Channe-to-Channe) V CM = V +.1V, V + (Note 5) I B Input Bias Current V CM = V + V CM = V +.1V ΔI B Input Bias Current Shift V CM = V +.1V to V Input Bias Current Match (Channe-to-Channe) V CM = V + (Note 5) V CM = V +.1V (Note 5) I OS Input Offset Current V CM = V + V CM = V +.1V ΔI OS Input Offset Current Shift V CM = V +.1V to V A VOL Large-Signa Votage Gain V O = 14.5V to 14.5V, R L = k V O = V to V, R L = 2k Channe Separation V O = V to V, R L = 2k 1 12 CMRR Common Mode Rejection Ratio V CM = V +.1V to V CMRR Match (Channe-to-Channe) (Note 5) V CM = V +.1V to V + 86 PSRR Power Suppy Rejection Ratio V S = ±5V to ±V 88 PSRR Match (Channe-to-Channe) (Note 5) V S = ±5V to ±V 82 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = ma V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = ma I SC Short-Circuit Current ± ±18 ma I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate A V = 1, R L = Open, V O = ±V Measure at V O = ±5V V/μs / C / C

11 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range 4 C < T A < 125 C. V S = ±V, V CM = V, V OUT = V, uness otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V +.5V V CM = V +.5V V OS TC Input Offset Votage Drift (Note 3) V CM = V +.5V ΔV OS Input Offset Votage Shift V CM = V +.5V to V +.5V 25 Input Offset Votage Match (Channe-to-Channe) V CM = V +.5V, V +.5V (Note 5) 4 22 I B Input Bias Current V CM = V +.5V V CM = V +.5V ΔI B Input Bias Current Shift V CM = V +.5V to V +.5V 24 Input Bias Current Match (Channe-to-Channe) V CM = V +.5V (Note 5) V CM = V +.5V (Note 5) I OS Input Offset Current V CM = V +.5V V CM = V +.5V ΔI OS Input Offset Current Shift V CM = V +.5V to V +.5V 8 6 A VOL Large-Signa Votage Gain V O = 14.5V to 14.5V, R L = k 4 4 Channe Separation V O = V to V, R L = 2k 1 12 CMRR Common Mode Rejection Ratio V CM = V +.5V to V +.5V 86 CMRR Match (Channe-to-Channe) (Note 5) V CM = V +.5V to V +.5V 8 PSRR Power Suppy Rejection Ratio V S = ±5V to ±V 88 PSRR Match (Channe-to-Channe) (Note 5) V S = ±5V to ±V 8 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = ma V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = ma I SC Short-Circuit Current ±7.5 ±12 ma I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate A V = 1, R L = Open, V O = ±V Measure at V O = ±5V V/μs / C / C 11

12 ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the temperature range 55 C < T A < 125 C. V S = ±V, V CM = V, V OUT = V, uness otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Votage V CM = V +.5V V CM = V +.5V V OS TC Input Offset Votage Drift (Note 3) V CM = V +.5V ΔV OS Input Offset Votage Shift V CM = V +.5V to V +.5V 25 Input Offset Votage Match (Channe-to-Channe) V CM = V +.5V, V +.5V (Note 5) 4 22 I B Input Bias Current V CM = V +.5V V CM = V +.5V ΔI B Input Bias Current Shift V CM = V +.5V to V +.5V 24 Input Bias Current Match (Channe-to-Channe) V CM = V +.5V (Note 5) V CM = V +.5V (Note 5) I OS Input Offset Current V CM = V +.5V V CM = V +.5V ΔI OS Input Offset Current Shift V CM = V +.5V to V +.5V 8 6 A VOL Large-Signa Votage Gain V O = 14.5V to 14.5V, R L = k 4 4 Channe Separation V O = V to V, R L = 2k 1 12 CMRR Common Mode Rejection Ratio V CM = V +.5V to V +.5V 86 CMRR Match (Channe-to-Channe) (Note 5) V CM = V +.5V to V +.5V 8 PSRR Power Suppy Rejection Ratio V S = ±5V to ±V 88 PSRR Match (Channe-to-Channe) (Note 5) V S = ±5V to ±V 8 V OL Output Votage Swing (Low) (Note 6) No Load I SINK =.5mA I SINK = ma V OH Output Votage Swing (High) (Note 6) No Load I SOURCE =.5mA I SOURCE = ma I SC Short-Circuit Current ±7.5 ±12 ma I S Suppy Current per Ampifi er ma GBW Gain-Bandwidth Product (Note 7) MHz SR Sew Rate A V = 1, R L = Open, V O = ±V Measure at V O = ±5V V/μs / C / C Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A heat sink may be required to keep the junction temperature beow the absoute maximum rating when the output is shorted indefinitey. Note 3: This parameter is not % tested. Note 4: The LT1498C/LT1499C are guaranteed to meet specifi ed performance from C to 7 C. The LT1498C/LT1499C are designed, characterized and expected to meet specifi ed performance from 4 C to 85 C but are not tested or QA samped at these temperatures. The LT1498I/LT1499I are guaranteed to meet specifi ed performance from 4 C to 85 C. The LT1498H/LT1499H are guaranteed to meet specifi ed performance from 4 C to 125 C. The LT1498MP is guaranteed to meet specified performance from 55 C to 125 C. Note 5: Matching parameters are the difference between ampifiers A and D and between B and C on the LT1499; between the two ampifi ers on the LT1498. Note 6: Output votage swings are measured between the output and power suppy rais. Note 7: V S = 3V, V S = ±V GBW imit guaranteed by correation to 5V tests. Note 8: V S = 3V, V S = 5V sew rate imit guaranteed by correation to ±V tests. 12

13 TYPICAL PERFORMANCE CHARACTERISTICS PERCENT OF UNITS (%) 25 2 V OS Distribution, V CM = V (PNP Stage) LT1498: N8, S8 PACKAGES LT1499: S14 PACKAGE V S = 5V, V V CM = V PERCENT OF UNITS (%) 25 2 V OS Distribution V CM = 5V (NPN Stage) LT1498: N8, S8 PACKAGES LT1499: S14 PACKAGE V S = 5V, V V CM = 5V PERCENT OF UNITS (%) 25 2 ΔV OS Shift for V CM = V to 5V LT1498: N8, S8 PACKAGES LT1499: S14 PACKAGE V S = 5V, V V CM = V TO 5V INPUT OFFSET VOLTAGE () INPUT OFFSET VOLTAGE () INPUT OFFSET VOLTAGE () G G G3 SUPPLY CURRENT PER AMPLIFIER (ma) Suppy Current vs Suppy Votage 2. T A = 125 C T A = 25 C 1.5 T A = 55 C 1..5 SUPPLY CURRENT PER AMPLIFIER (ma) Suppy Current vs Temperature 2. V S = V V S = 5V, V INPUT BIAS CURRENT () Input Bias Current vs Common Mode Votage V S = 5V, V T A = 125 C T A = 25 C T A = 55 C TOTAL SUPPLY VOLTAGE (V) TEMPERATURE ( C) COMMON MODE VOLTAGE (V) G G G6 4 3 Input Bias Current vs Temperature V S = V V CM = V Output Saturation Votage vs Load Current (Output High) Output Saturation Votage vs Load Current (Output Low) INPUT BIAS CURRENT () NPN ACTIVE PNP ACTIVE TEMPERATURE ( C) V S = 5V, V V CM = 5V V S = V V CM = V V S = 5V, V V CM = V SATURATION VOLTAGE () T A = 55 C T A = 125 C T A = 25 C LOAD CURRENT (ma) SATURATION VOLTAGE () T A = 25 C T A = 125 C T A = 55 C LOAD CURRENT (ma) G G G9 13

14 TYPICAL PERFORMANCE CHARACTERISTICS CHANGE IN OFFSET VOLTAGE () Minimum Suppy Votage T A = 25 C T A = 85 C T A = 7 C NONFUNCTIONAL T A = 55 C TOTAL SUPPLY VOLTAGE (V) G OUTPUT VOLTAGE (2nV/DIV).1Hz to Hz Output Votage Noise V S = 2.5V V CM = V TIME (1s/DIV) G11 NOISE VOLTAGE (nv/ Hz) Noise Votage Spectrum V S = 5V, V V CM = 2.5V PNP ACTIVE V CM = 4V NPN ACTIVE FREQUENCY (Hz) G12 CURRENT NOISE (pa/ Hz) Noise Current Spectrum Gain and Phase vs Frequency CMRR vs Frequency V S = 5V, V V CM = 4V 3 NPN ACTIVE 2 1 V CM = 2.5V PNP ACTIVE 1 FREQUENCY (Hz) G13 VOLTAGE GAIN () 7 R L = k 18 6 V S = 1.5V V S = V PHASE GAIN FREQUENCY (MHz) G14 PHASE SHIFT (DEG) COMMON MODE REJECTION RATIO () V S = 2.5V V S = V 2 1 FREQUENCY (khz) G POWER SUPPLY REJECTION RATIO () PSRR vs Frequency NEGATIVE SUPPLY V S = 2.5V POSITIVE SUPPLY 1 FREQUENCY (khz) G16 GAIN BANDWIDTH (MHz) Gain Bandwidth and Phase Margin vs Suppy Votage PHASE MARGIN GAIN BANDWIDTH TOTAL SUPPLY VOLTAGE (V) G PHASE MARGIN (DEG) CHANNEL SEPARATION () Channe Separation vs Frequency V S = V V OUT = 1V P-P R L = 2k.1 1 FREQUENCY (khz) G18 14

15 TYPICAL PERFORMANCE CHARACTERISTICS OVERSHOOT (%) Capacitive Load Handing V S = 5V, V A V = 1 R L = 1k SLEW RATE (V/μs) Sew Rate vs Suppy Votage V OUT = 8% OF V S A V = 1 RISING EDGE FALLING EDGE OUTPUT STEP (V) Output Step vs Setting Time to.1% V S = V NONINVERTING NONINVERTING INVERTING INVERTING CAPACITIVE LOAD (pf) TOTAL SUPPLY VOLTAGE (V) SETTLING TIME (μs) G G G21 INPUT VOLTAGE () Open-Loop Gain Open-Loop Gain Warm-Up Drift vs Time R L = k R L = 2k V S = V INPUT VOLTAGE () V S = 5V, V R L = 2k R L = k CHANGE IN OFFSET VOLTAGE () 2 3 S8 PACKAGE, V S = 2.5V N8 PACKAGE, V S = 2.5V LT1499CS, V S = 2.5V S8 PACKAGE, V S = V N8 PACKAGE, V S = V LT1499CS, V S = V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TIME AFTER POWER-UP (SEC) G G G24 THD + NOISE (%) Tota Harmonic Distortion + Noise vs Peak-to-Peak Votage f = 1kHz R L = k A V = 1 V S = 1.5V A V = 1 V S = 1.5V A V = 1 V S = 2.5V A V = 1 V S = 2.5V THD + NOISE (%) Tota Harmonic Distortion + Noise vs Frequency V S = 1.5V V IN = 2V P-P R L = k A V = 1 A V = INPUT VOLTAGE (V P-P ) G FREQUENCY (khz) G26

16 TYPICAL PERFORMANCE CHARACTERISTICS 5V Sma-Signa Response 5V Large-Signa Response 5/DIV 1V/DIV V S = 5V 2ns/DIV A V = 1 V IN = 2 P-P AT 5kHz R L = 1k G27 V S = 5V 2μs/DIV A V = 1 V IN = 4V P-P AT khz R L = 1k G28 ±V Sma-Signa Response ±V Large-Signa Response 5/DIV 5V/DIV V S = V 2ns/DIV A V = 1 V IN = 2 P-P AT 5kHz R L = 1k G29 V S = V 2μs/DIV A V = 1 V IN = 2V P-P AT khz R L = 1k G3 16

17 APPLICATIONS INFORMATION Rai-to-Rai Input and Output The are fuy functiona for an input and output signa range from the negative suppy to the positive suppy. Figure 1 shows a simpified schematic of the ampifi er. The input stage consists of two differentia ampifiers, a PNP stage (Q1/Q2) and an NPN stage (Q3/Q4) which are active over different ranges of input common mode votage. A compementary common emitter output stage (Q14/Q) is empoyed aowing the output to swing from rai-to-rai. The devices are fabricated on Linear Technoogy s proprietary compementary bipoar process to ensure very simiar DC and AC characteristics for the output devices (Q14/Q). The PNP differentia input pair is active for input common mode votages, V CM, between the negative suppy to approximatey 1.3V beow the positive suppy. As V CM moves further toward the positive suppy, the transistor (Q5) wi steer the tai current, I 1, to the current mirror (Q6/Q7) activating the NPN differentia pair, and the PNP differentia pair becomes inactive for the rest of the input common mode range up to the positive suppy. The output is configured with a pair of compementary common emitter stages that enabes the output to swing from rai to rai. Capacitors (C1 and C2) form oca feedback oops that ower the output impedance at high frequencies. Input Offset Votage The offset votage changes depending upon which input stage is active. The input offsets are random, but are trimmed to ess than 475. To maintain the precision characteristics of the ampifier, the change of V OS over the entire input common mode range (CMRR) is guaranteed to be ess than 425 on a singe 5V suppy. Input Bias Current The input bias current poarity aso depends on the input common mode votage, as described in the previous section. When the PNP differentia pair is active, the input bias currents f ow out of the input pins; they f ow in opposite direction when the NPN input stage is active. The offset error due to input bias current can be minimized by equaizing the noninverting and inverting input source impedances. This wi reduce the error since the input offset currents are much ess than the input bias currents. V + R3 R4 R5 Q +IN IN R6 R7 D5 D6 D1 D2 Q4 Q3 Q5 V BIAS Q1 I 1 Q2 Q11 Q12 Q13 V C C C2 OUT D3 D4 Q Q9 Q8 BUFFER AND OUTPUT BIAS C1 V Q7 Q6 R1 R2 Q F1 Figure 1. LT1498 Simpifi ed Schematic Diagram 17

18 APPLICATIONS INFORMATION Overdrive Protection To prevent the output from reversing poarity when the input votage exceeds the power suppies, two pair of crossing diodes D1 to D4 are empoyed. When the input votage exceeds either power suppy by approximatey 7, D1/D2 or D3/D4 wi turn on, forcing the output to the proper poarity. For the phase reversa protection to work propery, the input current must be ess than 5mA. If the ampifi er is to be severey overdriven, an externa resistor shoud be used to imit the overdrive current. Furthermore, the s input stages are protected by a pair of back-to-back diodes, D5/D6. When a differentia votage of more than.7v is appied to the inputs, these diodes wi turn on, preventing the Zener breakdown of the input transistors. The current in D5/D6 shoud be imited to ess than ma. Interna resistors R6 and R7 (7Ω tota) imit the input current for differentia input signas of 7V or ess. For arger input eves, a resistor in series with either or both inputs shoud be used to imit the current. Worst-case differentia input votage usuay occurs when the output is shorted to ground. In addition, the ampifi er is protected against ESD strikes up to 3kV on a pins. Capacitive Load The are designed for ease of use. The ampifier can drive a capacitive oad of more than nf without osciation at unity gain. When driving a heavy capacitive oad, the bandwidth is reduced to maintain stabiity. Figures 2a and 2b iustrate the stabiity of the device for sma-signa and arge-signa conditions with capacitive oads. Both the sma-signa and arge-signa transient response with a nf capacitive oad are we behaved. Feedback Components To minimize the oading effect of feedback, it is possibe to use the high vaue feedback resistors to set the gain. However, care must be taken to insure that the poe formed by the feedback resistors and the tota input capacitance at the inverting input does not degrade the stabiity of the ampifier. For instance, the in a noninverting gain of 2, set with two 3k resistors, wi probaby osciate with pf tota input capacitance (5pF input capacitance + 5pF board capacitance). The ampifi er has a 2.5MHz crossing frequency and a 6 phase margin at 6 of gain. The feedback resistors and the tota input capacitance create a poe at 1.6MHz that induces 67 of phase shift at 2.5MHz! The soution is simpe, either ower the vaue of the resistors or add a feedback capacitor of pf of more. C L = pf C L = pf C L = 5pF C L = 5pF C L = nf C L = nf V S = 5V A V = F2a V S = 5V A V = F2b Figure 2a. LT1498 Sma-Signa Response Figure 2b. LT1498 Large-Signa Response 18

19 TYPICAL APPLICATIONS 1A Votage Controed Current Source V +.5Ω 1k V IN 1k 1/2 LT pF Ω Si943DY V + VIN I OUT =.5Ω t r < 1μs I OUT R L TA3 1A Votage Controed Current Sink V + V + R L V IN 1k + 1/2 LT1498 5pF Ω I OUT Si94DY 1k I OUT = V IN.5Ω t r < 1μs.5Ω TA4 Input Bias Current Canceation R G R F SIGNAL AMP 1/2 LT1498 V OUT V IN + 1M 22pF 1/2 LT CANCELLATION AMP 1M TA5 INPUT BIAS CURRENT LESS THAN 5 FOR 5 V IN (V + 5) 19

20 PACKAGE DESCRIPTION N8 Package 8-Lead PDIP (Narrow.3 Inch) (Reference LTC DWG # 5-8-).4* (.16) MAX * ( ) ( ) ( ).13.5 ( ).8. ( ) (1.651) TYP. (2.54) BSC NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED. INCH (.254mm).12 (3.48) MIN.18.3 ( ).2 (.58) MIN N8 2 2

21 PACKAGE DESCRIPTION S8 Package 8-Lead Pastic Sma Outine (Narrow. Inch) (Reference LTC DWG # ).5 BSC ( ) NOTE MIN ( )..7 ( ) NOTE TYP RECOMMENDED SOLDER PAD LAYOUT ( ) ( ) 8 TYP ( ).4. (.1.254).16.5 ( ) NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) ( ) TYP 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.6" (.mm).5 (1.27) BSC SO

22 PACKAGE DESCRIPTION S Package 14-Lead Pastic Sma Outine (Narrow. Inch) (Reference LTC DWG # ).5 BSC ( ) NOTE 3 N MIN N/ ( ) N N/2..7 ( ) NOTE TYP RECOMMENDED SOLDER PAD LAYOUT ( ) ( ) 8 TYP ( ).4. (.1.254).16.5 ( ) NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) ( ) TYP 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.6" (.mm).5 (1.27) BSC S

23 REVISION HISTORY (Revision history begins at Rev E) REV DATE DESCRIPTION PAGE NUMBER E /9 Edit in Absoute Maximum Ratings 2 F 1/ Added LT1498H/LT1499H (H-Grade) Parts. Ref ected throughout the data sheet G 3/ Updated Part Markings in Order Information Section Updated Conditions for A VOL in Eectrica Characteristics Section 2 6, 7 Information furnished by Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 23

24 TYPICAL APPLICATION Bidirectiona Current Sensor A bidirectiona current sensor for battery-powered systems is shown in Figure 3. Two outputs are provided: one proportiona to charge current, the other proportiona to discharge current. The circuit takes advantage of the LT1498 s rai-to-rai input range and its output phase reversa protection. During the charge cyce, the op amp A1 forces a votage equa to (I L )(R SENSE ) across R A. This votage is then ampified at the Charge Out by the ratio of R B over R A. In this mode, the output of A2 remains high, keeping Q2 off and the Discharge Out ow, even though the (+) input of A2 exceeds the positive power suppy. During the discharge cyce, A2 and Q2 are active and the operation is simiar to the charge cyce. I L CHARGE R SENSE.1Ω V BATTERY DISCHARGE V BATTERY A2 1/2 LT R A R A R A R A + A1 1/2 LT1498 Q2 MTP23P6 DISCHARGE OUT R B Q1 MTP23P6 CHARGE OUT Figure 3. Bidirectiona Current Sensor R B V O = I L R R SENSE A FOR R A = 1k, R B = k V O = 1V/A I L F3 R B ( ) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC 12 Rai-to-Rai Input and Output, Zero-Drift Op Amp High DC Accuracy, V OS(MAX), nv/ C Drift, 1MHz GBW, 1V/μs Sew Rate, Max Suppy Current 2.2mA LT1211/LT1212 Dua/Quad 14MHz, 7V/μs, Singe Suppy Precision Op Amps Input Common Mode Incudes Ground, 275 V OS(MAX), 6/ C Max Drift, Max Suppy Current 1.8mA per Op Amp LT1213/LT1214 Dua/Quad 28MHz, 12V/μs, Singe Suppy Precision Op Amps Input Common Mode Incudes Ground, 275 V OS(MAX), 6/ C Max Drift, Max Suppy Current 3.5mA per Op Amp LT12/LT1216 Dua/Quad 23MHz, 5V/μs, Singe Suppy Precision Op Amps Input Common Mode Incudes Ground, 45 V OS(MAX), Max Suppy Current 6.6mA per Op Amp LT1366/LT1367 Dua/Quad Precision, Rai-to-Rai Input and Output Op Amps 475 V OS(MAX), 4kHz GBW,.13V/μs Sew Rate, Max Suppy Current 52μA per Op Amp LT149/LT1491 Dua/Quad Micropower, Rai-to-Rai Input and Output Op Amps Max Suppy Current 5μA per Op Amp, 2kHz GBW,.7V/μs Sew Rate, Operates with Inputs 44V Above V Independent of V + LT1884/LT1885 Dua/Quad, Rai-to-Rai Output Picoamp Input Precision Op Amps I CC = 65μA, V OS < 5, I B < 4pA 24 Linear Technoogy Corporation LT 4 REV G PRINTED IN USA 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 29