LT V, 200mA, Ultralow Noise, Ultrahigh PSRR RF Linear Regulator APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Utraow RMS Noise:.µV RMS (Hz to khz) n Utraow Spot Noise: nv/ Hz at khz n Utrahigh PSRR: 79dB at MHz n Output Current: ma n Wide Input Votage Range:.V to V n Singe Capacitor Improves Noise and PSRR n µa Pin Current: ±% Initia Accuracy n Singe Resistor Programs Output Votage n High Bandwidth: MHz n Programmabe Current Limit n Low Dropout Votage: 3mV n Output Votage Range: V to V n Programmabe Power Good n Fast Start-Up Capabiity n Precision Enabe/UVLO n Paraeabe for Lower Noise and Higher Current n Interna Current Limit with Fodback n Minimum Output Capacitor: Ceramic n Reverse Battery and Reverse Current Protection n -Lead MSOP and 3mm 3mm DFN Packages APPLICATIONS n RF Power Suppies: PLLs, VCOs, Mixers, LNAs n Very Low Noise Instrumentation n High Speed/High Precision Data Converters n Medica Appications: Imaging, Diagnostics n Precision Power Suppies n Post-Reguator for Switching Suppies DESCRIPTION LT3 V, ma, Utraow Noise, Utrahigh PSRR RF Linear Reguator The LT 3 is a high performance ow dropout inear reguator featuring LTC s utraow noise and utrahigh PSRR architecture for powering noise sensitive RF appications. Designed as a precision current reference foowed by a high performance votage buffer, the LT3 can be easiy paraeed to further reduce noise, increase output current and spread heat on the PCB. The device suppies ma at a typica 3mV dropout votage. Operating quiescent current is nominay ma and drops to <<µa in shutdown. The LT3 s wide output votage range (V to V) whie maintaining unitygain operation provides virtuay constant output noise, PSRR, bandwidth and oad reguation, regardess of the programmed output votage. Additionay, the reguator features programmabe current imit, fast start-up capabiity and programmabe power good to indicate output votage reguation. The LT3 is stabe with a minimum ceramic output capacitor. Buit-in protection incudes reverse battery protection, reverse current protection, interna current imit with fodback and therma imit with hysteresis. The LT3 is avaiabe in thermay enhanced -Lead MSOP and 3mm 3mm DFN packages. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. Patents Pending. A other trademarks are the property of their respective owners. TYPICAL APPLICATION V V ±% k µa LT3 S V 3.3V I (MAX) ma PSRR (db) 9 7 Power Suppy Rippe Rejection 33.k 99Ω k k 3 TAa For more information V = V R = 33.kΩ C = 3 C = I L = ma k k k M M FREQUENCY (Hz) 3 TAb 3f

2 LT3 ABSOLUTE MAXIMUM RATGS (Note ) Pin Votage...±V Pin Votage...±V -to- Differentia...±V Pin Votage (Note )...3V, V Pin Votage (Note )...3V, V Pin Votage (Note )...3V, V Pin Votage (Note )...3V, V Pin Current (Note 7)... ±ma S Pin Votage (Note )...3V, V S Pin Current (Note 7)... ±ma Pin Votage (Note )...3V, V -to-s Differentia (Note )... ±.V -to- Differentia...±V -to-s Differentia...±V Output Short-Circuit Duration... Indefinite Operating Junction Temperature Range (Note 9) E-, I-Grade... C to C H-Grade... C to C MP-Grade... C to C Storage Temperature Range... C to C Lead Temperature (Sodering, Sec) MSE Package...3 C P CONFIGURATION TOP VIEW 3 DD PACKAGE -LEAD (3mm 3mm) PLASTIC DFN T JMAX = C, θ JA = 3 C/W, θ JC =. C/W EXPOSED PAD (P ) IS, MUST BE SOLDERED TO PCB 9 7 S 3 TOP VIEW 9 7 S MSE PACKAGE -LEAD PLASTIC MSOP T JMAX = C, θ JA = 33 C/W, θ JC = C/W EXPOSED PAD (P ) IS, MUST BE SOLDERED TO PCB ORDER FORMATION LEAD FREE FISH TAPE AND REEL PART MARKG* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3EDD#PBF LT3EDD#TRPBF LGSJ -Lead (3mm 3mm) Pastic DFN C to C LT3IDD#PBF LT3IDD#TRPBF LGSJ -Lead (3mm 3mm) Pastic DFN C to C LT3HDD#PBF LT3HDD#TRPBF LGSJ -Lead (3mm 3mm) Pastic DFN C to C LT3MPDD#PBF LT3MPDD#TRPBF LGSJ -Lead (3mm 3mm) Pastic DFN C to C LT3EMSE#PBF LT3EMSE#TRPBF LTGSH -Lead Pastic MSOP C to C LT3IMSE#PBF LT3IMSE#TRPBF LTGSH -Lead Pastic MSOP C to C LT3HMSE#PBF LT3HMSE#TRPBF LTGSH -Lead Pastic MSOP C to C LT3MPMSE#PBF LT3MPMSE#TRPBF LTGSH -Lead Pastic MSOP C to C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on nonstandard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: For more information 3f

3 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = C. LT3 PARAMETER CONDITIONS M TYP MAX UNITS Minimum Pin Votage (Note ) I LOAD = ma, V UVLO Rising V UVLO Hysteresis.7 7 V mv Pin Current (I ) V = V, I LOAD = ma, V =.3V 99 µa V < V < V, V < V < V, ma < I LOAD < ma (Note 3) 9 µa Fast Start-Up Set Pin Current V = 9mV, V =.V, V =.3V ma Output Offset Votage V OS (V V ) (Note ) V = V, I LOAD = ma, V =.3V V < V < V, V < V < V, ma < I LOAD < ma (Note 3) Line Reguation: I V = V to V, I LOAD = ma, V =.3V Line Reguation: V OS V = V to V, I LOAD = ma, V =.3V (Note ) Load Reguation: I I LOAD = ma to ma, V = V, V =.3V Load Reguation: V OS I LOAD = ma to ma, V = V, V =.3V (Note ).. ± ±3 3.. Change in I with V V =.3V to V, V = V, I LOAD = ma 3 Change in V OS with V V =.3V to V, V = V, I LOAD = ma (Note ).3. Change in I with V V = V to.3v, V = V, I LOAD = ma Change in V OS with V V = V to.3v, V = V, I LOAD = ma (Note ). Dropout Votage I LOAD = ma, ma 7 3 I LOAD = ma (Note ) 7 mv I LOAD = ma (Note ) 3 mv Pin Current V = V (NOMAL) (Note ) Output Noise Spectra Density (Notes, ) Output RMS Noise (Notes, ) Reference Current RMS Output Noise (Notes, ) Rippe Rejection.3V V V V V = V (Avg) (Notes, ) Rippe Rejection V V <.3V V V = V (Avg) (Notes, ) I LOAD = µa I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma I LOAD = ma, Frequency = Hz, C =, C =.7µF, V = 3.3V I LOAD = ma, Frequency = Hz, C =, C =,.3V V V I LOAD = ma, Frequency = khz, C =, C =.7µF,.3V V V I LOAD = ma, Frequency = khz, C =, C =.7µF, V V <.3V I LOAD = ma, BW = Hz to khz, C =, C =.7µF, V = 3.3V I LOAD = ma, BW = Hz to khz, C =, C =,.3V V V I LOAD = ma, BW = Hz to khz, C =, C =, V V <.3V mv mv na/v µv/v na mv na mv na mv mv mv ma ma ma ma ma nv/ Hz nv/ Hz nv/ Hz nv/ Hz µv RMS µv RMS µv RMS BW = Hz to khz na RMS V RIPPLE = mv P-P, f RIPPLE = Hz, I LOAD = ma, C =, C = V RIPPLE = mv P-P, f RIPPLE = khz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = khz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = MHz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = MHz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = Hz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = khz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = khz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = MHz, I LOAD = ma, C =, C =.7µF V RIPPLE = mv P-P, f RIPPLE = MHz, I LOAD = ma, C =, C =.7µF Pin Threshod Trip Point Rising (Turn-On), V = V...3 V Pin Hysteresis Trip Point Hysteresis, V = V 7 mv Pin Current V = V, V = V V =.V, V = V V = V, V = V. ± µa µa µa db db db db db db db db db db For more information 3f 3

4 LT3 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = C. Quiescent Current in Shutdown (V = V) Interna Current Limit (Note ) Programmabe Current Limit V = V V = V, V = V V = V, V = V V = V, V = V Programming Scae Factor: V< V < V (Note ) V = V, V = V, R = Ω V = V, V = V, R =.kω µa µa ma ma ma ma kω ma ma Trip Point Trip Point Rising mv Hysteresis Trip Point Hysteresis 7 mv Pin Current V = V, V = 3mV na Output Low Votage I = µa 3 mv Leakage Current V = V µa Reverse Input Current V = V, V = V, V = V, V = V µa Reverse Output Current V =, V = V, = Open µa Minimum Load Required V < V µa (Note 3) Therma Shutdown T J Rising Hysteresis C C Start-Up Time V (NOM) = V, I LOAD = ma, C =.7µF, V = V, V = V V (NOM) = V, I LOAD = ma, C =, V = V, V = V V (NOM) = V, I LOAD = ma, C =, V = V, R = kω, R = kω Therma Reguation ms Puse. %/W ms ms ms Note : Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note : The pin threshod must be met to ensure device operation. Note 3: Maximum junction temperature imits operating conditions. The reguated output votage specification does not appy for a possibe combinations of input votage and output current, especiay due to the interna current imit fodback which starts to decrease current imit at V V > V. If operating at maximum output current, imit the input votage range. If operating at the maximum input votage, imit the output current range. Note : S ties directy to. Note : Dropout votage is the minimum input-to-output differentia votage needed to maintain reguation at a specified output current. The dropout votage is measured when output is % out of reguation. This definition resuts in a higher dropout votage compared to hard dropout which is measured when V = V (NOMAL). For ower output votages, beow.v, dropout votage is imited by the minimum input votage specification. Linear Technoogy is unabe to guarantee maximum dropout votage specifications at ma and ma due to production test imitations with Kevin-sensing the package pins. Pease consut the Typica Performance Characteristics for curves of dropout votage as a function of output oad current and temperature measured in a typica appication circuit. Note : pin current is tested with V = V (NOMAL) and a current source oad. Therefore, the device is tested whie operating in dropout. This is the worst-case pin current. pin current decreases at higher input votages. Note that pin current does not incude pin or pin current. Note 7: and S pins are camped using diodes and two Ω series resistors. For ess than ms transients, this camp circuitry can carry more than the rated current. Note : Adding a capacitor across the pin resistor decreases output votage noise. Adding this capacitor bypasses the pin resistor s therma noise as we as the reference current s noise. The output noise then equas the error ampifier noise. Use of a pin bypass capacitor aso increases start-up time. Note 9: The LT3 is tested and specified under pused oad conditions such that T J T A. The LT3E is % tested at C and performance is guaranteed from C to C. Specifications over the C to C operating temperature range are assured by design, characterization, and correation with statistica process contros. The LT3I is guaranteed over the fu C to C operating temperature range. The LT3MP For more information 3f

5 ELECTRICAL CHARACTERISTICS is % tested and guaranteed over the fu C to C operating temperature range. The LT3H is % tested at the C operating junction temperature. High junction temperatures degrade operating ifetimes. Operating ifetime is derated at junction temperatures greater than C. Note : Parasitic diode exists internay between the,,,, S, and pins and the pin. Do not drive these pins more than.3v beow the pin during a faut condition. These pins must remain at a votage more positive than during norma operation. LT3 Note : The current imit programming scae factor is specified whie the interna backup current imit is not active. Note that the interna current imit has fodback protection for V V differentias greater than V. Note : The interna back-up current imit circuitry incorporates fodback protection that decreases current imit for V V > V. Some eve of output current is provided at a V V differentia votages. Consut the Typica Performance Characteristics graph for current imit vs V V. Note 3: For output votages ess than V, the LT3 requires a µa minimum oad current for stabiity. Note : Maximum -to-s differentia is guaranteed by design. TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. P CURRENT (µa) Pin Current Pin Current Offset Votage (V V ) V = V I L = ma V =.3V G N = I DISTRIBUTION (µa) 3 G OFF VOLTAGE (mv) V = V I L = ma V =.3V G3 Offset Votage Pin Current Offset Votage (V V ) N = 3 V OS DISTRIBUTION (mv) 3 G P CURRENT (µa) I L = ma V =.3V C C C C 99. PUT VOLTAGE (V) 3 G OFF VOLTAGE (mv) I L = ma V =.3V C C C C PUT VOLTAGE (V) 3 G For more information 3f

6 LT3 TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. P CURRENT (µa) Pin Current Offset Votage (V V ) Load Reguation I L = ma V = V C C C C PUT VOLTAGE (V) 3 G7 OFF VOLTAGE (mv) I L = ma V = V C C C C PUT VOLTAGE (V) 3 G I LOAD REGULATION (na) V =.V I L = ma TO ma V =.3V I V OS G V OS LOAD REGULATION (mv) QUIESCENT CURRENT (ma) Quiescent Current Quiescent Current in Shutdown Quiescent Current V = V V = V I L = µa R = 3kΩ G QUIESCENT CURRENT (µa) V = V V = V V = V G QUIESCENT CURRENT (ma)..... I L = µa R = 33.kΩ PUT VOLTAGE (V) 3 G QUIESCENT CURRENT (ma) Quiescent Current Typica Dropout Votage Dropout Votage V = V V = V I L = µa C C C C PUT VOLTAGE (V) 3 G3 DROP VOLTAGE (mv) 3 3 R = 33.kΩ C C C C 7 7 PUT CURRENT (ma) 3 G DROP VOLTAGE (mv) 3 3 R = 33.kΩ I L = ma I L = ma I L = ma I L = ma G For more information 3f

7 TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. LT3 P CURRENT (ma) Pin Current Pin Current Pin Current V = V R = 33.kΩ I L = ma I L = ma I L = ma I L = ma G P CURRENT (ma) 7 3 V =.3V R = 33.kΩ 7 7 PUT CURRENT (ma) 3 G7 P CURRENT (ma) 7 3 R L = 33Ω R L = Ω R L = 33Ω R L =.Ω R L = 3.3kΩ R = 33.kΩ V = 3.3V PUT VOLTAGE (V) 3 G PUT UVLO THRESHOLD (V) Minimum Input Votage Turn-On Threshod Pin Hysteresis. RISG UVLO.7 FALLG UVLO TURN-ON THRESHOLD (V) V. = V V. = V. P HYSTERESIS (mv) V = V 7 V = V G G G P CURRENT (µa) Enabe Pin Input Current Enabe Pin Current Enabe Pin Current V = V C C C C ENABLE P VOLTAGE (V) 3 G P CURRENT (µa) V = V V = V ENABLE P VOLTAGE (V) 3 G3 P CURRENT (µa) 3 V = V 7 C C 9 C C ENABLE P VOLTAGE (V) 3 G For more information 3f 7

8 LT3 TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. PUT CURRENT (ma).3.. Input Pin Current Interna Current Limit Interna Current Limit V = V C C C C ENABLE P VOLTAGE (V) 3 G CURRENT LIMIT (ma) 3 3 R = Ω V = V V = 7.V V =.V G CURRENT LIMIT (ma) 3 V = V R = Ω V = V G7 CURRENT LIMIT (ma) 3 3 Interna Current Limit Programmabe Current Limit Programmabe Current Limit R = Ω C C C C PUT-TO-PUT DIFFERENTIAL (V) 3 G CURRENT LIMIT (ma) 3 3 R = Ω V = V V = 7.V V =.V G9 CURRENT LIMIT (ma) R =.9kΩ V = V V = 7.V V =.V G3 P CURRENT (µa) 3 3 Pin Current Rising Threshod Hysteresis V = V R = 33.kΩ V =.V V = V V = V PUT CURRENT (ma) 3 G3 RISG THRESHOLD (mv) V = V G3 HYSTERESIS (mv) 7 3 V = V G33 For more information 3f

9 TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. LT3 Output Low Votage V = V V = 9mV I = µa 9 Pin Leakage Current V = V V = 3mV.. I During Start-Up with Fast Start-Up Enabed V =.V V = 9mV V =.3V 3 7 V (mv) 3 I (na) I (ma) G G G3 I (ma) I During Start-Up with Fast Start-Up Enabed V = 9mV V =.3V PUT SK CURRENT (ma) Output Overshoot Recovery Current Sink V = V R = 33.kΩ C 3 C C C PUT SK CURRENT (ma) 7 3 Output Overshoot Recovery Current Sink V = V R = 33.kΩ V V > mv V -TO-V DIFFERENTIAL (V) 3 G37 V V (mv) 3 G G39 CURRENT (ma) Reverse Current Power Suppy Rippe Rejection Power Suppy Rippe Rejection V = V R = 33.kΩ PUT CURRENT PUT CURRENT PUT VOLTAGE (V) 3 G PSRR (db) 9 7 C = C =.7µF V = V R = 33.kΩ 3 C = I L = ma k k k M M FREQUENCY (Hz) 3 G PSRR (db) 9 7 C = µf C = V = V R = 33.kΩ 3 C =.7µF I L = ma k k k M M FREQUENCY (Hz) 3 G For more information 3f 9

10 LT3 TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. PSRR (db) 9 7 Power Suppy Rippe Rejection V = V R = 33.kΩ I L = ma I L = ma 3 C = C =.7µF I L = ma I L = ma k k k M M FREQUENCY (Hz) 3 G3 PSRR (db) 9 7 Power Suppy Rippe Rejection as a Function of Error Ampifier Input Pair V = V V I L = ma V.3V 3 C = C =.7µF.V < V <.3V V.V k k k M M FREQUENCY (Hz) 3 G PSRR (db) Power Suppy Rippe Rejection 9 7 I L = ma R = 33.kΩ C = C =.7µF 3 khz khz MHz MHz 3 PUT-TO-PUT DIFFERENTIAL (V) 3 G RMS PUT NOISE (µv RMS ) Integrated RMS Output Noise (Hz to khz) V = V R = 33.kΩ C = C = RMS PUT NOISE (µv RMS ) Integrated RMS Output Noise (Hz to khz) V = V R = 33.kΩ C = I L = ma RMS PUT NOISE (µv RMS ) Integrated RMS Output Noise (Hz to khz) V = V V C = C = I LOAD = ma LOAD CURRENT (ma) 3 G.. P CAPACITANCE (µf) 3 G PUT VOLTAGE (V) 3 G7 PUT NOISE (nv/ Hz) Noise Spectra Density C =.7µF C =.7µF C = µf C = C = µf V = V R = 33.kΩ C = I L = ma. k k k M M FREQUENCY (Hz) 3 G PUT NOISE (nv/ Hz) Noise Spectra Density C = C = µf V = V R = 33.kΩ C = I L = ma. k k k M M FREQUENCY (Hz) 3 G9 For more information PUT NOISE (nv/ Hz) Noise Spectra Density I L = ma I L = ma I L = ma I L = ma V = V R = 33.kΩ C = C =. k k k M M FREQUENCY (Hz) 3 G 3f

11 TYPICAL PERFORMANCE CHARACTERISTICS T J = C, uness otherwise noted. LT3 PUT NOISE (nv/ Hz) Noise Spectra Density as a Function of Error Ampifier Input Pair V.3V.V < V <.3V V.V V = V V I L = ma C = C =. k k k M M FREQUENCY (Hz) mv/div mv/div Line Transient Response PUT VOLTAGE PUT VOLTAGE 3 G µv/div Output Noise: Hz to khz V = V R = 33.kΩ C = C = I L = ma ms/div Start-Up Time with and without Fast Start-Up Circuitry for Large C PUT WITH FAST START-UP PUT WITH FAST START-UP ( AT 9%) PULSE 3 G mv/div mv/div ma/div mv/div V/DIV Load Transient Response LOAD STEP PUT VOLTAGE µs/div V = V R = 33.kΩ C = C =.7µF LOAD STEP = ma TO ma Input Suppy Ramp-Up and Ramp-Down PUT VOLTAGE PUT VOLTAGE 3 G3 V = V TO.V R = 33.kΩ C = C =.7µF I L = ma µs/div 3 G V = V R = 33.kΩ C = C = R L =.Ω ms/div 3 G V = V TO V R = 33.kΩ C = C =.7µF R L =.Ω ms/div 3 G For more information 3f

12 LT3 P FUNCTIONS (Pins, ): Input. These pins suppy power to the reguator. The LT3 requires a bypass capacitor at the pin. In genera, a battery s output impedance rises with frequency, so incude a bypass capacitor in battery-powered appications. Whie a input bypass capacitor generay suffices, appications with arge oad transients may require higher input capacitance to prevent input suppy droop. The LT3 withstands reverse votages on with respect to, S and. In the case of a reversed input, which occurs if a battery is pugged-in backwards, the LT3 acts as if a diode is in series with its input. Hence, no reverse current fows into the LT3 and no negative votage appears at the oad. The device protects itsef and the oad. (Pin 3): Enabe/UVLO. Puing the LT3 s pin ow paces the part in shutdown. Quiescent current in shutdown drops to ess than µa and the output votage turns off. Aternativey, the pin can set an input suppy undervotage ockout (UVLO) threshod using a resistor divider between, and. The LT3 typicay turns on when the votage exceeds.v on its rising edge, with a 7mV hysteresis on its faing edge. The pin can be driven above the input votage and maintain proper functionaity. If unused, tie to. Do not foat the pin. (Pin ): Power Good. is an open-coector fag that indicates output votage reguation. pus ow if is beow 3mV. If the power good functionaity is not needed, foat the pin. A parasitic substrate diode exists between and pins of the LT3; do not drive more than.3v beow during norma operation or during a faut condition. (Pin ): Current Limit Programming Pin. Connecting a resistor between and programs the current imit. For best accuracy, Kevin connect this resistor directy to the LT3 s pin. The programming scae factor is nominay ma kω. The pin sources current proportiona (:) to output current; therefore, it aso serves as a current monitoring pin with a V to 3mV range. If the programmabe current imit functionaity is not needed, tie to. A parasitic substrate diode exists between and pins of the LT3; do not drive more than.3v beow during norma operation or during a faut condition. (Pin ): Power Good Feedback. The pin pus high if increases beyond 3mV on its rising edge, with 7mV hysteresis on its faing edge. Connecting an externa resistor divider between, and sets the programmabe power good threshod with the foowing transfer function:.3v ( R /R ). As discussed in the Appications Information section, aso activates the fast start-up circuitry. If power good and fast start-up functionaities are not needed, tie to. If reverse input protection is required, tie the anode of a N diode to V and the cathode to. A parasitic substrate diode exists between and pins of the LT3; do not drive more than.3v beow during norma operation or during a faut condition. (Pin 7):. This pin is the inverting input of the error ampifier and the reguation set-point for the LT3. sources a precision µa current that fows through an externa resistor connected between and. The LT3 s output votage is determined by V = I R. Output votage range is from zero to V. Adding a capacitor from to improves noise, PSRR and transient response at the expense of increased start-up time. For optimum oad reguation, Kevin connect the ground side of the pin resistor directy to the oad. A parasitic substrate diode exists between and pins of the LT3; do not drive more than.3v beow during norma operation or during a faut condition. (Pin, Exposed Pad Pin ): Ground. The exposed backside is an eectrica connection to. To ensure proper eectrica and therma performance, soder the exposed backside to the PCB ground and tie it directy to the pin. For more information 3f

13 V V P FUNCTIONS S (Pin 9): Output Sense. This pin is the noninverting input to the error ampifier. For optima transient performance and oad reguation, Kevin connect S directy to the output capacitor and the oad. Aso, tie the connections of the output capacitor and the pin capacitor directy together. Moreover, pace the input and output capacitors (and their connections) very cose together. A parasitic substrate diode exists between S and pins of the LT3; do not drive S more than.3v beow during norma operation or during a faut condition. LT3 (Pin ): Output. This pin suppies power to the oad. For stabiity, use a minimum output capacitor with an ESR beow mω and an ESL beow nh. Large oad transients require arger output capacitance to imit peak votage transients. Refer to the Appications Information section for more information on output capacitance. A parasitic substrate diode exists between and pins of the LT3; do not drive more than.3v beow during norma operation or during a faut condition. BLOCK DIAGRAM 3, C V.V 3mV ENABLE COMPARATOR BIAS PROGRAMMABLE POWER GOOD ma FAST START-UP DISABLE LOGIC CURRENT REFERENCE FAST START-UP PUT UVLO CURRENT LIMIT THERMAL SHDN DROP µa THERMAL SHDN PUT UVLO ERROR AMPLIFIER V DRIVER PUT OVERSHOOT RECOVERY.V TERNAL CURRENT LIMIT V PROGRAMMABLE CURRENT LIMIT V 3mV QC 7Ω QP QPWR C R L V 7 -TO-S PROTECTION CLAMP 9 S 3mV R R R C R R 3 BD For more information 3f 3

14 LT3 APPLICATIONS FORMATION The LT3 is a high performance ow dropout inear reguator featuring LTC s utraow noise (nv/ Hz at khz) and utrahigh PSRR (79dB at MHz) architecture for powering noise sensitive appications. Designed as a precision current source foowed by a high performance rai-to-rai votage buffer, the LT3 can be easiy paraeed to further reduce noise, increase output current and spread heat on the PCB. The device additionay features programmabe current imit, fast start-up capabiity and programmabe power good. The LT3 is easy to use and incorporates a of the protection features expected in high performance reguators. Incuded are short-circuit protection, safe operating area protection, reverse battery protection, reverse current protection, and therma shutdown with hysteresis. NPN-based input pair is active for output votages greater than.3v, with a smooth transition between the two input pairs from.v to.3v output. Whie the NPN-based input pair is designed to offer the best overa performance, refer to the Eectrica Characteristics Tabe for detais on offset votage, pin current, output noise and PSRR variation with the error amp input pair. Tabe ists many common output votages and their corresponding % R resistors. Tabe. % Resistor for Common Output Votages V (V) R (kω) Output Votage The LT3 incorporates a precision µa current source fowing out of the pin, which aso ties to the error ampifier s inverting input. Figure iustrates that connecting a resistor from to ground generates a reference votage for the error ampifier. This reference votage is simpy the product of the pin current and the pin resistor. The error ampifier s unity-gain configuration produces a ow impedance version of this votage on its noninverting input, i.e. the S pin, which is externay tied to the pin. The LT3 s rai-to-rai error ampifier and current reference aows for a wide output votage range from V (using a Ω resistor) to V minus dropout up to V. A PNP-based input pair is active for V to.v output and an V V ±%.7µF µa 33.k LT3 S 3 F Figure. Basic Adjustabe Reguator V, 3.3V I (MAX), ma For more information The benefit of using a current reference compared with a votage reference as used in conventiona reguators is that the reguator aways operates in unity gain configuration, regardess of the programmed output votage. This aows the LT3 to have oop gain, frequency response and bandwidth independent of the output votage. As a resut, noise, PSRR and transient performance do not change with output votage. Moreover, since none of the error amp gain is needed to ampify the pin votage to a higher output votage, output oad reguation is more tighty specified in the hundreds of microvots range and not as a fixed percentage of the output votage. Since the zero TC current source is highy accurate, the pin resistor can become the imiting factor in achieving high accuracy. Hence, it shoud be a precision resistor. Additionay, any eakage paths to or from the pin create errors in the output votage. If necessary, use high quaity insuation (e.g., Tefon, Ke-F); moreover, ceaning of a insuating surfaces to remove fuxes and other residues may be required. High humidity environments may require a surface coating at the pin to provide a moisture barrier. Minimize board eakage by encircing the pin with a guard ring operated at a potentia cose to itsef ideay tied to the pin. Guarding both sides of the circuit board is recommended. Buk eakage reduction depends on the 3f

15 LT3 APPLICATIONS FORMATION guard ring width. Leakages as sma as na into or out of the pin creates a.% error in the reference votage. Leakages of this magnitude, couped with other sources of eakage, can cause significant errors in the output votage, especiay over wide operating temperature range. Figure iustrates a typica guard ring ayout technique. V C µa LT3 S V I (MAX) ma C R C 3 F Figure 3. C and C Connections for Stabiity Figure. Guard Ring Layout 3 F Since the pin is a very high impedance node, unwanted signas may coupe into the pin and cause erratic behavior. This is most noticeabe when operating with a minimum output capacitor at heavy oad currents. Bypassing the pin with a sma capacitance to ground resoves this issue nf is sufficient. It is especiay important to bypass the pin when guard ring techniques are used since it practicay eiminates any stray pin capacitance. For appications requiring high accuracy or an adjustabe output votage, the pin may be activey driven by an externa votage source capabe of sinking µa. Connecting a precision votage reference to the pin eiminates any errors present in the output votage due to the reference current and pin resistor toerances. Output Sensing The LT3 s S pin provides a Kevin sense connection to the output. The pin resistor s side provides a Kevin sense connection to the oad s side. Additionay, as shown in Figure 3, it is very important for stabiity to tie the S pin directy to the output capacitor (C ) and the side of pin capacitor (C ) directy to the side of C as we as keep the sides of input capacitor (C ) and C cose together. Refer to the PCB Layout Considerations section for an exampe ayout that meets these requirements. Stabiity and Output Capacitance The LT3 requires an output capacitor for stabiity. Given its high bandwidth (about MHz), LTC recommends ow ESR and ESL ceramic capacitors. A minimum output capacitor with an ESR beow mω and an ESL beow nh is required for stabiity. To minimize effects of board inductances on the LT3 s dynamic performance, Kevin connect the S pin directy to the output capacitor as we as Kevin connect the side of the pin capacitor (C ) directy to the side of the output capacitor. Aso, tie the input capacitor s connection as cose as possibe to the output capacitor s connection. Given the high PSRR and ow noise performance attained using a singe ceramic output capacitor, arger vaue of output capacitor ony marginay improves the performance because the reguator bandwidth decreases with increasing output capacitance hence, there is itte to be gained by using arger than the minimum output capacitor. Nonetheess, arger vaues of output capacitance do decrease peak output deviations during a oad transient. Note that bypass capacitors used to decoupe individua components powered by the LT3 increase the effective output capacitance. Give extra consideration to the type of ceramic capacitors used. They are manufactured with a variety of dieectrics, each with different behavior across temperature and appied votage. The most common dieectrics used are specified with EIA temperature characteristic codes of ZU, YV, For more information 3f

16 LT3 APPLICATIONS FORMATION XR and X7R. The ZU and YV dieectrics are good for providing high capacitance in the sma packages, but they tend to have stronger votage and temperature coefficients as shown in Figures and. When used with a V reguator, a V µf YV capacitor can exhibit an effective vaue as ow as µf to µf for the DC bias votage appied over the operating temperature range. XR and X7R dieectrics resut in more stabe characteristics and are thus more suitabe for LT3. The X7R dieectric has better stabiity across temperature, whie the XR is ess expensive and is avaiabe in higher vaues. Nonetheess, care must sti be exercised when using XR and X7R capacitors. The XR and X7R codes ony specify operating temperature range and the maximum capacitance change over temperature. Whie capacitance change due to DC bias for XR and X7R is better than YV and ZU dieectrics, it can sti be significant enough to drop capacitance beow sufficient eves. As shown in Figure, capacitor DC bias characteristics tend to improve as component case size increases, but verification of expected capacitance at the operating votage is highy recommended. Votage and temperature coefficients are not the ony sources of probems. Some ceramic capacitors have a piezoeectric response. A piezoeectric device generates votage across its terminas due to mechanica stress upon it, simiar to how a piezoeectric microphone works. For a ceramic capacitor, this stress can be induced by mechanica vibrations within the system or due to therma transients. Stabiity and Input Capacitance The LT3 is stabe with a minimum pin capacitor. LTC recommends using ow ESR ceramic capacitors. In cases where ong wires connect the power suppy to the LT3 s input and ground terminas, the use of ow vaue input capacitors combined with a arge oad current can resut in instabiity. The resonant LC tank circuit formed by the wire inductance and the input capacitor is the cause and not because of LT3 s instabiity. The sef-inductance, or isoated inductance, of a wire is directy proportiona to its ength. The wire diameter, CHANGE VALUE (%) BOTH CAPACITORS ARE V, CASE SIZE, µf DC BIAS VOLTAGE (V) 3 F Figure. Ceramic Capacitor DC Bias Characteristics CHANGE VALUE (%) Figure. Ceramic Capacitor Temperature Characteristics CHANGE VALUE (%) Figure. Capacitor Votage Coefficient for Different Case Sizes XR YV YV BOTH CAPACITORS ARE V, CASE SIZE, µf XR 7 MURATA: X7R, V, CERAMIC DC BIAS (V) 3 F,.mm THICK,.mm THICK,.mm THICK 3 F For more information 3f

17 APPLICATIONS FORMATION however, has ess infuence on its sef-inductance. For exampe, the sef-inductance of a -AWG isoated wire with a diameter of." is about haf the inductance of a 3-AWG wire with a diameter of.". One foot of 3-AWG wire has nh of sef-inductance. Severa methods exist to reduce a wire s sef-inductance. One method divides the current fowing towards the LT3 between two parae conductors. In this case, pacing the wires further apart reduces the inductance; up to a % reduction when paced ony a few inches apart. Spitting the wires connect two equa inductors in parae. However, when paced in cose proximity to each other, their mutua inductance adds to the overa sef inductance of the wires therefore a % reduction is not possibe in such cases. The second and more effective technique to reduce the overa inductance is to pace the forward and return current conductors (the input and ground wires) in cose proximity. Two 3-AWG wires separated by." reduce the overa inductance to about one-fifth of a singe wire. If a battery mounted in cose proximity powers the LT3, a input capacitor suffices for stabiity. However, if a distanty ocated suppy powers the LT3, use a arger vaue input capacitor. Use a rough guideine of µf (in addition to the minimum) per " of wire ength. The minimum input capacitance needed to stabiize the appication aso varies with the output capacitance as we as the oad current. Pacing additiona capacitance on the LT3 s output heps. However, this requires significanty more capacitance compared to additiona input bypassing. Series resistance between the suppy and the LT3 input aso heps stabiize the appication; as itte as.ω to.ω suffices. This impedance dampens the LC tank circuit at the expense of dropout votage. A better aternative is to use a higher ESR tantaum or eectroytic capacitor at the LT3 input in parae with a ceramic capacitor. Output Noise The LT3 offers many advantages with respect to noise performance. Traditiona inear reguators have severa sources of noise. The most critica noise sources for a traditiona reguator are its votage reference, error ampifier, noise from the resistor divider network used for setting output votage and the noise gain created by this resistor LT3 divider. Many ow noise reguators pin out their votage reference to aow for noise reduction by bypassing the reference votage. Unike most inear reguators, the LT3 does not use a votage reference; instead, it uses a µa current reference. The current reference operates with typica noise current eve of pa/ Hz (na RMS over a Hz to khz bandwidth). The resutant votage noise equas the current noise mutipied by the resistor vaue, which in turn is RMS summed with the error ampifier s noise and the resistor s own noise of ktr whereby k = Botzmann s constant.3 3 J/K and T is the absoute temperature. One probem that conventiona inear reguators face is that the resistor divider setting the output votage gains up the reference noise. In contrast, the LT3 s unity-gain foower architecture presents no gain from the pin to the output. Therefore, if a capacitor bypasses the pin resistor, then the output noise is independent of the programmed output votage. The resutant output noise is then set just by the error ampifier s noise typicay nv/ Hz from khz to MHz and.µv RMS in a Hz to khz bandwidth using a pin capacitor. Paraeing mutipe LT3s further reduces noise by N, for N parae reguators. Refer to the Typica Performance Characteristics section for noise spectra density and RMS integrated noise over various oad currents and pin capacitances. Set Pin (Bypass) Capacitance: Noise, PSRR, Transient Response and Soft-Start In addition to reducing output noise, using a pin bypass capacitor aso improves PSRR and transient performance. Note that any bypass capacitor eakage deteriorates the LT3 s DC reguation. Capacitor eakage of even na is a.% DC error. Therefore, LTC recommends the use of a good quaity ow eakage ceramic capacitor. Using a pin bypass capacitor aso soft-starts the output and imits inrush current. The RC time constant, formed by the pin resistor and capacitor, contros soft-start time. Ramp-up rate from to 9% of nomina V is: t SS.3 R C For more information 3f 7

18 LT3 APPLICATIONS FORMATION Fast Start-Up For utraow noise appications that require ow /f noise (i.e. at frequencies beow Hz), a arger vaue pin capacitor is required, up to. Whie normay this woud significanty increase the reguator s start-up time, the LT3 incorporates fast start-up circuitry that increases the pin current to about ma during start-up. As shown in the Bock Diagram, the ma current source remains engaged whie is beow 3mV, uness the reguator is in current imit, dropout, therma shutdown or input votage is beow minimum V. If fast start-up capabiity is not used, tie to or to for output votages above 3mV. Note that doing so aso disabes power good functionaity. Fitering High Frequency Spikes For appications where the LT3 is used to post-reguate a switching converter, its high PSRR effectivey suppresses any noise present at the switcher s switching frequency typicay khz to MHz. However, the very high frequency (s of MHz) spikes beyond the LT3 s bandwidth associated with the switcher s power switch transition times wi amost directy pass through the LT3. Whie the output capacitor is party intended to absorb these spikes, its ESL wi imit its abiity at these frequencies. A ferrite bead or even the inductance associated with a short (e.g..") PCB trace between the switcher s output and the LT3 s input can serve as an LC-fiter to suppress these very high frequency spikes. ENABLE/UVLO The pin is used to put the reguator into a micropower shutdown state. The LT3 has an accurate.v turn-on threshod on the pin with 7mV of hysteresis. This threshod can be used in conjunction with a resistor divider from the input suppy to define an accurate undervotage ockout (UVLO) threshod for the reguator. The pin current (I EN ) at the threshod from the Eectrica Characteristics tabe needs to be considered when cacuating the resistor divider network: V (UVLO) =.V R EN I EN R EN R EN For more information The pin current (I EN ) can be ignored if R EN is ess than k. If unused, tie pin to. Programmabe Power Good As iustrated in the Bock Diagram, power good threshod is user programmabe using the ratio of two externa resistors, R and R : V ( _ THRESHOLD) =.3V R I R R If the pin increases above 3mV, the open-coector pin de-asserts and becomes high impedance. The power good comparator has 7mV hysteresis and µs of degitching. The pin current (I ) from the Eectrica Characteristics tabe must be considered when determining the resistor divider network. The pin current (I ) can be ignored if R is ess than 3k. If power good functionaity is not used, foat the pin. Pease note that programmabe power good and fast start-up capabiities are disabed for output votages beow 3mV. Externay Programmabe Current Limit The pin s current imit threshod is 3mV. Connecting a resistor from to sets the maximum current fowing out of the pin, which in turn programs the LT3 s current imit. The programming scae factor is ma kω. For exampe, a kω resistor programs the current imit to ma and a k resistor programs the current imit to.ma. For good accuracy, Kevin connect this resistor to the LT3 s pin. In cases where -to- differentia is greater than V, the LT3 s fodback circuitry decreases the interna current imit. As a resut, interna current imit may override the externay programmed current imit eve to keep the LT3 within its safe-operating-area (SOA). See the Interna Current Limit vs Input-to-Output Differentia graph in the Typica Performance Characteristics section. As shown in the Bock Diagram, the pin sources current proportiona (:) to output current; therefore, it aso serves as a current monitoring pin with a V to 3mV range. If externa current imit or current monitoring is not used, tie to. 3f

19 LT3 APPLICATIONS FORMATION Output Overshoot Recovery During a oad step from fu oad to no oad (or ight oad), the output votage overshoots before the reguator responds to turn the power transistor OFF. Given that there is no oad (or very ight oad) present at the output, it takes a ong time to discharge the output capacitor. V V ±% µf µa LT3 S mω As iustrated in the Bock Diagram, the LT3 incorporates an overshoot recovery circuitry that turns on a current sink to discharge the output capacitor in the event S is higher than. This current is typicay about ma. No oad recovery is disabed for input votages ess than.v or output votages ess than.v. If S is externay hed above, the current sink turns ON in an attempt to restore S to its programmed votage. The current sink remains ON unti the externa circuitry reeases S. µa.k LT3 S.7µF mω 3 F7 V 3.3V I (MAX) ma Direct Paraeing for Higher Current Higher output current is obtained by paraeing mutipe LT3s. Tie a pins together and a pins together. Connect the pins together using sma pieces of PCB trace (used as a baast resistor) to equaize currents in the LT3s. PCB trace resistance in miiohms/inch is shown in Tabe. Tabe. PC Board Trace Resistance WEIGHT (oz) mi WIDTH mi WIDTH Trace resistance is measured in mω/in. The sma worst-case offset of mv for each paraeed LT3 minimizes the required baast resistor vaue. Figure 7 iustrates that two LT3s, each using a mω PCB trace baast resistor, provide better than % output current sharing at fu oad. The two mω externa resistors ony add mv of output reguation drop with a ma maximum current. With a 3.3V output, this ony adds.3% to the reguation accuracy. As has been discussed previousy, tie the S pin directy to the output capacitor. More than two LT3s can aso be paraeed for even higher output current and ower output noise. Paraeing mutipe LT3s is aso usefu for distributing heat on the Figure 7. Parae Devices PCB. For appications with high input-to-output votage differentia, input series resistor or resistor in parae with the LT3 can aso be used to spread heat. PCB Layout Considerations Given the LT3 s high bandwidth and utrahigh PSRR, carefu PCB ayout must be empoyed to achieve fu device performance. Figure shows an exampe ayout that deivers fu performance of the reguator. Refer to the LT3 s DCA demo board manua for further detais. Therma Considerations The LT3 has interna power and therma imiting circuits that protect the device under overoad conditions. The therma shutdown temperature is nominay C with about C of hysteresis. For continuous norma oad conditions, do not exceed the maximum junction temperature, ( C for E-, I-grades and C for H-, MP-grades). It is important to consider a sources of therma resistance from junction to ambient. This incudes junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the appication dictates. Additionay, For more information 3f 9

20 LT3 APPLICATIONS FORMATION Figure. Exampe DFN Layout 3 F consider a heat sources in cose proximity to the LT3. The undersides of the DFN and MSOP packages have exposed meta from the ead frame to the die attachment. Both packages aow heat to directy transfer from the die junction to the PCB meta to imit maximum operating junction temperature. The dua-in-ine pin arrangement aows meta to extend beyond the ends of the package on the topside (component side) of the PCB. For surface mount devices, heat sinking is accompished by using the heat spreading capabiities of the PCB and its copper traces. Copper board stiffeners and pated throughhoes can aso be used to spread the heat generated by the reguator. Tabes 3 and ist therma resistance as a function of copper area on a fixed board size. A measurements were taken in sti air on a ayer FR- board with oz soid interna panes and oz top/bottom panes with a tota board thickness of.mm. The four ayers were eectricay isoated with no therma vias present. PCB ayers, copper weight, board ayout and therma vias affect the resutant therma resistance. For more information on therma resistance and high therma conductivity test boards, refer to JEDEC standard JESD, notaby JESD-7 and JESD-. Achieving ow therma resistance necessitates attention to detai and carefu PCB ayout. Tabe 3. Measured Therma Resistance for DFN Package TOP SIDE* COPPER AREA BOTTOM SIDE BOARD AREA THERMAL RESISTANCE mm mm mm 3 C/W mm mm mm 3 C/W mm mm mm 3 C/W mm mm mm 3 C/W *Device is mounted on topside Tabe. Measured Therma Resistance for MSOP Package TOP SIDE* COPPER AREA BOTTOM SIDE BOARD AREA THERMAL RESISTANCE mm mm mm 33 C/W mm mm mm 33 C/W mm mm mm 3 C/W mm mm mm 3 C/W *Device is mounted on topside Cacuating Junction Temperature Exampe: Given an output votage of.v and input votage of V ± %, output current range from ma to ma, and a maximum ambient temperature of C, what is the maximum junction temperature? The LT3 s power dissipation is: I (MAX) (V (MAX) V ) I V (MAX) where: I (MAX) = ma V (MAX) =.V I (at I = ma and V =.V) = 7.mA thus: P DISS =.A (.V.V) 7.mA.V =.9W Using a DFN package, the therma resistance is in the range of 3 C/W to 3 C/W depending on the copper area. Therefore, the junction temperature rise above ambient approximatey equas:.9w 3 C/W =.7 C For more information 3f

21 APPLICATIONS FORMATION The maximum junction temperature equas the maximum ambient temperature pus the maximum junction temperature rise above ambient: T JMAX = C.7 C =.7 C Overoad Recovery Like many IC power reguators, the LT3 incorporates safe-operating-area (SOA) protection. The SOA protection activates at input-to-output differentia votages greater than V. The SOA protection decreases the current imit as the input-to-output differentia increases and keeps the power transistor inside a safe operating region for a vaues of input-to-output votages up to the LT3 s absoute maximum ratings. The LT3 provides some eve of output current for a vaues of input-to-output differentias. Refer to the Current Limit curves in the Typica Performance Characteristics section. When power is first appied and input votage rises, the output foows the input and keeps the input-to-output differentia ow to aow the reguator to suppy arge output current and start-up into high current oads. Due to current imit fodback, however, at high input votages a probem can occur if the output votage is ow and the oad current is high. Such situations occur after the remova of a short-circuit or if the pin is pued high after the input votage has aready turned ON. The oad ine in such cases intersects the output current profie at two points. The reguator now has two stabe operating points. With this doube intersection, the input power suppy may need to be cyced down to zero and brought back up again to make the output recover. Other inear reguators with fodback current imit protection (such as the LT9 and LT93A, etc.) aso exhibit this phenomenon, so it is not unique to the LT3. LT3 Protection Features The LT3 incorporates severa protection features for battery-powered appications. Precision current imit and therma overoad protection protect the LT3 against overoad and faut conditions at the device s output. For norma operation, do not aow the junction temperature to exceed C (E-, I-grade) or C (H-, MP-grade). To protect the LT3 s ow noise error ampifier, the -to-s protection camp imits the maximum votage between and S to ±V with a maximum DC current of ma through the camp. So for appications where is activey driven by a votage source, the votage source must be current imited to ma or ess. Moreover, to imit the transient current fowing through these camps during a transient faut condition, imit the maximum vaue of the pin capacitor (C ) to µf. The LT3 aso incorporates reverse input protection whereby the pin withstands reverse votages of up to V without causing any input current fow and without deveoping negative votages at the pin. The reguator protects both itsef and the oad against batteries that are pugged-in backwards. In circuits where a backup battery is required, severa different input/output conditions can occur. The output votage may be hed up whie the input is either pued to, pued to some intermediate votage, or eft opencircuit. In a of these cases, the reverse current protection circuitry prevents current fow from output to the input. Nonetheess, due to the S-to- camp, uness the pin is foating, current can fow to through the pin resistor as we as up to ma to through the output overshoot recovery circuitry. This current fow through the output overshoot recovery circuitry can be significanty reduced by pacing a Schottky diode between S and pins, with its anode at the S pin. For more information 3f

22 LT3 TYPICAL APPLICATIONS V V to 3V V with.µv RMS Integrated Noise V V ±% µa LT3 k S V 3.3V I (MAX) ma 3k 33.k 9.9k 3 TA Disabed without Reverse Input Protection Disabed with Reverse Input Protection V LT3 V LT3 µa µa S V N S V.7µF R.7µF R 3 TA 3 TA Low Noise CC/CV Lab Power Suppy V LT3 µa S V.7µF R R I 3 TA3 For more information 3f

23 TYPICAL APPLICATIONS Programming Undervotage Lockout LT3 V V Turn-ON 3.V Turn-OFF µa LT3 V (UVLO) =.V k 9.9k R EN k R EN 9.9k S V 3.3V I (MAX) ma.7µf 33.k 3 TA Ratiometric Tracking LT3 µa V.V TO V µa LT3 S.µF.9k V 3.3V M LOAD µa S 3 TA V V.µF 33.k For more information 3f 3

24 LT3 TYPICAL APPLICATIONS Reference Buffer V LT3 µa S V I (MAX) ma PUT LT9 PUT 3 TA Paraeing Mutipe Devices Using (Current Monitor) to Cance Baast Resistor Drop V V LT3 LT3 µf µa µa V = 3.3V I (MAX) = ma S mω mω S R 9Ω 9Ω 3 TA3 µf.k N = NUMBER OF DEVICES PARALLEL R CDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTOR R = CURRENT LIMIT PROGRAMMG RESISTOR R BALLAST = BALLAST RESISTOR = PUT CURRENT LIMIT R CDC Ω R = ma kω/ R CDC N = 9Ω (FOR ma PER REGULATOR) R CDC = R BALLAST /N = Ω For more information 3f