LTC /LTC V Microprocessor Supervisory Circuits APPLICATIONS TYPICAL APPLICATION

Transcription

1 Microprocessor Supervisory Circuits FEATURES n Guaranteed Reset Assertion at = 1 n Pin Compatibe with LTC69/LTC695 for Systems n 2μA Typica Suppy Current n Fast (ns Typ) Onboard Gating of RAM Chip Enabe Signas n SO-8 and S16 Packages n 2.9 Precision otage Monitor n Power OK/Reset Time Deay: 2ms or Adjustabe n Minimum Externa Component Count n 1μA Maximum Standby Current n otage Monitor for Power-Fai or Low-Battery Warning n Therma Limiting n Performance Specified Over Temperature APPLICATIONS n Low Power Systems n Critica μp Power Monitoring n Inteigent Instruments n Battery-Powered Computers and Controers n Automotive Systems L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. DESCRIPTION The LTC 69-./ provide compete power suppy monitoring and battery contro functions. These incude power-on reset, battery back-up, RAM write protection, power faiure warning and watchdog timing. The devices are pin compatibe upgrades of the LTC69/LTC695 that are optimized for systems. Operating power consumption has been reduced to.6mw (typica) and μw maximum in battery back-up mode. Microprocessor reset and memory write protection are provided when the suppy fas beow 2.9. The output is guaranteed to remain ogic ow with as ow as 1. The LTC69-./ power the active RAMs with a charge pumped NMOS power switch to achieve ow dropout and ow suppy current. When primary power is ost, auxiiary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an eary warning of impending power faiure, the LTC69-./ provide an interna comparator with a user-defined threshod. An interna watchdog timer is aso avaiabe, which forces the reset pins to active states when the watchdog input is not togged prior to a preset timeout period. TYPICAL APPLICATION IN k 18k 1μF LT IN OUT OUT SENSE SHDN 1μF 2. MICROPROCESSOR, BATTERY BACK-UP, RAM WRITE PROTECTION, POWER WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEM + PFI OUT CE IN CE OUT PFO WDI 1Ω POWER TO μp CMOS RAM POWER μp SYSTEM DECODER OUTPUT RAM CS μp μp NMI I/O LINE OUTPUT OLTAGE () Output otage vs Suppy otage 69/5-. TA SUPPLY OLTAGE () 69/5-. TA2 1

2 ABSOLUTE MAXIMUM RATINGS Termina otage.... to to 6 A Other Inputs.... to ( OUT +.) Input Current...1mA...25mA...1mA (Notes 1 and 2) OUT Output Current... Short-Circuit Protected Power Dissipation... 5mW Operating Temperature Range LTC69C-./LTC695C-.... C to 7 C LTC69I-./LTC695I-.... C to 85 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec)... C PIN CONFIGURATION OUT BATT ON LOW LINE OSC IN OSC SEL TOP IEW N PACKAGE 16-LEAD PDIP WDO 1 CE IN 12 CE OUT 11 WDI 1 PFO 9 PFI T JMAX = 11 C, θ JA = 1 C/W TOP IEW 1 OUT 2 CC BATT ON LOW LINE 5 OSC IN 6 OSC SEL 7 8 TOP IEW WDO 1 CE IN 12 CE OUT 11 WDI 1 PFO 9 PFI SW PACKAGE 16-LEAD PLASTIC WIDE SO T JMAX = 11 C, θ JA = 1 C/W TOP IEW OUT 1 8 OUT WDI 6 WDI PFI 5 PFO PFI 5 PFO N8 PACKAGE 8-LEAD PDIP T JMAX = 11 C, θ JA = 1 C/W S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 11 C, θ JA = 18 C/W 2

3 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC695CN-.#PBF LTC695CN-.#TRPBF LTC695CN-. 16-Lead PDIP C to 7 C LTC695IN-.#PBF LTC695IN-.#TRPBF LTC695IN-. 16-Lead PDIP C to 85 C LTC695CSW-.#PBF LTC695CSW-.#TRPBF LTC695CSW-. 16-Lead Pastic Wide SO C to 7 C LTC695ISW-.#PBF LTC695ISW-.#TRPBF LTC695ISW-. 16-Lead Pastic Wide SO C to 85 C LTC69CN8-.#PBF LTC69CN8-.#TRPBF LTC69CN8-. 8-Lead PDIP C to 7 C LTC69IN8-.#PBF LTC69IN8-.#TRPBF LTC69IN8-. 8-Lead PDIP C to 85 C LTC69CS8-.#PBF LTC69CS8-.#TRPBF 69 8-Lead Pastic SO C to 7 C LTC69IS8-.#PBF LTC69IS8-.#TRPBF 69I 8-Lead Pastic SO C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on non-standard ead based finish parts. Consut LTC Marketing for miitary grade parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: PRODUCT SELECTION GUIDE PINS THRESHOLD () WATCHDOG TIMER BATTERY BACK-UP POWER-FAIL WARNING RAM WRITE PROTECT PUSH-BUTTON CONDITIONAL BATTERY BACK-UP LTC X X X X X X X LTC X X X LTC X X X X LTC X X X LTC X X X X LTC X LTC /.62 X X LTC X X X X X X

4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. =, = 2, uness otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Back-Up Switching Operating otage Range OUT Output otage I OUT = 1mA I OUT = 5mA.8. OUT in Battery Back-Up Mode I OUT = 25μA, <.1.2 Suppy Current (Excude I OUT ) I OUT 5μA, = ma.2 1. ma Suppy Current in Battery Back-Up Mode =, = 2. 1 μa. 5 μa Battery Standby Current (+ = Discharge, = Charge).6 > > μa.1.1 μa Battery Switchover Threshod ( ) Power-Up Power-Down 7 5 m m Battery Switchover Hysteresis 2 m BATT ON Output otage (Note ) I SINK = 8μA. BATT ON Output Short-Circuit Current (Note ) BATT ON = OUT, Sink Current BATT ON =, Source Current Reset and Watchdog Timer Reset otage Threshod Reset Threshod Hysteresis m Reset Active Time OSC SEL HIGH, = ms ms Watchdog Timeout Period, Interna Osciator Long Period, = sec sec Short Period, = ms ms Watchdog Timeout Period, Externa Cock (Note 5) Long Period, = Short Period, = Cock Cyces Reset Active Time PSRR ms/ Watchdog Timeout Period PSRR, Interna OSC Short Period Long Period Minimum WDI Input Puse Width IL =., IH = 2 ns Output otage at = 1 I SINK = 1μA, = 1 2 m and LOW _ LINE Output otage (Note ) I SINK = μa, = 2.8 I SOURCE =.1μA, = and WDO Output otage (Note ),, WDO, LOW _ LINE Output Short-Circuit Current (Note ) WDI Input Threshod WDI Input Current I SINK = μa, = I SOURCE =.1μA, = 2.8 Output Source Current Output Sink Current Logic Low Logic High WDI = OUT WDI = ma μa ms/ ms/.. 25 μa ma. 5 μa μa

5 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. =, = 2, uness otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Power-Fai Detector PFI Input Threshod PFI Input Threshod PSRR. m/ PFI Input Current ±.1 ±25 na PFO Output otage (Note ) I SINK = 8μA. I SOURCE =.1μA 2. PFO Short-Circuit Source Current (Note ) PFI = HIGH, PFO = 1 PFI = LOW, PFO = OUT μa μa PFI Comparator Response Time (Faing) Δ IN = 2m, OD = 15m 2 μs PFI Comparator Response Time (Rising) (Note ) Δ IN = 2m, OD = 15m with 1kΩ Pu-Up 8 μs μs Chip Enabe Gating CE IN Threshod IL IH CE IN Pu-Up Current (Note 6) μa CE OUT Output otage I SINK = 8μA. I SOURCE = μa I SOURCE = 1μA, = OUT.5 OUT.5 CE IN Propagation Deay C L = 2pF 5 ns CE OUT Output Short-Circuit Current Output Source Current Output Sink Current Osciator OSC IN Input Current (Note 6) ±2 μa OSC SEL Input Pu-Up Current (Note 6) 5 μa OSC IN Frequency Range OSC SEL = 125 khz OSC SEL =, C A = 7pF khz 15 2 ma ma Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A votage vaues are with respect to. Note : For miitary temperature range parts, consut the factory. Note : The output pins of BATT ON, LOW _ LINE, PFO, WDO, and have weak interna pu-ups of typicay μa. However, externa puup resistors may be used when higher speed is required. Note 5: The externa cock feeding into the circuit passes through the osciator before cocking the watchdog timer. ariation in the timeout period is caused by phase errors which occur when the osciator divides the externa cock by 6. The resuting variation in the timeout period is 6 pus one cock of jitter. Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak interna pu-ups which pu to the suppy when the input pins are foating. 5

6 TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT OLTAGE () Output otage vs Load Current SLOPE =.6Ω = = 2. T A = 25 C OUTPUT OLTAGE () Output otage vs Load Current SLOPE = 9Ω = = 2. T A = 25 C PFI INPUT THRESHOLD () Power Faiure Input Threshod vs Temperature = PFO OUTPUT OLTAGE () LOAD CURRENT (ma) Power-Fai Comparator Response Time 69/5-. G1 = T A = 25 C PFI + PFO 1. pf PFO OUTPUT OLTAGE () LOAD CURRENT (μa) Power-Fai Comparator Response Time = T A = 25 C 69/5-. G2 PFI + PFO 1. pf PFO OUTPUT OLTAGE () TEMPERATURE ( C) Power-Fai Comparator Response Time with Pu-Up Resistor = T A = 25 C 69/5-. G PFI + 1k PFO 1. pf PFI = 2m STEP PFI = 2m STEP PFI = 2m STEP TIME (μs) TIME (μs) TIME (μs) /5-. G 69/5-. G5 69/5-. G6 22 Reset Active Time vs Temperature = 2.9 Reset otage Threshod vs Temperature = 5 Output otage vs Suppy otage ACTIE TIME (ms) OLTAGE THRESHOLD () OUTPUT OLTAGE () TEMPERATURE ( C) TEMPERATURE ( C) SUPPLY OLTAGE () 69/5-. G7 69/5-. G8 69/5-. G9 6

7 PIN FUNCTIONS BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes ow when OUT is internay connected to. The output typicay sinks 25mA and can provide base drive for an externa PNP transistor to increase the output current above the 5mA rating of OUT. BATT ON goes high when OUT is internay switched to. CE IN: Logic Input to the Chip _ Enabe Gating Circuit. CE IN can be derived from microprocessor s address ine and/or decoder output. See the Appications Information section and Figure 5 for additiona information. CE OUT: Logic Output on the Chip _ Enabe Gating Circuit. When is above the reset votage threshod, CE OUT is a buffered repica of CE IN. When is beow the reset votage threshod CE OUT is forced high (see Figure 5). : Ground Pin. LOW _ LINE: Logic Output from Comparator C1. LOW _ LINE indicates a ow ine condition at the input. When fas beow the reset votage threshod (2.9 typicay), LOW _ LINE goes ow. As soon as rises above the reset votage threshod, LOW _ LINE returns high (see Figure 1). LOW _ LINE goes ow when drops beow (see Tabe 1). OSC IN: Osciator Input. OSC IN can be driven by an externa cock signa or an externa capacitor can be connected between OSC IN and when OSC SEL is forced ow. In this configuration the nomina reset active time and watchdog timeout period are determined by the number of cocks or set by the formua (see the Appications Information section). When OSC SEL is high or foating, the interna osciator is enabed and the reset active time is fixed at 2ms typica for the. OSC IN seects between the 1.6 seconds and 1ms typica watchdog timeout periods. In both cases, the timeout period immediatey after a reset is 1.6 seconds typica. OSC SEL: Osciator Seection Input. When OSC SEL is high or foating, the interna osciator sets the reset active time and watchdog timeout period. Forcing OSC SEL ow, aows OSC IN to be driven from an externa cock signa or an externa capacitor can be connected between OSC IN and. PFI: Power Faiure Input. PFI is the noninverting input to the power-fai comparator, C. The inverting input is internay connected to a 1. reference. The power faiure output remains high when PFI is above 1. and goes ow when PFI is beow 1.. Connect PFI to or OUT when C is not used. PFO: Power Faiure Output from C. PFO remains high when PFI is above 1. and goes ow when PFI is beow 1.. When is ower than, C is shut down and PFO is forced ow. : Active High Logic Output. It is the inverse of. : Logic Output for μp Reset Contro. Whenever fas beow either the reset votage threshod (2.9, typicay) or, goes active ow. After returns to, the reset puse generator forces to remain active ow for a minimum of 1ms. When the watchdog timer is enabed but not serviced prior to a preset timeout period, the reset puse generator aso forces to active ow for a minimum of 1ms for every preset timeout period (see Figure 11). The reset active time is adjustabe on the. An externa push-button reset can be used in connection with the output. See Push-Button Reset in the Appications Information section. : Back-Up Battery Input. When fas beow, auxiiary power connected to, is deivered to OUT through PMOS switch, M2. If back-up battery or auxiiary power is not used, shoud be connected to. : Suppy Input. The pin shoud be bypassed with a capacitor. OUT : otage Output for Backed Up Memory. Bypass with a capacitor of or greater. During norma operation, OUT obtains power from through an NMOS power switch, M1, which can deiver up to 5mA and has a typica on resistance of 5Ω. When is ower than, OUT is internay switched to. If OUT and are not used, connect OUT to. 7

8 PIN FUNCTIONS WDI: Watchdog Input. WDI is a three-eve input. Driving WDI either high or ow for onger than the watchdog timeout period, forces both and WDO ow. Foating WDI disabes the watchdog timer. The timer resets itsef with each transition of the watchdog input (see Figure 11). WDO: Watchdog Logic Output. When the watchdog input remains either high or ow for onger than the watchdog timeout period, WDO goes ow. WDO is set high whenever there is a transition on the WDI pin, or LOW _ LINE goes ow. The watchdog timer can be disabed by foating WDI (see Figure 11). BLOCK DIAGRAM M2 OUT M1 C2 + CHARGE PUMP BATT ON 1. + C1 LOW LINE CE OUT CE IN PFI + C PFO OSC IN OSC SEL OSC PULSE GENERATOR WDI TRANSITION DETECTOR WATCHDOG TIMER WDO 69/5-. BD 8

9 APPLICATIONS INFORMATION Microprocessor Reset The LTC69-./ use a bandgap votage reference and a precision votage comparator C1 to monitor the suppy input on (see the Bock Diagram). When fas beow the reset votage threshod, the output is forced to active ow state. The reset votage threshod accounts for a 1% variation on, so the output becomes active ow when fas beow. (2.9 typica). On power-up, the signa is hed active ow for a minimum of 1ms after reset votage threshod is reached to aow the power suppy and microprocessor to stabiize. The reset active time is adjustabe on the. On power-down, the signa remains active ow even with as ow as 1. This capabiity heps hod the microprocessor in stabe shutdown condition. Figure 1 shows the timing diagram of the signa. The precision votage comparator, C1, typicay has m of hysteresis which ensures that gitches at pin do not activate the output. Response time is typicay 1ms. To hep prevent mistriggering due to transient oads, the pin shoud be bypassed with a capacitor with the eads trimmed as short as possibe. The has two additiona outputs: and LOW _ LINE. is an active high output and is the inverse of. LOW _ LINE is the output of the precision votage comparator C1. When fas beow the reset votage threshod, LOW _ LINE goes ow. LOW _ LINE returns high as soon as rises above the reset votage threshod. Battery Switchover The battery switchover circuit compares to the input, and connects OUT to whichever is higher. When rises to 7m above, the battery switchover comparator, C2, connects OUT to through a charge pumped NMOS power switch, M1. When fas to 5m above, C2 connects OUT to through a PMOS switch, M2. C2 has typicay 2m of hysteresis to prevent spurious switching when remains neary equa to. The response time of C2 is approximatey 2μs. During norma operation, the LTC69-./ use a charge-pumped NMOS power switch to achieve ow dropout and ow suppy current. This power switch can deiver up to 5mA to OUT from and has a typica on resistance of 5Ω. The OUT pin shoud be bypassed with a capacitor of or greater to ensure stabiity. Use of a arger bypass capacitor is advantageous for suppying current to heavy transient oads. When operating currents arger than 5mA are required from OUT, or a ower dropout ( OUT votage differentia) is desired, the shoud be used. This product provides BATT ON output to drive the base of an externa PNP transistor (Figure 2). If higher currents are needed with the LTC69-., a high current Schottky diode can be connected from the pin to the OUT pin to suppy the extra current = OLTAGE THRESHOLD 2 = OLTAGE THRESHOLD + THRESHOLD HYSTERESIS 1 t 1 t 1 t 1 = ACTIE TIME LOW LINE 69/5-. F1 Figure 1. Reset Active Time 9

10 APPLICATIONS INFORMATION ANY PNP POWER TRANSISTOR I = OUT R BATT ON OUT 2 2. R OUT LTC /5-. F2 69/5-. F Figure 2. Using BATT ON to Drive Externa PNP Transistor Figure. Charging Externa Battery Through OUT The LTC69-./ are protected for safe area operation with short-circuit imit. Output current is imited to approximatey 2mA. If the device is overoaded for a ong period of time, therma shutdown turns the power switch off unti the device coos down. The threshod temperature for therma shutdown is approximatey 155 C with about 1 C of hysteresis which prevents the device from osciating in and out of shutdown. The PNP switch used in competitive devices was not chosen for the interna power switch because it injects unwanted current into the substrate. This current is coected by the pin in competitive devices and adds to the charging current of the battery which can damage ithium batteries. The LTC69-./ use a charge-pumped NMOS power switch to eiminate unwanted charging current whie achieving ow dropout and ow suppy current. Since no current goes to the substrate, the current coected by pin is stricty junction eakage. A 125Ω PMOS switch connects the input to OUT in battery back-up mode. The switch is designed for very ow dropout votage (input-to-output differentia). This feature is advantageous for ow current appications such as battery back-up in CMOS RAM and other ow power CMOS circuitry. The suppy current in battery back-up mode is 1μA maximum. The operating votage at the pin ranges from 1.5 to The charging resistor for rechargeabe batteries shoud be connected to OUT since this eiminates the discharge path that exists when the resistor is connected to (Figure ). Repacing the Back-Up Battery When changing the back-up battery with system power on, spurious resets can occur whie the battery is removed due to battery standby current. Athough battery standby current is ony a tiny eakage current, it can sti charge up the stray capacitance on the pin. The osciation cyce is as foows: When reaches within 5m of, the LTC69-./ switch to battery backup. OUT pus ow and the device goes back to norma operation. The eakage current then charges up the pin again and the cyce repeats. If spurious resets during battery repacement pose no probems, then no action is required. Otherwise, a resistor from to wi hod the pin ow whie changing the battery. For exampe, the battery standby current is 1μA maximum over temperature so the externa resistor required to hod beow is: R 5m 1µA With =, a 2.7M resistor wi work. With a 2 battery, this resistor wi draw ony.7μa from the battery, which is negigibe in most cases. 1

11 APPLICATIONS INFORMATION If battery connections are made through ong wires, a 1Ω to 1Ω series resistor and a capacitor are recommended to prevent any overshoot beyond due to the ead inductance (Figure ). 1Ω 2.7M LTC69-. Tabe 1 shows the state of each pin during battery back-up. When the battery switchover section is not used, connect to and OUT to. Tabe 1. Input and Output Status in Battery Back-Up Mode SIGNAL STATUS C2 monitors for active switchover. OUT OUT is connected to through an interna PMOS switch. The suppy current is 1μA maximum. BATT ON Logic high. The open-circuit output votage is equa to OUT. PFI Power faiure input is ignored. PFO Logic ow. Logic ow. Logic high. The open-circuit output votage is equa to OUT. LOW _ LINE Logic ow. WDI Watchdog input is ignored. WDO Logic high. The open-circuit output votage is equa to OUT. CE IN Chip _ Enabe input is ignored. CE OUT Logic high. The open-circuit output votage is equa to OUT. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. Figure. 1Ω/ Combination Eiminates Inductive Overshoot and Prevents Spurious Resets During Battery Repacement. The 2.7M Pus the Pin to Ground Whie the Battery is Removed, Eiminating Spurious Resets Memory Protection The incudes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when is at invaid eve. Two additiona pins, CE IN and CE OUT, contro the Chip _ Enabe or Write inputs of CMOS RAM. When is, CE OUT foows CE IN with a typica propagation deay of ns. When fas beow the reset votage threshod or, CE OUT is forced high, independent of CE IN. CE OUT is an aternative signa to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can aso be used to drive the Store or Write input of an EEPROM, EAROM or NORAM to achieve simiar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. 69/5-. F = OLTAGE THRESHOLD 2 = OLTAGE THRESHOLD + THRESHOLD HYSTERESIS CE IN CE OUT OUT = OUT = 69/5-. F5 Figure 5. Timing Diagram for CE IN and CE OUT 11

12 APPLICATIONS INFORMATION 2. OUT CE OUT CE IN + 1μF FROM DECODER TO μp RAM CS ns PROPAGATION DELAY 69/5-. F6 Figure 6. A Typica Nonvoatie CMOS RAM Appication 2. IN 5 R1 51k R2 16k OUT LTC μF Figure 7. Write Protect for RAM with LTC69-. 1μF LT IN OUT + + OUT SENSE SHDN ADJ 1μF R 2k R 1k CS RAM CS1 CS2 PFO PFI TO μp 69/5-. F7 LTC69-. Figure 8. Monitoring Unreguated DC Suppy with the LTC69-./ s Power-Fai Comparator IN 6.5 1μF LT IN OUT OUT SENSE SHDN ADJ + + 1μF R1 R 27k 1k R 2.7M R2 16k R5 5k PFO PFI TO μp LTC /5-. F8 69/5-. F9 CE IN can be derived from the microprocessor s address decoder output. Figure 6 shows a typica nonvoatie CMOS RAM appication. Memory protection can aso be achieved with the LTC69-. by using as shown in Figure 7. Power-Fai Warning The LTC69-./ generate a Power Faiure Output (PFO) for eary warning of faiure in the microprocessor s power suppy. This is accompished by comparing the power faiure input (PFI) with an interna 1. reference. PFO goes ow when the votage at the PFI pin is ess than 1.. Typicay PFI is driven by an externa votage divider (R1 and R2 in Figures 8 and 9) which senses either an unreguated DC input or a reguated output. The votage divider ratio can be chosen such that the votage at the PFI pin fas beow 1. severa miiseconds before the suppy fas beow the maximum reset votage threshod.. PFO is normay used to interrupt the microprocessor to execute shutdown procedure between PFO and or. The power-fai comparator, C, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and ower trip points in the comparator are estabished as foows: When PFO output is ow, R sinks current from the summing junction at the PFI pin. H =1. 1+ R1 R2 + R1 R When PFO output is high, the series combination of R and R source current into the PFI summing junction. L =1. 1+ R1 ( ±1.)R1 R2 1.(R + R) Assuming R << R, HYSTERESIS = R1 R Figure 9. Monitoring Reguated DC Suppy with the LTC69-./ s Power-Fai Comparator 12

13 APPLICATIONS INFORMATION Exampe 1: The circuit in Figure 8 demonstrates the use of the power-fai comparator to monitor the unreguated power suppy input. Assuming the the rate of decay of the suppy input IN is 1m/ms and the tota time to execute a shutdown procedure is 8ms. Aso the noise of IN is 2m. With these assumptions in mind, we can reasonaby set L = 5 which is 1.6 greater than the sum of maximum reset votage threshod and the dropout votage of the LT ( +.) and HYSTERESIS = 85m. HYSTERESIS = R1 R = 85m R.88 R1 Choose R = 2k and R1 = 51k. Aso seect R = 1k which is much smaer than R. 5 = k ( 1.)51k R2 1.(21k) R2 = 15.8k, Choose nearest 5% resistor 16k and recacuate L, L = k ( 1.)51k 16k 1.(21k) =.96 H = k 16 k + 51k 2k =5.77 (.96.) 1m / ms = 15.6ms HYSTERESIS = = 81m The 15.6ms aows enough time to execute shutdown procedure for microprocessor and 81m of hysteresis woud prevent PFO from going ow due to the noise of IN. Exampe 2: The circuit in Figure 9 can be used to measure the reguated suppy to provide eary warning of power faiure. Because of variations in the PFI threshod, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshod is reached. Adjust R5 such that the PFO output goes ow when the suppy reaches the desired eve (e.g.,.1). LTC69-./ Monitoring the Status of the Battery C can aso monitor the status of the memory back-up battery (Figure 1). If desired, the CE OUT can be used to appy a test oad to the battery. Since CE OUT is forced high in battery back-up mode, the test oad wi not be appied to the battery whie it is in use, even if the microprocessor is not powered. 2. R1 1M R2 1.6M R L 2k OPTIONAL TEST LOAD PFI CE OUT PFO CE IN LOW-BATTERY SIGNAL T μp I/O PIN I/O PIN 69/5-. F1 Figure 1. Back-Up Battery Monitor with Optiona Test Load Watchdog Timer The LTC69-./ provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not togge the watchdog input (WDI) within a seected timeout period, is forced to active ow for a minimum of 1ms. The reset active time is adjustabe on the. Since many systems can not service the watchdog timer immediatey after a reset, the has a onger timeout period (1. second minimum) right after a reset is issued. The norma timeout period (7ms minimum) becomes effective foowing the first transition of WDI after is inactive. The watchdog timeout period is fixed at 1. second minimum on the LTC69-.. Figure 11 shows the timing diagram of watchdog timeout period and reset active time. The watchdog timeout period is restarted as soon as is inactive. When either a high-to-ow or ow-to-high transition occurs at the WDI pin prior to timeout, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a high-to-ow or ow-to-high transition on the WDI pin must occur at or ess than the minimum timeout period. If the input to the 1

14 APPLICATIONS INFORMATION = WDI WDO t 1 = ACTIE TIME t 2 = NORMAL WATCHDOG TIMEOUT PERIOD t = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER A t 2 t t 1 t 1 69/5-. F11 Figure 11. Watchdog Timeout Period and Reset Active Time EXTERNAL CLOCK EXTERNAL OSCILLATOR OSC SEL 8 OSC SEL 8 OSC IN 7 OSC IN 7 INTERNAL OSCILLATOR 1.6 SECOND WATCHDOG 8 FLOATING CC OSC SEL OR HIGH INTERNAL OSCILLATOR 1ms WATCHDOG OSC SEL 8 FLOATING OR HIGH 7 FLOATING OSC IN OR HIGH OSC IN 7 Figure 12. Osciator Configurations 69/5-. F12 WDI pin remains either high or ow, reset puses wi be issued every 1.6 seconds typicay. The watchdog time can be deactivated by foating the WDI pin. The timer is aso disabed when fas beow the reset votage threshod or. The provides an additiona output (Watchdog Output, WDO) which goes ow if the watchdog timer is aowed to time out and remains ow unti set high by the next transition on the WDI pin. WDO is aso set high when fas beow the reset votage threshod or. 1 The has two additiona pins, OSC SEL and OSC IN, which aow reset active time and watchdog timeout period to be adjusted per Tabe 2. Severa configurations are shown in Figure 12. OSC IN can be driven by an externa cock signa or an externa capacitor can be connected between OSC IN and when OSC SEL is forced ow. In these configurations, the nomina reset active time and watchdog timeout period are determined by the number of cocks or set by the formua in Tabe 2. When OSC SEL is high or foating,

15 TYPICAL APPLICATION Tabe 2. Reset Active Time and Watchdog Timeout Seections WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER OSC SEL OSC IN NORMAL (SHORT PERIOD) (LONG PERIOD) Low Externa Cock Input 12 CLKs 96 CLKs 28 CLKs Low Externa Capacitor* ms 7pF C 1.6s 7pF C ACTIE TIME 8ms 7pF C Foating or High Low 1ms 1.6 sec 2ms Foating or High Foating or High 1.6 sec 1.6 sec 2ms *The nomina interna frequency is 1.2kHz. The nomina osciator frequency with externa capacitor is f OSC (Hz) = 18, C(pF) 125 the interna osciator is enabed and the reset active time is fixed at 1ms minimum for the. OSC IN seects between the 1 second and 7ms minimum norma watchdog timeout periods. In both cases, the timeout period immediatey after a reset is at east 1 second. The 1Ω resistor in series with the push-button is required to prevent the ringing, due to the capacitance and ead inductance, from puing the pins of the MPU and LTC69X beow ground. Push-Button Reset The LTC69-./ do not provide a ogic input for direct connection to a push-button. However, a pushbutton in series with a 1Ω resistor connected to the output pin (Figure 1) provides an aternative for manua reset. Connecting a capacitor to the pin debounces the push-button input. LTC69-. 1Ω Figure 1. The Externa Push-Button Reset MPU (e.g. 68HC5) 69/5-. F1 TYPICAL APPLICATION Capacitor Back-Up with 7HC16 Switch OUT R1 1k HC LOW LINE R2 k 7 1 1μF + 69/5-. TA 15

16 PACKAGE DESCRIPTION N8 Package 8-Lead PDIP (Narrow.) (Reference LTC DWG # )..25 ( ).5.65 ( ).1.5 (.2.127).* (1.16) MAX (.2.81) (1.651) TYP.1 (2.5) BSC NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.1 INCH (.25mm) N * ( ).12 (.8) MIN.2 (.58) (.57.76) MIN S8 Package 8-Lead Pastic Sma Outine (Narrow.15) (Reference LTC DWG # ).5 BSC.5 ± (.81 5.) NOTE MIN.16 ± ( ) ( ) NOTE. ±.5 TYP RECOMMENDED SOLDER PAD LAYOUT (.2.25).1.2 (.25.58) 5 8 TYP.5.69 ( )..1 (.11.25).16.5 ( ) NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS).1.19 (.55.8) TYP 2. DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.6" (.15mm).5 (1.27) BSC SO8 16

17 PACKAGE DESCRIPTION N Package 16-Lead PDIP (Narrow.) (Reference LTC DWG # ) LTC69-./.77* (19.558) MAX ±.15* (6.77 ±.81) ( ).1 ±.5 (.2 ±.127).5.65 ( ).8.15 (.2.81) ( ) NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS.2 (.58) MIN.12 (.8) MIN *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.1 INCH (.25mm).1 (2.5) BSC.65 (1.651) TYP.18 ±. (.57 ±.76) N

18 PACKAGE DESCRIPTION SW Package 16-Lead Pastic Sma Outine (Wide.) (Reference LTC DWG # ). ±.5 TYP N.5 BSC.5 ± ( ) NOTE N.2 MIN.25 ±.5 NOTE.9.19 ( ) 1 2 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT (.127) RAD MIN ( ) NOTE (.25.77) 8 TYP.9.1 ( ).7.5 (.9 1.1) (1.27) (.229.) NOTE BSC (.56.82) ( ) TYP NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE. PIN 1 IDENT, NOTCH ON TOP AND CAITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.6" (.15mm)..12 (.12.5) S16 (WIDE) 52 18

19 REISION HISTORY (Revision history begins at Rev B) RE DATE DESCRIPTION PAGE NUMBER B /1 Removed UL Recognized and UL fie number from the Features section. 1 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 19

20 TYPICAL APPLICATION Write Protect for Additiona RAMs 2. OUT CE OUT CE IN LOW LINE + 1μF ns PROPAGATION DELAY CS A LH5168SH RAM A CS CS B LH5116S RAM B CS1 CS2 CS C LH5116S RAM C CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs 69/5-. TA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC126 Micropower Precision Tripe Suppy Monitor.725,.118, 1 Threshods (.75%) LTC156 Micropower Tripe Suppy Monitor for PCI Appications Meets PCI t FAIL Timing Specifications 2 LT 1 RE B PRINTED IN USA Linear Technoogy Corporation 16 McCarthy Bvd., Mipitas, CA (8) 2-19 FAX: (8) LINEAR TECHNOLOGY CORPORATION 21