LT8710 Synchronous SEPIC/ Inverting/Boost Controller with Output Current Control. Applications. Typical Application

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1 Features n Wide Input Range: 4.5V to 8V n Rai-to-Rai Output Current Monitor and Contro n Input Votage Reguation for High Impedance Inputs n C/1 or Power Good Indication Pin n MODE Pin for Forced CCM or Puse-Skipping Operation n Switching Frequency Up to 75kHz n Easiy Configurabe as a Boost, SEPIC, Inverting or Fyback Converter with Singe Feedback Pin n Can Be Synchronized to Externa Cock n High Gain EN/FBIN Pin Accepts Sowy Varying Input Signas n 2-Lead TSSOP Package Appications n High Power Loca Power Suppy n Wide Input Votage Range SEPIC/Inverting n Lead Acid Battery Charger n Automotive Engine Contro Unit (ECU) Power n Soar Pane Power Converter L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents, Incuding Synchronous SEPIC/ Inverting/Boost Controer with Output Current Contro Description The LT 871 is a synchronous PWM DC/DC controer with a rai-to-rai output current monitor and contro. The is idea for many types of power suppy topoogies and can be easiy configured for boost, SEPIC, inverting, or fyback configurations. The s rai-to-rai output current monitor and contro aows the part to be configured in current imited appications such as battery charging. The FLAG pin can be used as a power good indication or C/1 indication aowing for accurate buk and foat battery votages. The s switching frequency range can be set between 1kHz and 75kHz using an externa resistor or synchronized to an externa cock. The aso features innovative EN/FBIN pin circuitry that aows for sowy varying input signas and an adjustabe undervotage ockout function. The pin is aso used for input votage reguation to avoid coapsing a high impedance input suppy. Additiona features such as frequency fodback and soft-start are integrated. The is avaiabe in a 2-ead TSSOP package. Typica Appication 3kHz Inverter Generates 5V from a 4.5V to 25V Input Efficiency and Power Loss 4.5V TO 25V 12µF 1µF 4 2.2µH 13.3k 1k 2.2µF 118k 1µF 2 499Ω 2.2µH 1.5m.47µF 4m BG CSN CSP TG ISN ISP EN/FBIN BIAS INTV CC 6.4k 2.2µF MODE INTV EE INTV CC FBX RT FLAG V C SYNC GND IMON SS 1pF 11.5k 47nF 22nF 3.3nF 1µF 2 5V 7A 33µF EFFICIENCY (%) = 5V = 12V LOAD CURRENT (A) 871 TA1b POWER LOSS (W) 871 TA1a 1

2 Absoute Maximum Ratings (Note 1) Votage....3V to 8V BIAS Votage....3V to 8V EN/FBIN Votage....3V to 8V BG Votage...Note 5 TG Votage...Note 5 RT Votage....3V to 5V SS Votage....3V to 3V FBX Votage...5V FBX Current...1mA V C Votage....3V to 2V SYNC Votage....3V to 5.5V FLAG Votage....3V to 7V FLAG Current... ±1mA MODE Votage....3V to 4V INTV CC Votage....3V to 7V INTV EE Votage...Note 5 CSP Votage....3V to 2V CSN Votage....3V to 2V ISP Votage... ISN.4V to ISN 2V ISN Votage....3V to 8V IMON Votage....3V to 2.5V Operating Junction Temperature Range E... 4 C to 125 C I... 4 C to 125 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec)...3 C Pin Configuration TOP VIEW FBX 1 2 GND V C 2 19 SYNC SS 3 18 RT FLAG 4 17 MODE IMON ISN GND EN/FBIN CSP ISP 7 14 CSN BIAS 8 13 INTV EE 9 12 INTV CC TG 1 11 BG FE PACKAGE 2-LEAD PLASTIC TSSOP T JMAX = 125 C, θ JA = 38 C/W, θ JC = 1 C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE EFE#PBF EFE#TRPBF FE 2-Lead Pastic TSSOP 4 C to 125 C IFE#PBF IFE#TRPBF FE 2-Lead Pastic TSSOP 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2

3 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications for each channe are at T A = 25 C. = 12V, V EN/FBIN = 12V, V BIAS = 12V, uness otherwise noted (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Input Votage Quiescent Current, I VIN OR V BIAS if V BIAS 4.5V V BIAS = V ISN = 7.5V, Not Switching V BIAS = 6.3V, TVEE = V ISN = V, Not Switching V V Quiescent Current in Shutdown V EN/FBIN = V 1 µa EN/FBIN Active Mode EN/FBIN Rising V EN/FBIN Chip Enabe EN/FBIN Rising EN/FBIN Faing V V EN/FBIN Chip Enabe Hysteresis 44 mv EN/FBIN Input Votage Low Shutdown Mode.3 V EN/FBIN Pin Bias Current V EN/FBIN = 3V V EN/FBIN = 1.7V V EN/FBIN = 1.6V V EN/FBIN = V SS Charge Current V SS = V, Current Fows Out of SS Pin µa SS Low Detection Votage Part Exiting Undervotage Lockout mv SS Hi Detection Votage SS Rising SS Faing V V SS Hi Detection Hysteresis 1 mv Low Dropout Reguators, INTV CC and INTV EE INTV CC Votage I INTVCC = 1mA V INTV CC Undervotage Lockout INTV CC Rising INTV CC Faing INTV CC Undervotage Lockout Hysteresis 27 mv INTV CC Dropout Votage INTV CC, = 6V, V BIAS = V, I INTVCC = 1mA 255 mv V BIAS TVCC, = V, V BIAS = 6V, I INTVCC = 1mA 28 mv INTV CC Load Reguation INTV CC Line Reguation = 12V, V BIAS = V, I INTVCC = ma to 8mA = V, V BIAS = 12V, I INTVCC = ma to 4mA 1V 8V, V BIAS = V, I INTVCC = 1mA 1V V BIAS 8V, = V, I INTVCC = 1mA INTV CC Maximum Externa Load Current 5 ma INTV EE Votage, V BIAS TVEE I INTVEE = 1mA V INTV EE Undervotage Lockout, V BIAS TVEE V BIAS TVEE Rising V BIAS TVEE Faing INTV EE Undervotage Lockout 2 mv Hysteresis, V BIAS TVEE INTV EE Dropout Votage, TVEE V BIAS = 6V, I INTVEE = 1mA.75 V Contro Loops (Refer to Bock Diagram to Locate Ampifiers) Current Limit Votage, V CSP V CSN V FBX = 1.1V, Minimum Duty Cyce V FBX = 1.1V, Maximum Duty Cyce V FBX = 1.4V, MODE = V, Minimum Duty Cyce V FBX = 1.4V, MODE = V, Maximum Duty Cyce FBX Positive Output Reguation Votage, EA1 FBX Negative Output Reguation Votage, EA ma ma µa µa µa µa V V % % %/V %/V V V mv mv mv mv V mv 3

4 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications for each channe are at T A = 25 C. = 12V, V EN/FBIN = 12V, V BIAS = 12V, uness otherwise noted (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Positive FBX Pin Bias Current V FBX = Positive FBX Reg Votage, Current into Pin µa Negative FBX Pin Bias Current V FBX = Negative FBX Reg Votage, Current Out of Pin µa FBX Amp Transconductance, EA1 or EA2 ΔI = 2μA 2 µmhos FBX Amp Votage Gain, EA1 or EA2 7 V/V FBX Line Reguation 4.5V 8V, V BIAS = V %/V Output Current Sense Reguation Votage, V ISP V ISN IMON Reguation Votage, EA3 Output Current Sense Amp Transconductance, A6 Output Current Sense Amp Votage Gain, A6 Output Current Sense Amp Input Dynamic Range, A6 V ISN = 8V, V FBX = 1V V ISN = 12V, V FBX = 1V V ISN = V, V FBX = 1V V ISN = 12V, V FBX = 1V, INTV EE in UVLO and V SS > 1.8V V FBX = 1V V FBX = 1V, INTV EE in UVLO and V SS > 1.8V ΔI = 1μA 1 µmhos Negative Input Range, V ISP V ISN Positive Input Range, V ISP V ISN 5 mv mv mv mv V V 11.9 V/V 51.8 mv mv IMON Amp Transconductance, EA3 ΔI = 2μA, V FBX = 1V 165 µmhos IMON Amp Votage Gain, EA3 V FBX = 1V 65 V/V EN/FBIN Input Reguation Votage, EA4 V FBX = 1V V EN/FBIN Amp Transconductance, EA4 ΔI = 2µA, V FBX = 1V 14 µmhos EN/FBIN Amp Votage Gain, EA4 V FBX = 1V 55 V/V MODE Forced CCM Threshod To Exit Forced CCM Mode, MODE Rising To Enter Forced CCM Mode, MODE Faing V V MODE Forced CCM Threshod Hysteresis 49 mv DCM Comparator Threshod in Puse-Skipping Mode, MODE = 2V DCM Comparator Threshod in Forced CCM, MODE =V V ISN = 8V, To Enter DCM Mode, V ISP V ISN Faing V ISN = 12V, To Enter DCM Mode, V ISP V ISN Faing V ISN = V, To Enter DCM Mode, V ISP V ISN Faing V ISN = 8V, To Enter DCM Mode, V ISP V ISN Faing V ISN = 12V, To Enter DCM Mode, V ISP V ISN Faing V ISN = V, To Enter DCM Mode, V ISP V ISN Faing Osciator Switching Frequency, f OSC R T = 46.4k R T = 357k khz khz Switching Frequency in Fodback Compared to Norma f OSC 1/5 ratio Switching Frequency Range Free-Running or Synchronizing 1 75 khz SYNC High Leve for Sync 1.5 V SYNC Low Leve for Sync.4 V SYNC Cock Puse Duty Cyce V SYNC = V to 3V 2 8 % Recommended Min SYNC Ratio f SYNC /f OSC 3/ mv mv mv mv mv mv 4

5 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications for each channe are at T A = 25 C. = 12V, V EN/FBIN = 12V, V BIAS = 12V, uness otherwise noted (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Drivers, BG and TG BG Rise Time C BG = 33pF (Note 3) 24 ns BG Fa Time C BG = 33pF (Note 3) 21 ns TG Rise Time C TG = 33pF (Note 3) 15 ns TG Fa Time C TG = 33pF (Note 3) 16 ns BG and TG Non-Overap Time TG Rising to BG Rising, C BG = C TG = 33pF (Note 3) BG Faing to TG Faing, C BG = C TG = 33pF (Note 3) BG Minimum On-Time C BG = C TG = 33pF ns BG Minimum Off-Time C BG = C TG = 33pF 1 48 ns TG Minimum On-Time C BG = C TG = 33pF 15 ns TG Minimum Off-Time C BG = C TG = 33pF ns C/1 and Power Good Indicators, FLAG FLAG C/1 Indicator Threshod V ISP V ISN Faing, V FBX = 1.215V V ISP V ISN Rising, V FBX = 1.215V FLAG C/1 Indicator Hysteresis 5 mv FLAG Power Good Threshod for Positive FBX Votage FLAG Power Good Threshod for Negative FBX Votage FLAG Power Good Hysteresis for Positive or Negative FBX Votage FLAG Anti-Gitch V FBX Rising, V ISP V ISN = V V FBX Faing, V ISP V ISN = V V FBX Faing, V ISP V ISN = V V FBX Rising, V ISP V ISN = V ns ns mv mv V V mv mv 58 mv Deay from C/1 or Power Good Threshod Trip to FLAG Togge 1 µs FLAG Output Votage Low 1µA into FLAG Pin 9 5 mv FLAG Leakage Current V FLAG = 7V, FLAG Off.1 1 µa Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The E is guaranteed to meet performance specifications from C to 125 C junction temperature. Specifications over the 4 C to 125 C operating temperature range are assured by design, characterization and correation with statistica process contros. The I is guaranteed over the fu 4 C to 125 C operating junction temperature range. Note 3: Rise and fa times are measured using 1% and 9% eves. Deay times are measured using 5% eves. Note 4: This IC incudes overtemperature protection that is intended to protect the device during momentary overoad conditions. Junction temperature wi exceed 125 C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reiabiity. Note 5: Do not appy a positive or negative votage or current source to the BG, TG, and INTV EE pins, otherwise permanent damage may occur. 5

6 Typica Performance Characteristics T A = 25 C, uness otherwise noted. MAX POSITIVE CSP-CSN (mv) Max Current Limit vs Duty Cyce (CSP - CSN) f OSC = 3kHz MAX NEGATIVE CSP-CSN (mv) MAX POSITIVE CSP-CSN (mv) Max Current Limit vs Temperature at Min DC (CSP - CSN) MAX NEGATIVE CSP-CSN (mv) CSP-CSN (mv) Max Current Limit vs SS (CSP - CSN) DUTY CYCLE (%) 871 G TEMPERATURE ( C) 871 G SS (V) 871 G3 POSITIVE FBX VOLTAGE (V) Positive and Negative Output Votage Reguation (FBX) TEMPERATURE ( C) G4 NEGATIVE FBX VOLTAGE (mv) POSITIVE FBX CURRENT INTO PIN (µa) Positive and Negative FBX Current at Output Votage Reguation TEMPERATURE ( C) 871 G NEGATIVE FBX CURRENT OUT OF PIN (µa) EN/FBIN VOLTAGE (V) Input Votage Reguation (EN/FBIN) TEMPERATURE ( C) 871 G6 2. Input Votage Reguation vs FBX (EN/FBIN) 57.5 Output Current Sense Reguation Votage (ISP-ISN and IMON) Output Current Sense Reguation Votage vs FBX (ISP-ISN and IMON) 1.3 EN/FBIN (V) AVERAGE ISP-ISN (mv) IMON AVE ISP-ISN IMON (V) AVERAGE ISP-ISN (mv) IMON AVE ISP-ISN IMON (V) FBX (V) 871 G TEMPERATURE ( C) 871 G FBX (V) 871 G9 6

7 Typica Performance Characteristics T A = 25 C, uness otherwise noted. DCM Threshods (ISP-ISN) Power Good Threshods (FBX) C/1 Threshods (ISP-ISN) ISP-ISN (mv) MODE = V, FCM MODE = 2V, DCM ISP-ISN (mv) POSITIVE FBX (V) RISING FALLING NEGATIVE FBX (V) AVERAGE ISP-ISN (mv) FALLING RISING TEMPERATURE ( C) 871 G TEMPERATURE ( C) 871 G TEMPERATURE ( C) 871 G12 MODE (V) MODE Forced CCM Threshods RISING, EXIT FCM FALLING, ENTER FCM TEMPERATURE ( C) 871 G13 EN/FBIN CHIP ENABLE (V) EN/FBIN Chip Enabe and Active Mode Threshods RISING ONLY RISING FALLING TEMPERATURE ( C) 871 G EN/FBIN ACTIVE MODE (V) EN/FBIN PIN CURRENT (µa) EN/FBIN Pin Current 4 C 25 C 125 C EN/FBIN VOLTAGE (V) G15 fosc (khz) Osciator Frequency vs Temperature 5 R T = 46.4kΩ R T = 357kΩ TEMPERATURE ( C) 871 G16 NORMALIZED OSCILLATOR FREQUENCY (F SW /F NOM ) 1 1/2 1/3 1/4 1/5 Osciator Frequency During Soft-Start INVERTING CONFIGURATIONS NONINVERTING CONFIGURATIONS FBX VOLTAGE (V) 871 G17 TRANSITION TIME (ns) BG and TG Transition Time BG RISING BG FALLING TG RISING TG FALLING CAP LOAD (nf) 871 G18 7

8 Typica Performance Characteristics T A = 25 C, uness otherwise noted. OR V BIAS (V) 4.27 Minimum Operating Input Votage INTV CC vs Temperature INTV CC UVLO vs Temperature TEMPERATURE ( C) INTV CC (V) I INTVCC = 1mA TEMPERATURE ( C) RISING FALLING TEMPERATURE ( C) 871 G G2 871 G21 INTV CC (V) INTV CC CURRENT LIMIT (ma) INTV CC Current Limit vs or BIAS BIAS OR BIAS INTV CC > 3.5V INTV CC > 3.5V INTV CC < 3.5V INPUT - INTV CC (V) INTV CC Dropout from or BIAS BIAS BIAS - INTV EE (V) INTV EE vs Temperature 6.28 I INTVEE = 1mA INPUT VOLTAGE (V) 871 G INTV CC LOAD CURRENT (ma) 871 G TEMPERATURE ( C) 871 G24 BIAS - INTV EE (V) INTV EE UVLO vs Temperature INTV EE Current Limit vs BIAS INTV EE Dropout (BIAS = 6V) RISING FALLING INTV EE CURRENT LIMIT (ma) BIAS - INTV EE = 5V INTV EE (V) C 25 C 125 C TEMPERATURE ( C) 871 G BIAS (V) 871 G INTV EE LOAD CURRENT (ma) 871 G27 8

9 Pin Functions FBX (Pin 1): Positive and Negative Feedback Pin. For a boost, SEPIC, or inverting converter, tie a resistor from the FBX pin to according to the foowing equations: R FBX = 1.213V 83.7µA ; Boost or SEPIC Converter R FBX = 9.6mV 83.1µA ; Inverting Converter V C (Pin 2): Error Ampifier Output Pin. Tie externa compensation network to this pin. SS (Pin 3): Soft-Start Pin. Pace a soft-start capacitor here that is greater than 5x the IMON capacitor. Upon start-up, the SS pin wi be charged by a (nominay) 26k resistor to ~2.7V. During a current overoad as seen by ISP - ISN, overtemperature, or UVLO condition, the SS pin wi be quicky discharged to reset the part. Once those conditions are cear, the part wi attempt to restart. FLAG (Pin 4): Power Good or C/1 Indication Pin. The FLAG pin functions as an active high power good pin if C/1 is true. Aternativey, the FLAG pin functions as an active high C/1 indication pin if power is good. Power is good when FBX < 68.5mV or FBX > 1.153V and has 58mV of hysteresis. When FBX = 1.153V, it s 5% beow reguation which corresponds to ~1% beow reguation on (for > 8V). Active high C/1 indication is when the charge current seen by the ISP and ISN pins is ess than 1% of fu current (V ISP V ISN < 5mV) as the charge current decreases. For increasing charge currents, the C/1 threshod has to reach 2% of fu current (V ISP V ISN > 1mV). The C/1 indication can be used to set the buk and foat votage when charging a battery. For either C/1 or power good indicators, there is a 1µs anti-gitch deay. A pu-up resistor or some other form of pu-up network needs to exist on this pin to use these features. See the Bock Diagram and Appications section for more information. IMON (Pin 5): Output Current Sense Monitor Output Pin. Outputs a votage that is proportiona to the votage seen across the ISP and ISN pins. V IMON = 11.9 (V ISP ISN 51.8mV) Since the votage across the ISP and ISN pins is AC, a fitering capacitor is needed on the IMON pin to average out the ISP and ISN votage. Recommended capacitor vaue is 1nF to 1nF. A 51.8mV offset is added to the ampifier, so when the average ISP ISN votage is V, the IMON votage is 616mV. When the average votage across the ISP and ISN pins is 5mV, the IMON pin wi output 1.213V. Do not resistivey oad down this pin. ISN, ISP (Pins 6, 7): Output Current Sense Negative and Positive Input Pins Respectivey. Kevin connect ISN and ISP pins to a sense resistor to imit the output current. The commanded NFET current wi imit the votage difference across the sense resistor to 5mV. BIAS (Pin 8): Aternate Input Suppy and PFET Bias Pin. Must be ocay bypassed. The BIAS pin sets the top rai for the TG gate driver. Must connect to the converter s for a positive output votage or INTV CC for a converter s negative output votage. INTV EE (Pin 9): 6.18V-Beow-BIAS Reguator Pin. Must be ocay bypassed with a minimum capacitance of 2.2µF to BIAS. This pin sets the bottom rai for the TG gate driver. The TG gate driver can begin switching when BIAS INTV EE exceeds 3.42V (typica). Connect pin to ground for an inverting converter. TG (Pin 1): PFET Gate Drive Pin. Low and high eves are BIAS INTV EE and BIAS respectivey. BG (Pin 11): NFET Gate Drive Pin. Low and high eves are GND and INTV CC respectivey. INTV CC (Pin 12): 6.3V Dua Input LDO Reguator Pin. Must be ocay bypassed with a minimum capacitance of 2.2µF to GND. Logic wi choose to run INTV CC from the or BIAS pins. A maximum 5mA externa oad can connect to the INTV CC pin. The undervotage ockout on INTV CC is 4V (typica). The BG gate driver can begin switching when INTV CC exceeds 4V (typica). (Pin 13): Input Suppy Pin. Must be ocay bypassed. Can run down to V as ong as BIAS > 4.5V. CSN, CSP (Pins 14, 15): NFET Current Sense Negative and Positive Input Pins Respectivey. Kevin connect these pins to a sense resistor to imit the NFET switch current. The maximum sense votage at ow duty cyce is 5mV. EN/FBIN (Pin 16): Enabe and Input Votage Reguation Pin. In conjunction with the UVLO (undervotage ockout) circuit, this pin is used to enabe/disabe the chip and restart the soft-start sequence. The EN/FBIN pin is aso 9

10 Pin Functions used to imit the NFET current to avoid coapsing the input suppy. Drive beow.3v to disabe the chip with very ow quiescent current. Drive above 1.7V (typica) to activate the chip and restart the soft-start sequence. The commanded NFET current wi adjust when the EN/FBIN pin votage drops between 1.55V and 1.662V. See the Bock Diagram and Appications section for more information. Do not foat this pin. MODE (Pin 17): Forced CCM Mode Pin. Drive beow 1.175V (typica) to operate in forced CCM. Drive above 1.224V (typica) to operate in DCM and/or puse-skipping mode at ight oads. If SS < 1.8V (typica) or INTV EE is in UVLO, the part wi operate in DCM at ight oad. RT (Pin 18): Timing Resistor Pin. Adjusts the s switching frequency. Pace a resistor from this pin to ground to set the frequency to a fixed free-running eve. Do not foat this pin. SYNC (Pin 19): To synchronize the switching frequency to an outside cock, simpy drive this pin with a cock. The high votage eve of the cock must exceed 1.5V, and the ow eve must be ess than.4v. Drive this pin to ess than.4v to revert to the interna free running cock. See the Appications Information section for more information. GND (Pin 2, Exposed Pad Pin 21): Ground. Must be sodered directy to oca ground pane. Bock Diagram L1 C1 L2 C IN MN R1 D1 MP C OUT R SENSE1 C2 R SENSE2 R FBX CSP CSN BG INTV CC BIAS TG BIAS INTV CC LDO LOGIC BIAS DRIVER LEVEL SHIFT DRIVER LDO C VEE LDO A5 SR1 Q R S TG DRIVER DISABLE DCM_EN ISP ISN DCM_EN UVLO BIAS 6.18V INTV EE FLAG 6.3V C VCC INTV CC UVLO 1.213V REFERENCE IMON A7 IMON 666.5mV CHRG PG 1µs ANTI-GLITCH 1.153V 1.38V R IN1 R IN2 EN/FBIN MODE 1.224V 1.8V 51.5k EN/FBIN LOGIC 1.3V 1.7V DCM_EN DIE TEMP 175 C N SLOPE COMPENSATION ADJUSTABLE OSCILLATOR EA1 FBX SS 2.7V 5mV START-UP AND RESET LOGIC SYNC BLOCK SS SOFT-START EA V 14.5k 68.5mV 26k 14.5k C SS GND FBX DCM_EN DRIVER DISABLE FREQUENCY FOLDBACK SYNC RT EN/FBIN 1.67V EA4 V C EA V IMON A6 11.9k 51.8mV ISN ISP R C 871 BD R T C C C F C IMON 1 Figure 1. Bock Diagram

11 STATE Diagram EN/FBIN < 1.3V (TYP) OR AND BIAS < 4.5V (MAX) 1.3V < EN/FBIN < 1.7V (TYP) AND OR BIAS > 4.5V CHIP OFF ALL SWITCHES DISABLED INITIALIZE SS PULLED LOW INTV CC CHARGES UP RESET EN/FBIN > 1.7V AND OR BIAS > 4.5V AND INTV CC > 4V (TYP) ACTIVE MODE SS SLOWLY CHARGES UP V C PULLED LOW RESET RESET DETECTED BEGIN SWITCHING NFET BEGINS SWITCHING PFET STARTS SWITCHING WHEN INTV EE REGULATOR IS OUT OF UVLO RESET SS DISCHARGES QUICKLY SWITCHER DISABLED SS < 5mV MODE < 1.175V (TYP) AND SS > 1.8V (TYP) FORCED CCM OPERATION MODE > 1.224V (TYP) DCM AT LIGHT LOAD REGULATION RESET OVER NO RESET CONDITIONS DETECTED RESET BG AND TG SWITCH AT CONSTANT FREQUENCY INDUCTOR CURRENT CAN REVERSE IF ISP-ISN VOLTAGE GOES BELOW 3mV (TYP), PFET TURNS OFF SO INDUCTOR CURRENT GOES MORE POSITIVE PFET TURNS OFF FOR REMAINDER OF CYCLE IF ISP-ISN VOLTAGE FALLS BELOW 2.8mV (TYP) FOR VERY LIGHT LOAD, PART MAY SKIP PULSES V C COMMANDS PEAK INDUCTOR CURRENT TO MAINTAIN REGULATION INTV EE REGULATOR IN UVLO AND SS > 1.8V (TYP) OUTPUT CURRENT FOLDBACK RESET OUTPUT CURRENT LIMITED TO 25mV (TYP) AVERAGE ACROSS THE ISP-ISN PINS RESET 871 SD REGULATION = OUTPUT VOLTAGE (FBX) INPUT VOLTAGE (EN/FBIN) OUTPUT CURRENT (ISP-ISN AND IMON) RESET = UVLO ON OR BIAS ( < 4.5V (MAX)) UVLO ON INTV CC ( < 4V (TYP)) EN/FBIN < 1.7V (TYP) AT 1ST POWER-UP EN/FBIN < 1.26V (TYP) AFTER ACTIVE MODE SET OVERCURRENT (ISP ISN > 63.6mV AVERAGE (TYP)) OVERTEMPERATURE (T J > 175 C (TYP)) Figure 2. State Diagram 11

12 Operation OPERATION OVERVIEW The uses a constant frequency, current mode contro scheme to provide exceent ine and oad reguation. The part s undervotage ockout (UVLO) function, together with soft-start and frequency fodback, offers a controed means of starting up. Output votage, output current, and input votage have contro over the commanded peak current which aows a wide range of appications to be buit using the. Synchronous switching makes high efficiency and high output current appications possibe. When operating at ight currents with the MODE pin > 1.224V (typica), the wi disabe synchronous operation for part of the cyce to prevent negative switch currents. Refer to the Bock Diagram (Figure 1) and the State Diagram (Figure 2) for the foowing description of the part s operation. OPERATION START-UP Severa functions are provided to enabe a very cean start-up of the. Precise Turn-On Votages The EN/FBIN pin has two votage eves for activating the part; one that enabes the part and aows interna rais to operate and a 2nd votage threshod which activates a soft-start cyce and switching can begin. To enabe the part, take the EN/FBIN pin above 1.3V (typica). This comparator has 44mV of hysteresis to protect against gitches and sow ramping. To activate a soft-start cyce and aow switching, take EN/FBIN above 1.7V (typica). When EN/ FBIN exceeds 1.7V (typica), the ogic state is atched so that if EN/FBIN drops between 1.3V to 1.7V (typica), the SS pin is not pued ow by the EN/FBIN pin. The EN/FBIN pin is aso used for input votage reguation which is at 1.67V (typica). Input votage reguation is expained in more detai in the Operation Reguation section. Taking the EN/FBIN pin beow.3v shuts down the chip, resuting in extremey ow quiescent current. See Figure 3 that iustrates the different EN/FBIN votage threshods. EN/FBIN (V) 1.76V 1.64V 1.662V 1.55V 1.38V 1.18V.3V V Figure 3. EN/FBIN Modes of Operation Undervotage Lockout (UVLO) ACTIVE MODE (NORMAL OPERATION) (MODE LATCHED UNTIL EN/FBIN DROPS BELOW CHIP ENABLE TRESHOLD) ACTIVE MODE THRESHOLD (TOLERANCE) NORMAL OPERATION IF ACTIVE MODE SET INPUT VOLTAGE REGULATION (ONLY IF ACTIVE MODE SET) SWITCH OFF, INTV CC AND INTV EE ENABLED, SS CAP DISCHARGED IF ACTIVE MODE NOT SET CHIP ENABLE THRESHOLD (HYSTERSIS AND TOLERANCE) LOCKOUT (SWITCH OFF, SS CAP DISCHARGED, INTV CC AND INTV EE DISABLED) SHUTDOWN (LOW QUIESCENT CURRENT) 871 F3 The has interna UVLO circuitry that disabes the chip when the greater of or BIAS < 4.5V (maximum) or INTV CC < 4V (typica). The EN/FBIN pin can aso be used to create a configurabe UVLO. See the Appications section for more information. Soft-Start of Switch Current The soft-start circuitry provides for a gradua ramp-up of the switch current (refer to Max Current Limit vs SS in Typica Performance Characteristics). When the part is brought out of shutdown, the externa SS capacitor is first discharged which resets the states of the ogic circuits in the chip. Once INTV CC comes out of UVLO (> 4V typica) and the chip is in active mode, an integrated 26k resistor pus the SS pin to ~2.7V at a ramp rate set by the externa capacitor connected to the pin. Typica vaues for the soft-start capacitor range from 1nF to 1µF. The soft-start capacitor shoud aso be at east 5x greater than the externa capacitor connected to the IMON pin to avoid start-up issues. 12

13 Operation Frequency Fodback The frequency fodback circuitry reduces the switching frequency when 175mV < FBX < 1.1V (typica). This feature owers the minimum duty cyce that the part can achieve, thus aowing better contro of the inductor current at start-up. When the FBX votage is pued outside of this range, the switching frequency returns to norma. If the part is configured to be in forced continuous conduction mode (MODE pin is driven beow 1.175V), then the frequency fodback circuitry is disabed as ong as INTV EE is not in UVLO and the SS pin is higher than the SS Hi threshod. Note that the peak inductor current at start-up is a function of many variabes incuding oad profie, output capacitance, target,, switching frequency, etc. mode of reguation wi be described independenty so that ony one of the modes of reguation is in command of the. Output Votage Reguation A singe externa resistor is used to set the target output votage. See the Pin Functions section for seecting the feedback resistor for a desired output votage. The V C pin votage (negative input of A7) is set by EA1 (or EA2), which is simpy an ampified difference between the FBX pin votage and the reference votage (1.213V if the is configured as a noninverting converter or 9.6mV if configured as an inverting converter). In this manner, the FBX error ampifier sets the correct peak current eve to maintain output votage reguation. OPERATION REGULATION Use the Bock Diagram when stepping through the foowing description of the operating in reguation. Aso, assume the converter s oad current is high enough such that the part is operating in synchronous switching. The has three modes of reguation: 1. Output Votage (via FBX pin) 2. Input Votage (via EN/FBIN pin) 3. Output Current (via ISP, ISN, and IMON pins) A three of these reguation oops contro the peak commanded current through the externa NFET, MN. This operation is the same regardess of the reguation mode, so that wi be described first. At the start of each osciator cyce, the SR atch (SR1) is set, which first turns off the externa PFET, MP, and then turns on the externa NFET, MN. The NFET s source current fows through an externa current sense resistor (R SENSE1 ) generating a votage proportiona to the NFET switch current. This votage is then ampified by A5 and added to a stabiizing ramp. The resuting sum is fed into the positive termina of the PWM comparator A7. When the votage on the positive input of A7 exceeds the votage on the negative input (V C pin), the SR atch is reset, turning off the NFET and then turning on the PFET. The votage on the V C pin is controed by one of the reguation oops, or a combination of reguation oops. For simpicity, each Input Votage Reguation A singe resistor or resistor divider from the EN/FBIN pin to the converter s input votage sets the input votage reguation. It is recommended to use a resistor divider for improved accuracy as described in the Setting the Input Votage Reguation or Undervotage Lockout section. The EN/FBIN pin votage connects to the positive input of ampifier EA4. The V C pin votage is set by EA4, which is simpy an ampified difference between the EN/FBIN pin votage and a 1.67V reference votage. In this manner, the EN/FBIN error ampifier sets the correct peak current eve to maintain input votage reguation. Output Current Reguation An externa sense resistor connected between the ISP and ISN pins (R SENSE2 ) sets the maximum output current of the converter when paced in the source of the PFET, MP. A buit-in 51.8mV offset is added to the votage seen across R SENSE2. That votage is then ampified and outputs to the IMON pin. An externa capacitor must be paced from IMON to ground to fiter the ampified chopped votage that s sensed across R SENSE2. The votage at the IMON pin is fed to the negative input of the IMON error ampifier, EA3. The V C pin votage is set by EA3, which is simpy an ampified difference between the IMON pin votage and the 1.213V reference votage. In this manner, the IMON error ampifier sets the correct peak current eve to maintain output current reguation. 13

14 Operation Note that if the INTV EE LDO is in UVLO and SS > 1.8V (typica), then the votage reference at the positive input of EA3 is 916mV (typica), resuting in imiting the output current to about haf of its set imit. OPERATION RESET CONDITIONS The has three reset cases. When the part is in reset, the SS pin is pued ow and both power switches, MN and MP, are forced off. Once a of the reset conditions are gone, the part is aowed to begin a soft-start sequence and switching can commence. Each of the foowing events can cause the to be in reset: 1. UVLO a. The greater of and BIAS is < 4.5V (maximum) b. INTV CC < 4V (typica) c. EN/FBIN < 1.7V (typica) at first power-up 2. Overcurrent sensed by IMON > 1.38V (typica) 3. Die Temperature > 175 C OPERATION POWER SWITCH CONTROL The main power switch is the externa NFET (MN in Bock Diagram) and the synchronous power switch is the externa PFET (MP in Bock Diagram). The two switches are never on at the same time, and there is a non-overap time of ~14ns and ~9ns on the rising and faing edges respectivey (see Eectrica Characteristics) to prevent cross conduction. Figure 4 beow shows the BG and TG (BIASTG) signas: 14ns BG ON 9ns TG ON Light Load Current (MODE Pin) The MODE pin can be used to te the to operate in forced CCM regardess of oad current, or operate in DCM at ight oads. MODE < 1.175V (typica) = Forced CCM or FCM MODE > 1.224V (typica) = DCM or Puse-Skipping The forced continuous mode (FCM) aows the inductor current to reverse directions without any switches being forced off. At very ight oad currents, the inductor current wi swing positive and negative as the appropriate average current is deivered to the output. There are some exceptions that negate the MODE pin and force the part to operate in DCM at ight oads: 1. The INTV EE LDO is in UVLO (BIAS INTV EE < 3.42V typica). 2. SS < 1.8V (typica). 3. The part is in a reset condition. When the is in discontinuous mode (DCM), synchronous switch MP is hed off whenever MP s current fas near current (ess than 2.8mV (typica) across R SENSE2 ). This is to prevent current draw from the output and/or feeding current to the input suppy. Under very ight oads, the current comparator A7, may aso remain tripped for severa cyces (i.e. skipping puses). Since MP is hed off during the skipped puses, the inductor current wi not reverse. OPERATION C/1 AND POWER GOOD (FLAG PIN) The FLAG pin is an open-drain pin that functions as an active high C/1 and power good pin. The FLAG pin changes states 1µs (typica) after the interna comparators te the FLAG pin to change states to reject gitches or transient events. Figure 4. Synchronous Switching 871 F4 14

15 Operation C/1 Indication If power is good, then the FLAG pin wi function as an active high C/1 indication pin. C/1 is when the charging current (output current) has dropped to 1/1 its maximum and is usefu in battery charging appications. The C/1 comparator monitors the votage at the IMON pin, and when the average ISP-ISN votage drops beow 5mV (typica), the FLAG pin pu-down device is turned off, and the FLAG pin votage is aowed to pu high. The FLAG pin wi pu ow again if the average ISP-ISN votage rises above 1mV (typica). The IMON votage corresponding to 5mV and 1mV on ISP ISN is 666.5mV and 727.5mV respectivey. Note that if the is set to operate in FCM (MODE pin ow), then the C/1 comparator is disabed and the FLAG pin operates ony as a power good pin. See the Appications section for more information. Power Good Indication If C/1 is detected (average ISP-ISN < 5mV typica), then the FLAG pin functions as an active high power good (PG) pin. Power is good when the FBX votage is greater than 95% of its reguation target, which corresponds to ~9% of the reguation target (for > ~8V). This corresponds to FBX > 1.153V (typica) for noninverting converters and FBX < 68.5mV (typica) for inverting converters. The PG comparators have 58mV of hysteresis to reject gitches. OPERATION LDO REGULATORS (INTV CC AND INTV EE ) The INTV CC LDO reguates at 6.3V (typica) and is used as the top rai for the BG gate driver. The INTV CC LDO can run from or BIAS and wi inteigenty seect to run from the best for minimizing power oss in the chip, but at the same time, seect the proper input for maintaining INTV CC as cose to 6.3V as possibe. The INTV CC reguator aso has safety features to imit the power dissipation in the interna pass device and aso to prevent it from damage if the pin is shorted to ground. The UVLO threshod on INTV CC is 4V (typica), and the wi be in reset unti the LDO comes out of UVLO. The INTV EE reguator reguates to 6.18V (typica) beow the BIAS pin votage. The BIAS and INTV EE votages are used for the top and bottom rais of the TG gate driver respectivey. Just ike the INTV CC reguator, the INTV EE reguator has a safety feature to imit the power dissipation in the interna pass device. The TG pin can begin switching after the INTV EE reguator comes out of UVLO (3.42V typica across the BIAS and INTV EE pins) and the part is not in a reset condition. 15

16 Appications Information BOOST CONVERTER COMPONENT SELECTION 4.5V TO 9V C IN2 33µF C IN1 22µF 4 L1 1.3µH R IN1 13.3k R IN2 1k 2.2µF R T 88.7k BG SYNC GND Figure 5. Boost Converter The Component Vaues Given are Typica Vaues for a 4kHz, 4.5V to 9V to 12V/6A Boost. The can be configured as a boost converter as in Figure 5. This topoogy generates a positive output votage where the input votage is ower than the output votage. A singe feedback resistor sets the output votage. For a desired output current and output votage over a given input votage range, Tabe 1 is a step-by-step set of equations to cacuate component vaues for the when operating as a boost converter. Refer to more detai in this section and the Appendix for further information on the design equations presented in Tabe 1. Variabe Definitions: (MIN) = Minimum Input Votage (MAX) = Maximum Input Votage = Output Votage I OUT = Output Current of Converter f = Switching Frequency DC MAX = Power Switch Duty Cyce at (MIN) V CSPN = Current Limit Votage at DC MAX 1m EN/FBIN MODE INTV CC RT MN 2 R SENSE1 IMON CSN CSP TG ISP ISN BIAS INTV EE FBX FLAG V C C IMON 47nF SS MP C SS 22nF R SENSE2 5m 2.2µF C F 1pF R FBX 13k R C 18k C OUT1 22µF 4 12V 6A C OUT2 33µF C C 3.3nF 871 F5 Tabe 1. Boost Design Equations Parameters/Equations Step 1: Inputs Pick,, I OUT, and f to cacuate equations beow. Step 2: DC MAX DC MAX 1 (MIN) Step 3: V CSPN Step 4: R SENSE1 Step 5: R SENSE2 Step 6: L Step 7: C OUT Step 8: C IN Step 9: C IMON Step 1: R FBX See Max Current Limit vs Duty Cyce pot in Typica Performance Characteristics to find V CSPN at DC MAX. R SENSE1.58 V CSPN I OUT (1 DC MAX ).5 R SENSE2 1.6 I OUT L TYP = R SENSE1 (MIN) 12.5m f L MIN = R SENSE1 4m f L MAX1 = R SENSE1 (MIN) 5m f L MAX2 = R SENSE1 (MAX) 5m f 1 (MIN) (MIN) 1 (MIN) (1) (2) 1 (MIN) (3) 1 (MAX) (4) Sove equations 1 to 4 for a range of L vaues. The minimum vaue of the L range is the higher of L TYP and L MIN. The maximum of the L vaue range is the ower of L MAX1 and L MAX2. C OUT I OUT DC MAX f.5 DC MAX C IN 8 L f 2.5 C IMON 1µDC MAX.5 f R FBX = 1.213V 83.7µA Step 11: R T R T = 35,88 1; f in khz andr T in kω f NOTE: The fina vaues for C OUT and C IN may deviate from the above equations in order to obtain desired oad transient performance for a particuar appication. The C OUT and C IN equations assume zero ESR, so increase the capacitance accordingy based on the combined ESR. 16

17 Appications Information SEPIC CONVERTER COMPONENT SELECTION COUPLED OR UNCOUPLED INDUCTORS 3V TO 4V(OPERATING) 4.5V TO 4V(START-UP) C IN2 22µF C IN1 1µF 6 R IN1 4.2k R IN2 1k 2.2µF L1 2.9µH R T 178k BG 1.5m EN/FBIN MODE INTV CC RT SYNC MN CSN GND IMON C1 1µF 2 R SENSE1 CSP C IMON 47nF SS MP L2 2.9µH TG ISP ISN BIAS INTV EE FBX FLAG V C C SS 22nF R SENSE2 6m 2.2µF C F 1pF R FBX 45.3k R C 8.87k C C 6.8nF 5V 5A C OUT2 33µF C OUT1 1µF 4 Figure 6. SEPIC Converter The Component Vaues Given Are Typica Vaues for a 2kHz, 3V to 4V to 5V/5A SEPIC Topoogy Using Couped Inductors. The can aso be configured as a SEPIC as in Figure 6. This topoogy generates a positive output votage where the input votage can be ower, equa, or higher than the output votage. Output disconnect is inherenty buit into the SEPIC topoogy, meaning no DC path exists between the input and output due to capacitor C1. For a desired output current and output votage over a given input votage range, Tabe 2 is a step-by-step set of equations to cacuate component vaues for the when operating as a SEPIC converter. Refer to more detai in this section and the Appendix for further information on the design equations presented in Tabe 2. Variabe Definitions: (MIN) = Minimum Input Votage = Output Votage I OUT = Output Current of Converter f = Switching Frequency DC MAX = Power Switch Duty Cyce at (MIN) V CSPN = Current Limit Votage at DC MAX 871 F6 Tabe 2. SEPIC Design Equations Parameters/Equations Step 1: Inputs Pick,, I OUT, and f to cacuate equations beow. Step 2: DC MAX V DC MAX OUT (MIN) Step 3: V CSPN Step 4: R SENSE1 Step 5: R SENSE2 Step 6: L Step 7: C1 Step 8: C OUT Step 9: C IN Step 1: C IMON Step 11: R FBX See Max Current Limit vs Duty Cyce pot in Typica Performance Characteristics to find V CSPN at DC MAX. R SENSE1.58 V CSPN I OUT (1DC MAX ).5 R SENSE2 1.6 I OUT L TYP = R SENSE1 12.5m f L MIN = R SENSE1 4m f L MAX = R SENSE1 5m f (MIN) (MIN) 1 (MIN) 2 (MIN) (MIN) (1) (2) (3) Sove equations 1, 2, and 3 for a range of L vaues. The minimum vaue of the L range is the higher of L TYP and L MIN. The maximum of the L vaue range is L MAX. L = L 1 = L 2 for couped inductors. L = L 1 L 2 for uncouped inductors. C1 1µF ( TYPICAL );V RATING > C OUT I OUT DC MAX f.5 DC MAX C IN 8 L f 2.5 C IMON 1µDC MAX.5 f R FBX = 1.213V 83.7µA Step 12: R T R T = 35,88 1; f in khz andr T in kω f NOTE: The fina vaues for C OUT and C IN may deviate from the above equations in order to obtain desired oad transient performance for a particuar appication. The C OUT and C IN equations assume zero ESR, so increase the capacitance accordingy based on the combined ESR. 17

18 Appications Information DUAL INDUCTOR INVERTING COMPONENT SELECTION COUPLED OR UNCOUPLED INDUCTORS 4.5V TO 25V C IN2 12µF C IN1 1µF 4 R IN1 13.3k R IN2 1k 2.2µF L1 2.2µH R T 118k C1 1µF 2 MP MN R1 499Ω R SENSE1 1.5m D1 R C2 SENSE2.47µF 4m BG CSN CSP TG ISN ISP EN/FBIN BIAS INTV CC 2.2µF INTV EE MODE FBX INTV CC FLAG RT V C SYNC GND IMON C IMON 47nF SS C SS 22nF C C 1pF L2 2.2µH R C 11.5k C C 3.3nF Figure 7. Dua Inductor Inverting Converter The Component Vaues Given Are Typica Vaues for a 3kHz, 4.5V to 25V to 5V/7A Inverting Topoogy Using Couped Inductors. Due to its unique FBX pin, the can work in a dua inductor inverting configuration as in Figure 7. Changing the connections of L2 and the PFET in the SEPIC topoogy, resuts in generating negative output votages. This soution resuts in very ow output votage rippe due to inductor L2 in series with the output. Output disconnect is inherenty buit into this topoogy due to the capacitor C1. For a desired output current and output votage over a given input votage range, Tabe 3 is a step-by-step set of equations to cacuate component vaues for the when operating as a dua inductor inverting converter. Refer to more detai in this section and the Appendix for further information on the design equations presented in Tabe 3. Variabe Definitions: (MIN) = Minimum Input Votage (MAX) = Maximum Input Votage = Output Votage I OUT = Output Current of Converter f = Switching Frequency DC MAX = Power Switch Duty Cyce at (MIN) V CSPN = Current Limit Votage at DC MAX R FBX 6.4k 5V 7A C OUT2 33µF C OUT1 1µF F7 Tabe 3. Dua Inductor Inverting Design Equations Parameters/Equations Step 1: Inputs Pick,, I OUT, and f to cacuate equations beow. Step 2: DC MAX V DC MAX OUT (MIN) Step 3: V CSPN Step 4: R SENSE1 Step 5: R SENSE2 Step 6: L Step 7: C1 See Max Current Limit vs Duty Cyce pot in Typica Performance Characteristics to find V CSPN at DC MAX. R SENSE1.58 V CSPN I OUT.5 R SENSE2 1.6 I OUT L TYP = R SENSE1 12.5m f L MIN = R SENSE1 4m f L MAX = R SENSE1 5m f (1DC MAX (MIN) (MIN) 1 (MIN) 2 (MIN) (MIN) (1) (2) (3) Sove equations 1, 2, and 3 for a range of L vaues. The minimum vaue of the L range is the higher of L TYP and L MIN. The maximum of the L vaue range is L MAX. L = L 1 = L 2 for couped inductors. L = L 1 L 2 for uncouped inductors. C1 1µF ( TYPICAL );V RATING > Step 8: C OUT C 1 OUT 8 f 2.5 (MAX) (MAX) Step 9: C IN Step 1: C IMON Step 11: R FBX DC MAX C IN 8 L f 2.5 C IMON 1µDC MAX.5 f R FBX = 9. 6mV 83.1µA Step 12: R T R T = 35,88 1; f in khz andr T in kω f NOTE: The fina vaues for C OUT and C IN may deviate from the above equations in order to obtain desired oad transient performance for a particuar appication. The C OUT and C IN equations assume zero ESR, so increase the capacitance accordingy based on the combined ESR. 18

19 Appications Information SETTING THE OUTPUT VOLTAGE REGULATION The output votage is set by connecting an externa resistor (R FBX ) from the converter s output,, to the FBX pin. The equations beow determines R FBX : R FBX = 1.213V ; Boost or SEPIC Converter 83.7µA R FBX = 9.6mV ; Inverting Converter 83.1µA See the Eectrica Characteristics for toerances on the FBX reguation votage and current. SETTING THE INPUT VOLTAGE REGULATION OR UNDERVOLTAGE LOCKOUT By connecting a resistor divider between, EN/FBIN, and GND, the EN/FBIN pin provides a mean to reguate the input votage or to create an undervotage ockout function. Referring to error ampifier EA4 in the bock diagram, when EN/FBIN is ower than the 1.67V reference, V C is pued ow. For exampe, if is provided by a reativey high impedance source (e.g. a soar pane) and the current draw pus beow a preset imit, V C wi be reduced, thus reducing current draw from the input suppy and imiting the input votage drop. Note that using this function in forced continuous mode (MODE pin ow) can resut in current being drawn from the output and forced into the input. If this behavior is not desired then set the MODE pin high to prevent reverse current fow. To set the minimum or reguated input votage use: (MINREG) = 1.67V 1 R IN1 17.6µA R IN1 R IN1 = (MINREG) 1.67V 1.67V R IN2 17.6µA R IN2 where R IN1 and R IN2 are shown in Figure 8. For increased accuracy, set R IN2 1k. The resistor R IN2 is optiona, but it is recommended to be used to increase the accuracy of the input votage reguation by making the R IN1 current much higher than the EN/FBIN pin current. R IN1 R IN2 (OPTIONAL) EN/FBIN GND 17.6µA AT 1.67V 51.5k 1.67V 1.7V 1.3V EA4 EN/FBN LOGIC Figure 8. Configurabe UVLO ACTIVE MODE CHIP ENABLE V C 871 F8 This same technique can be used to create an undervotage ockout if the is NOT in forced continuous mode. When in discontinuous mode, forcing V C ow wi stop a switching activity. Note that this does not reset the soft start function, therefore resumption of switching activity wi not be accompanied by a soft-start. Note that for very ow input impedance suppies, a capacitor from EN/FBIN to ground may be needed to prevent osciations from the input votage reguation contro oop. At start-up, the minimum votage on EN/FBIN must exceed 1.7V (typica) to begin a soft-start cyce. Afterwards, the EN/FBIN votage can drop beow 1.7V and the input can be reguated such that the EN/FBIN votage is at ~1.67V. So the equation beow gives the start-up for a desired input reguation votage: (START-UP) = 1.7V 1.67V (MIN REG).78µA R IN1 OUTPUT CURRENT MONITORING AND LIMITING (R SENSE2 AND ISP-ISN AND IMON Pins) The has an output current monitor circuit that can be used to monitor and/or imit the output current. The current monitor circuit works as shown in Figure 9. If it is not desirabe to monitor and imit the output current, simpy connect the IMON pin to ground. Note that the current sense resistor connected to the ISP and ISN pins must sti be used, and the vaue shoud foow the guideines in the next coupe sections. 19

20 Appications Information MP TG 51.8mV R SENSE2 ISP 1mA/V A7 ISN TO SYSTEM votage. Assume the current through R SENSE2 is steady state and that its time average current is approximatey equa to the converter s oad current: V IMON =11.9 ( I RSENSE2(AVE) R SENSE2 51.8mV ) I OUT I RSENSE2(AVE) = V IMON mV R SENSE2 OVER CURRENT CHRG 1.38V 666.5mV 1.213V 11.9K GND EA3 IMON C IMON V C Output Current Limiting As shown in Figure 9, IMON votages exceeding 1.213V (typica) causes the V C votage to reduce, thus imiting the inductor current. This votage on IMON corresponds to an average votage of 5mV across R SENSE2. Beow is the equation for seecting the R SENSE2 resistor for imiting the output current at steady state: Figure 9. Output Current Monitor and Contro 871 F9 R SENSE2 = 5mV I OUT(LIMIT) The current through R SENSE2 is sensing the current through MP which is turning on and off every cock cyce. Since the current through R SENSE2 is chopped, a fiter capacitor connected from the IMON pin to ground is needed to fiter the votage at the IMON pin before heading to EA3. Beow is the equation to cacuate the required IMON pin capacitor: C IMON 1µA DC MAX 5mV f where DC MAX is the maximum duty cyce of the converter s appication ( at the owest of its input range) and f is the switching frequency. To prevent start-up issues, the IMON capacitor shoud charge up faster than the SS capacitor. It is recommended to size the SS capacitor at east 5x greater than the IMON capacitor. Output Current Monitoring The votage at the IMON pin is a gained up version of the votage seen across the ISP and ISN pins. Beow are the equations reating the R SENSE2 current to the IMON pin If it is not desirabe to imit the output current, size R SENSE2 by setting I OUT(LIMIT) at east 6% higher than the maximum output current of the converter. This current sense resistor is needed if using the synchronous PFET in the converter. If the PFET is repaced with a Schottky, then R SENSE2 is not needed if output current imiting or monitoring isn t required. Note that if the INTV EE LDO is in UVLO and SS > 1.8V (typica), then the reference votage at EA3 reduces to 916mV, and the output current is imited to about haf its set point. Output Overcurrent As shown in Figure 9, a comparator monitors the votage at the IMON pin and triggers a reset condition if the IMON pin votage exceeds 1.38V (typica). This corresponds to an average votage of 63.6mV (typica) across the ISP and ISN pins: I OUT(OVERCURRENT) = 63.6mV R SENSE2 I OUT(OVERCURRENT) =1.27 I OUT(LIMIT) 2

21 Appications Information Battery Charging and C/1 A usefu appication for imiting the output current is to charge a battery. When charging a battery such as a 12V ead acid battery, it may be usefu to charge to a buk and foat votage, in which case, the C/1 function of the FLAG pin can be used. For decreasing charge currents, C/1 is detected when the IMON votage fas beow 666.5mV (typica) and corresponds to an average ISP ISN votage of 5mV (typica). For increasing charge currents, C/1 is ceared when IMON gets above 727.5mV (typica) which corresponds to an average ISP ISN votage of 1mV (typica). To set a buk and foat battery votage, simpy connect a resistor from the FLAG pin to the FBX pin. When the battery charging current is high (C/1 not detected), the target output votage is the buk battery votage as set by the resistor connected between the FLAG and FBX pins. Once the charging current drops such that C/1 is detected, the target output votage drops to the foat battery votage as set by the externa FBX resistor. See Figure 1 beow on the FLAG pin connections and equations for setting the buk and foat battery votages. Note that in order to use the C/1 feature, the MODE pin must be high to operate in DCM at ight oads. PG CHRG DCM_EN 1µs ANTI-GLITCH FROM CONTROLLER IMON FLAG GND R FBX = (FLOAT)1.213V 83.7µA 666.5mV R FLAG R FBX FBX 1.213V 83.7µA 871 F V R FLAG =R FBX (BULK) (FLOAT) Figure 1. FLAG Pin Connections and Equations for Battery Charging C OUT LEAD ACID BATTERY Capacitor Charging When the appication is to charge a bank of capacitors such as SuperCaps, the charging current is set by R SENSE2 and the FLAG pin isn t necessariy needed as in the case of charging a battery. Temperature Dependent Output Votage Using NTC Resistor It may be desirabe to reguate the converter s output based on the ambient temperature. The INTV CC LDO reguated votage is 6.3V ± 1.6% (see Eectrica Characteristics), and a negative temperature coefficient (NTC) resistor can be used to sum into the FBX pin to create an output votage that decreases with temperature. See Figure 11 for the necessary connections. The FBX votages reguates to 1.213V (typica) for positive output votages. For an accurate room temperature output votage, size the resistor divider off the INTV CC pin to give 1.213V such that the current through R2 is ~ at room temperature. Choose R NTC(25) 1kΩ and use the equations beow to cacuate R 1, R FBX, and at room temperature and R 2 for a desired change over temperature V R1=RNTC(25) 1.213V (25) 1.213V83.7µA R FBX R FBX R2 R 1.213V 6.3V 1 R 1 R NTC(25) R NTC =R NTC(25) e β 1 ( T 1 T 25 ) = 6.3V R FBX R R R 1 R NTC(T(MAX)) R 1 R NTC(T(MIN)) R 2 = 6.3V R V FBX R1 OUT 1 1 R 1 R NTC(T(MAX)) R 1 R NTC(T(MIN)) 21

22 Appications Information where: R NTC(25) = Resistance of the NTC resistor at 25 C b T = Materia-specific constant of NTC resistor. Specified at two temperatures such as b 25/85. If more than two bs are specified, use the most appropriate for the appication. = Absoute temperature in Kevin T 25 = Room temperature in Kevin (298.15k) FROM SYSTEM R FBX R2 6.3V R NTC R1 FBX INTV CC 1.213V 14.5k 14.5k SWITCH CURRENT LIMIT (R SENSE1 AND CSP-CSN PINS) The externa current sense resistor (R SENSE1 ) sets the maximum peak current though the externa NFET switch (MN). The maximum votage across R SENSE1 is 5mV (typica) at very ow switch duty cyces, and then sope compensation decreases the current imit as the duty cyce increases (see the Max Current Limit vs Duty Cyce (CSP- CSN) pot in the Typica Performance Characteristics). The equation beow gives the switch current imit for a given duty cyce and current sense resistor (find V CSPN at the operating duty cyce in the pot mentioned). GND Figure 11. Temperature Dependent Output Using an NTC Resistor Divider EA1 EA2 V C 871 F11 To provide a desired oad current for any given appication, R SENSE1 must be sized appropriatey. The switch current wi be at its highest when the input votage is at the owest of its range. The equation beow cacuates R SENSE1 for a desired output current: R SENSE1.74 η V CSPN ( 1DC MAX ) 1 i RIPPLE I OUT 2 where η = Converter efficiency (assume ~9%) V CSPN = Max current imit votage (see Max Current Limit vs Duty Cyce (CSP-CSN) pot in the Typica Performance Characteristics) I OUT = Converter oad current DC MAX = Switching duty cyce at minimum (see Power Switch Duty Cyce in Appendix) i RIPPLE = Peak-to-peak inductor rippe current percentage at minimum (recommended to use 25%) Reverse Current APPLICATIONS (MODE Pin Low) When the forced continuous mode is seected (MODE pin ow), inductor current is aowed to reverse directions and fow from the side to the side. This can ead to current sinking from the output and being forced into the input. The reverse current is at a maximum magnitude when V C is owest. The graph of Max Current Limit vs Duty Cyce (CSP CSN) in the Typica Performance Characteristics section can hep to determine the maximum reverse current capabiity. The IMON pin votage wi indicate negative inductor currents. Refer to the equation for IMON in the Pin Functions. Note that the IMON votage is ony accurate if the dynamic votage across R SENSE2 stays within 51.8mV to 5mV. If the vaey inductor current goes more negative than 3mV as sensed by R SENSE2, the externa PFET wi turn off, and the inductor current wi start going more positive. I SW(LIMIT) = V CSPN R SENSE1 22

23 Appications Information Backup Power With the use of reverse current contro and input votage reguation, the can be used as a backup power converter as shown in Figure 12 beow. With the MODE pin ow to operate in FCM, when the input source is removed, the output can suppy current into the input and keep the input reguated for some amount of time. The amount of time depends on the output capacitance and the oad current at the input. V PWR 12V ± 5% INPUT POWER SOURCE CAN BE REMOVED IDEAL DIODE BG R IN1 49.9k EN/FBIN R IN2 1k MODE C IN2 CSN CSP Figure 12. Backup Power Converter Once drops ow enough to put the INTV EE LDO in UVLO ( at ~4.25V), the PFET wi stop switching and the current wi stop fowing from to V SYSTEM. For this type of appication, it is recommended to use a PFET that is in the inear mode of operation with ony 4V of gate drive. Input Overvotage Protection Whenever the MODE pin is ow to aow current to fow from output to input, it is strongy recommended to add a coupe externa components to protect the input from overvotage as shown in Figure 13 beow. With either 1k C IN1 L1 MODE R SENSE1 GND V SYSTEM V PWR IF V PWR IS PRESENT 1.5V IF V PWR IS REMOVED MP R SENSE2 TG ISP ISN BIAS INTV EE FBX Figure 13. Input Overvotage Protection C1 MN R OVP2 _OVP = V Z 1.224V _OVP = 1.224V 1 R OVP1 871 F13 OR L2 R OVP2 R OVP1 MODE ( ) R FBX CAP BANK 871 F12 approach, as approaches the OVP point, the MODE pin approaches the MODE FCM threshod (1.224V typica) and the won't aow reverse current fow, preventing to go above the OVP point. CURRENT SENSE FILTERING Certain appications may require fitering of the inductor current sense signas due to excessive switching noise that can appear across R SENSE1 and/or R SENSE2. Higher operating votages, higher vaues of R SENSE, and more capacitive MOSFETs wi a contribute additiona noise across R SENSE when MOSFETs transition. The CSP/CSN and/or the ISP/ ISN sense signas can be fitered by adding one of the RC networks shown in Figure 14. The fiter shown in Figure 14a fiters out differentia noise, whereas the fiter in Figure 14b fiters out the differentia and common mode noise at the expense of an additiona capacitor and approximatey twice the capacitance vaue. It is recommended to Kevin the ground connection directy to the padde of the if using the fiter in Figure 14b. The fiter network shoud be paced as cose as possibe to the. Resistors greater than 1Ω shoud be avoided as this can increase the offset votages at the CSP/CSN and ISP/ISN pins. R SENSE1, R SENSE2 Figure 14a. Differentia RC Fiter on CSP/CSN and/or ISP/ISN Pins R SENSE1, R SENSE2 5.1Ω 5.1Ω 5.1Ω 5.1Ω 4.7nF 4.7nF 2.2nF CSP OR ISP CSN OR ISN 871 F14a CSP OR ISP CSN OR ISN 871 F14b Figure 14b. Differentia and Common Mode RC Fiter on CSP/ CSN and/or ISP/ISN Pins 23

24 Appications Information The RC product shoud be kept ess than 3ns, which is simpy the tota series R (5.1Ω5.1Ω in this case) times the equivaent capacitance seen across the sense pins (2.2nF for Figure 14a and 2.35nF for Figure 14b). SWITCHING FREQUENCY The uses a constant frequency architecture between 1kHz and 75kHz. The frequency can be set using the interna osciator or can be synchronized to an externa cock source. Seection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching osses, but requires arger inductance and/or capacitance to maintain ow output rippe votage. For high power appications, consider operating at ower frequencies to minimize MOSFET heating from switching osses. The switching frequency can be set by pacing an appropriate resistor from the RT pin to ground and tying the SYNC pin ow. The frequency can aso be synchronized to an externa cock source driven into the SYNC pin. The foowing sections provide more detais. Osciator Timing Resistor (R T ) The operating frequency of the can be set by the interna free-running osciator. When the SYNC pin is driven ow (<.4V), the frequency of operation is set by a resistor from the RT pin to ground. The osciator frequency is cacuated using the foowing formua: f = 35,88 R T 1 ( ) where f is in khz and R T is in k. Conversey, R T (in k) can be cacuated from the desired frequency (in khz) using: R T = 35,88 f 24 1 Cock Synchronization An externa source can set the operating frequency of the by providing a digita cock signa into the SYNC pin (R T resistor sti required). The wi operate at the SYNC cock frequency. The wi revert to its interna free-running osciator cock when the SYNC pin is driven beow.4v for a few free-running cock periods. Driving SYNC high for an extended period of time effectivey stops the operating cock and prevents atch SR1 from becoming set (see Bock Diagram). As a resut, the switching operation of the wi stop. The duty cyce of the SYNC signa must be between 2% and 8% for proper operation. Aso, the frequency of the SYNC signa must meet the foowing two criteria: 1. SYNC may not togge outside the frequency range of 1kHz to 75kHz uness it is stopped beow.4v to enabe the free-running osciator. 2. The SYNC frequency can aways be higher than the free-running osciator frequency (as set by the R T resistor), f OSC, but shoud not be ess than 25% beow f OSC. After SYNC begins togging, it is recommended that switching activity is stopped before the SYNC pin stops togging. Excess negative inductor current can resut when SYNC stops togging as the transitions from the externa SYNC cock source to the interna free-running osciator cock. Switching activity can be stopped by driving the EN/FBIN pin ow. LDO REGULATORS The has two inear reguators to run the BG and TG gate drivers. The INTV CC LDO reguates 6.3V (typica) above ground, and the INTV EE reguator reguates 6.18V (typica) beow the BIAS pin. INTV CC LDO Reguator The INTV CC LDO is used as the top rai for the BG gate driver for positive output converters. In the case of a negative output converter, the INTV CC LDO is used as the top rai for both the BG and TG gate drivers (BIAS and INTV EE must tie to INTV CC and GND respectivey). An externa capacitor greater than 2.2µF must be paced from the INTV CC pin to ground. The UVLO threshod on INTV CC is 4V (typica), and the wi be in reset unti the LDO comes out of UVLO. The INTV CC LDO can run off or BIAS and wi inteigenty seect to run off the best for minimizing chip power oss, but at the same time, seect the proper input for maintaining INTV CC as cose to 6.3V as possibe. For

25 Appications Information VOLTAGE 24V 12V 11.2V 8.5V 8V BIAS SELECTED INPUT Figure 15. INTV CC Input Votage Seection 871 F15 exampe, Figure 15 is a pot that shows an appication where /BIAS is reguated to 12V and starts at 24V and ramps down to 5V and indicates that INTV CC is reguating from or BIAS. Overcurrent protection circuitry typicay imits the maximum current draw from the LDO to ~125mA and ~65mA when running from and BIAS respectivey. When INTV CC is beow ~3.5V during start-up or an overoad condition, the typica current imit is reduced to ~25mA when running from either or BIAS. If the seected input votage is greater than 2V (typica), then the current imit of the LDO reduces ineary with input votage to imit the maximum power in the INTV CC pass device. See the INTV CC Current Limit vs or BIAS pot in the Typica Performance Characteristics. If the die temperature exceeds 175 C (typica), the current imit of the LDO drops to. Power dissipated in the INTV CC LDO shoud be minimized to improve efficiency and prevent overheating of the. The current imit reduction with input votage circuit heps prevent the part from overheating, but these guideines shoud be foowed. The maximum current drawn through the INTV CC LDO occurs under the foowing conditions: 1. Large (capacitive) MOSFETs being driven at high frequencies. 2. The converter s switch votage ( for boost or for dua inductor converters) is high, thus requiring more charge to turn the MOSFET gates on and off. In genera, use appropriatey sized MOSFETs and ower the switching frequency for higher votage appications to keep the INTV CC current at a minimum. BIAS BIAS TIME INTV EE LDO Reguator The BIAS and INTV EE votages are used for the top and bottom rais of the TG gate driver respectivey. An externa capacitor greater than 2.2µF must be paced between the BIAS and INTV EE pins. The UVLO threshod on the reguator (BIAS-INTV EE ) is 3.42V (typica) as ong as the BIAS votage is greater than ~3.36V. The TG pin can begin switching after the INTV EE reguator comes out of UVLO. For positive output converters, BIAS must be tied to the converter s output votage. For negative output converters, BIAS must connect to the INTV CC pin and the INTV EE pin ties to ground. In this manner, the votage of the INTV EE reguator is driven to the INTV CC votage of 6.3V and hence the TG gate driver wi have eves of V and 6.3V. Overcurrent protection circuitry typicay imits the maximum current draw from the reguator to ~7mA. If the BIAS votage is greater than 2V (typica), then the current imit of the reguator reduces ineary with input votage to imit the maximum power in the INTV EE pass device. See the INTV EE Current Limit vs BIAS pot in the Typica Performance Characteristics. The same therma guideines from the INTV CC LDO Reguator section appy to the INTV EE reguator as we. NON-SYNCHRONOUS CONVERTER It may be desirabe in some appications to repace the externa PFET with a Schottky diode to make a nonsynchronous converter. One exampe woud be a high output votage appication because the votage drop across the rectifier has a sma affect on the efficiency of the converter. In fact, for high output votage appications, repacing the PFET with a Schottky may resut in higher efficiency because the doesn t have to suppy gate drive to the PFET. Figure 16 shows the recommended connections for using the as a non-synchronous boost converter, however the same concept can be used for any other converter. Note that the MODE pin must be tied high if using the as a non-synchronous converter or ese the output might not be reguated at ight oad. Aso, the TG pin 25

26 Appications Information must be eft foating or permanent damage coud occur to the TG gate driver. The schematic of Figure 16 coud be modified if needed. If it is not desirabe to monitor and/ or contro the output current, R SENSE2 is not needed and simpy tie the ISP and ISN pins to INTV CC. The IMON pin can be eft foating or can connect to ground. The BIAS and INTV EE pins can tie to ground if the dua input feature of the INTV CC LDO is not needed and stays above 4.5V. C IN2 C IN1 R IN1 R IN2 L1 BG EN/FBIN MODE INTV CC MN R SENSE1 CSN CSP GND C OUT1 TG ISP ISN BIAS INTV EE FBX IMON R SENSE2 R FBX C OUT2 Pace bypass capacitors for the and BIAS pins (1µF or greater) as cose as possibe to the. Pace bypass capacitors for the INTV CC and INTV EE (between BIAS and INTV EE ) pins (2.2µF or greater) as cose as possibe to the. The oad shoud connect directy to the positive and negative terminas of the output capacitor for best oad reguation. Boost Topoogy Specific Layout Guideines Keep ength of oop (high speed switching path) governing R SENSE1, MN, MP, R SENSE2, C OUT, and ground return as short as possibe to minimize parasitic inductive spikes at the switch node during switching. L1 MP 871 F16 Figure 16. Simpified Schematic of a Non-Synchronous Boost Converter C IN MN R SENSE2 C OUT LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL INDUCTOR INVERTING TOPOLOGIES R SENSE1 Genera Layout Guideines To optimize therma performance, soder the exposed pad of the to the ground pane with mutipe vias around the pad connecting to additiona ground panes. High speed switching path (see specific topoogy beow for more information) must be kept as short as possibe. The FBX, V C, IMON, and RT components shoud be paced as cose to the as possibe, whie being far away as practicay possibe from switching nodes. The ground for these components shoud be separated from the switch current path. CKT Figure 17. Suggested Component Pacement for Boost Topoogy 875 F17 SEPIC Topoogy Specific Layout Guideines Keep ength of oop (high speed switching path) governing R SENSE1, MN, C1, MP, R SENSE2, C OUT, and ground return as short as possibe to minimize parasitic inductive spikes at the switch node during switching. GND 26

27 Appications Information L1 L2 C1 L1 L2 MP C1 MN MP MN C IN R SENSE2 C OUT C IN R1 D1 C2 C OUT R SENSE1 R SENSE2 R SENSE1 CKT GND CKT GND 875 F18 Figure 19. Suggested Component Pacement for Dua Inductor Inverting Topoogy 875 F19 Figure 18. Suggested Component Pacement for SEPIC Topoogy Dua Inductor Inverting Topoogy Specific Layout Guideines Keep ground return path from the ow side of R SENSE1 and R SENSE2 (to chip) separated from C IN s and C OUT s ground return path (to chip) in order to minimize switching noise couping into the input and output. Notice the cuts in the ground return for the ow side of R SENSE1 and R SENSE2. Keep ength of oop (high speed switching path) governing R SENSE1, MN, C1, MP, R SENSE2, and ground return as short as possibe to minimize parasitic inductive spikes at the switch node during switching. Current Sense Resistor Layout Guideines Route the CSP/CSN and ISP/ISN ines differentiay (cose together) from the chip to the current sense resistor as shown in Figure 2. Pace the vias that connect the CSP/CSN and ISP/ISN ines directy at the terminas of the current sense resistor as shown in Figure 2. TO CURRENT SENSE PINS Figure 2. Suggested Routing and Connections of CSP/CSN and ISP/ISN Lines THERMAL CONSIDERATIONS R SENSE1, F2 Overview The primary components on the board that consume the most power and produce the most heat are the power switches, MN and MP, the power inductor, and the IC. It is imperative that a good therma path be provided for these components to dissipate the heat generated within the packages. This can be accompished by taking advantage of the therma pads on the underside of the packages. It is recommended that mutipe vias in the printed circuit board be used to conduct heat away from each of these components and into a copper pane with as much area as possibe. For the case of the power switches, the copper area of the drain connections shoudn t be too big as to create a arge EMI surface that can radiate noise around the board. 27

28 Appications Information Power MOSFET Loss and Therma Cacuations The requires two externa power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. Important parameters for estimating the power dissipation in the MOSFETs are: 1. On-resistance (R DSON ) 2. Gate-to-drain charge (Q GD ) 3. PFET body diode forward votage (V BD ) 4. V DS of the FETs during their Off-Time 5. Switch current (I SW ) 6. Switching frequency (f) The power oss in each power switch has a DC and AC term. The DC term is when the power switch is fuy on, and the AC term is when the power switch is transitioning from on-off or off-on. The foowing appies for both the NFET and PFET power switches. For a boost appication, the average current through the MOSFET (I SW ) during its on-time, is the same as the average input current. The magnitude of the drainto-source votage, V DS, during its off-time is approximatey. For a SEPIC or dua inductor inverting appication, the average current through each MOSFET (I SW ) during its on-time, is the sum of the average input current and the output current. The V DS votage during the off-time is approximatey. During the non-overap time of the gate drivers, the peak and vaey inductor current is fowing through the body diode of the PFET. Beow are the equations for the power oss in MN and MP. PMOSFET = PI 2 R P SWITCHING P MN = I 2 N R DS O N V DS I N f t RF P RR N P MP =I 2 I P R DSO NV BD I PK VY f14nsp 1.6 RR P I SW = I OUT (1DC) ; I i PK =I SW RIPPLE ; I VY =I SW i RIPPLE 2 2 i 2 I N = DC I 2 SW RIPPLE 12 I P = ( 1DC) i 2 I 2 SW RIPPLE 12 P RR N V DSI RR t RR f 2 PRR P V DS I RR t RR f 2 where: f = Switching Frequency I N = NFET RMS Current I P = PFET RMS Current t RF = Average of the rise and fa times of the NFET s drain votage I SW = Average switch current during its on-time I PK = Peak inductor current I VY = Vaey inductor current i RIPPLE = Inductor rippe current DC = Switch duty cyce (see Power Switch Duty Cyce section in Appendix) V BD V DS = PFET body diode forward votage at I SW = Votage across the FET when it s off. for a boost, for a dua inductor inverting or SEPIC converter P RR-N = PFET body diode reverse recovery power oss in the NFET P RR-P = PFET body diode reverse recovery power oss in the PFET 28

29 Appications Information I RR t RR = Current needed to remove the PFET body diode charge = Reverse recovery time of PFET body diode Typica vaues for t RF are 1ns to 4ns depending on the MOSFET capacitance and drain votage. In genera, the ower the Q GD of the MOSFET, the faster the rise and fa times of its drain votage. For best cacuations, measure the rise and fa times in the appication. PFET body diode reverse recovery power oss is dependent on many factors and can be difficut to quantify in an appication. In genera, this power oss increases with higher V DS and/or higher switching frequency. Chip Power and Therma Cacuations Power dissipation in the chip comes from three primary sources: INTV CC and INTV EE LDOs providing gate drive to the BG and TG pins and additiona input quiescent current. The average current through each LDO is determined by the gate charge of the power switches, MN and MP, and the switching frequency. Beow are the equations for cacuating the chip power oss foowed by exampes. Noninverting Converter: The INTV CC LDO primariy suppies votage for the BG gate driver. The BIAS and INTV EE votages suppy the top and bottom rais of the TG gate driver respectivey. The chip Q current comes from the higher of and BIAS. Beow are the chip power equations for a noninverting converter: P VCC = 1.4 Q MN f V SELECT P VEE1 = Q MP f V BIAS P VEE2 = 3.1mA (1 DC) V BIAS P Q = 4mA V MAX where: f = Switching frequency DC = Switch duty cyce (see Power Switch Duty Cyce section in Appendix) Q MN = Tota gate charge of NFET power switch (MN) at 6.3V GS Q MP = Tota gate charge of PFET power switch (MP) at 6.18V SG V SELECT = INTV CC LDO seected input votage, or BIAS (see LDO REGULATORS section) V MAX = Higher of and BIAS. Inverting Converter: Due to BIAS connecting to INTV CC and INTV EE connecting to ground (see Typica Appications), a the chip power comes from the pin. The INTV CC LDO primariy suppies votage for both the BG and TG gate drivers. The chip Q current comes from. For consistency, the power that s needed to run the TG gate driver is sti abeed as P VEE even though the power is coming from INTV CC. Beow are the chip power equations for an inverting converter: P VCC = 1.4 Q MN f P VEE1 = Q MP f P VEE2 = 3.15mA (1 DC) P Q = 5.5mA where: f = Switching frequency DC = Switch duty cyce (see Power Switch Duty Cyce section in Appendix) Q MN = Tota gate charge of NFET power switch (MN) at 6.3V GS Q MP = Tota gate charge of PFET power switch (MP) at 6.3V SG Chip Power Cacuations Exampe Tabe 4 cacuates the power dissipation of the for a 2kHz, 3V 4V to 5V SEPIC appication when is 12V. From P CHIP in Tabe 4, the die junction temperature can be cacuated using the appropriate therma resistance and worst-case ambient temperature: T J = T A Q JA P CHIP where T J = die junction temperature, T A = ambient temperature and θ JA is the therma resistance from the siicon junction to the ambient air. The pubished θ JA vaue is 38 C/W for the TSSOP exposed pad package. In practice, ower θ JA vaues are reaizabe if board ayout is performed with appropriate grounding 29

30 Appications Information (accounting for heat sinking properties of the board) and other considerations isted in the Layout Guideines section. For instance, a θ JA vaue of ~22 C/W was consistenty achieved when board ayout was optimized as per the suggestions in the Layout Guideines section. Therma Lockout If the die temperature reaches ~175 C, the part wi go into reset, so the power switches turn off and the soft-start capacitor wi be discharged. The wi come out of reset when the die temperature drops by ~5 C (typica). Tabe 4. Power Cacuations Exampe for a 2kHz, 3V to 4V to 5V/5A SEPIC ( = 12V, MN = FDMS865L and MP = SUD5P6-15) DEFINITION OF VARIABLES EQUATION DESIGN EXAMPLE VALUE DC = Switch Duty Cyce V DC OUT 5V DC 29.4% DC 12V 5V P VCC = INTV CC LDO Power Driving the BG Gate Driver Q MN = NFET Tota Gate Charge at V GS = 6.3V f = Switching Frequency V SELECT = LDO Chooses P VEE1 = INTV EE LDO Power Driving the TG Gate Driver Q MP = PFET Tota Gate Charge at V SG = 4.25V P VEE2 = Additiona TG Gate Driver Power Loss P Q = Chip Bias Loss V MAX = Higher Votage of and BIAS P VCC = 1.4 Q MN f V SELECT P VCC = nC 2kHz 12V P VCC = 182.2mW P VEE1 = Q MP f V BIAS P VEE1 = 55nC 2kHz 5V P VEE1 = 55mW P VEE2 = 3.1mA (1 DC) V BIAS P VEE2 = 3.1mA (1.294) 5V P VEE2 = 1.9mW P Q = 4mA V MAX P Q = 4mA 12V P Q = 48mW P CHIP = 296.1mW 3

31 AppENDIX POWER SWITCH DUTY CYCLE In order to maintain oop stabiity and deiver adequate current to the oad, the externa power NFET (MN in the Bock Diagram) cannot remain on for 1% of each cock cyce. The maximum aowabe duty cyce is given by: ( ) DC MAX = T P MinOffTime T P 1% where T P is the cock period and MinOffTime (found in the Eectrica Characteristics) is a maximum of 48ns. Conversey, the externa power NFET (MN in the Bock Diagram) cannot remain off for 1% of each cock cyce, and wi turn on for a minimum on time (MinOnTime) when in reguation. This MinOnTime governs the minimum aowabe duty cyce given by: DC MIN = (MinOnTime) 1% T P where T P is the cock period and MinOnTime (found in the Eectrica Characteristics) is a maximum of 42ns. The appication shoud be designed such that the operating duty cyce is between DC MIN and DC MAX. Duty cyce equations for severa common topoogies are given beow where V ON_MP is the votage drop across the externa power PFET (MP) when it is on, and V ON_MN is the votage drop across the externa power NFET (MN) when it is on. For the boost topoogy (see Figure 5): V DC BOOST OUT V ON_MP V ON_MP V ON_MN For the SEPIC or dua inductor inverting topoogy (see Figures 6 and 7): V DC SEPIC_&_INVERT OUT V ON_MP V ON_MP V ON_MN The can be used in configurations where the duty cyce is higher than DC MAX, but it must be operated in the discontinuous conduction mode (MODE pin must be high) so that the effective duty cyce is reduced. INDUCTOR SELECTION For high efficiency, choose inductors with high frequency core materia, such as ferrite, to reduce core osses. Aso to improve efficiency, choose inductors with more voume for a given inductance. The inductor shoud have ow DCR (copper-wire resistance) to reduce I 2 R osses, and must be abe to hande the peak inductor current without saturating. Note that in some appications, the current handing requirements of the inductor can be ower, such as in the SEPIC topoogy where each inductor carries a fraction of the tota switch current. Moded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5A to 15A range. To minimize radiated noise, use a toroida or shieded inductor. See Tabe 5 for a ist of inductor manufacturers. Tabe 5. Inductor Manufacturers Coicraft MSS1278, XAL11, and MSD1278 Series Cooper Bussmann DRQ127, DR127, and HCM114 Series Vishay IHLP Series Würth WE-DCT Series WE-CFWI Series Minimum Inductance Athough there can be a trade-off with efficiency, it is often desirabe to minimize board space by choosing smaer inductors. When choosing an inductor, there are three conditions that imit the minimum inductance; (1) providing adequate oad current, and (2) avoidance of subharmonic osciation, and (3) suppying a minimum rippe current to avoid fase tripping of the current comparator. 31

32 AppENDIX Adequate Load Current Sma vaue inductors resut in increased rippe currents and thus, due to the imited peak switch current, decrease the average current that can be provided to the oad. In order to provide adequate oad current, L shoud be at east: V L BOOST IN DC V 2 f CSPN I OUT R SENSE1 η or V L DUAL IN DC V 2 f CSPN I OUT I R SENSE1 η OUT where: L BOOST = L 1 for boost topoogies (see Figure 5) L DUAL L DUAL DC V CSPN = L 1 = L 2 for couped dua inductor topoogies (see Figures 6 and 7) = L 1 L 2 for uncouped dua inductor topoogies (see Figures 6 and 7) = Switch duty cyce (see previous section) = Current imit votage at the operating switch duty cyce (see Max Current Limit vs Duty Cyce (CSP CSN) pot in the Typica Performance Characteristics) R SENSE1 = Current sense resistor connected across the CSP-CSN pins (see Bock Diagram) η = Power conversion efficiency (assume 9%) f I OUT = Switching frequency = Maximum output current Boost Topoogy SEPIC or Inverting Topoogies Negative vaues of L BOOST or L DUAL indicate that the output oad current, I OUT, exceeds the switch current imit capabiity of the converter. Decrease R SENSE1 to increase the switch current imit. Avoiding Subharmonic Osciations The s interna sope compensation circuit wi prevent subharmonic osciations that can occur when the duty cyce is greater than 5%, provided that the inductance exceeds a minimum vaue. In appications that operate with duty cyces greater than 5%, the inductance must be at east: L MIN R SENSE1 (2DC1) 4mDC f (1DC) where L MIN = L 1 for boost topoogies (see Figure 5) L MIN = L 1 = L 2 for couped dua inductor topoogies (see Figures 6 and 7) L MIN = L 1 L 2 for uncouped dua inductor topoogies (see Figures 6 and 7) Maximum Inductance Excessive inductance can reduce rippe current to eves that are difficut for the current comparator (A5 in the Bock Diagram) to ceany discriminate, thus causing duty cyce jitter and/or poor reguation. The maximum inductance can be cacuated by: L MAX R SENSE1 DC 5m f where: L MAX = L 1 for boost topoogies (see Figure 5) L MAX = L 1 = L 2 for couped dua inductor topoogies (see Figures 6 and 7) L MAX = L 1 L 2 for uncouped dua inductor topoogies (see Figures 6 and 7) Inductor Current Rating The inductor(s) must have a rating greater than its (their) peak operating current to prevent inductor saturation, which woud resut in efficiency osses. The maximum 32

33 AppENDIX inductor current (considering start-up and steady-state conditions) is given by: I L_PEAK = where I L_PEAK 54mV 16mV DC2 T MIN_PROP R SENSE1 L = Peak inductor current in L 1 for a boost topoogy, or the sum of the peak inductor currents for dua inductor topoogies. T MIN_PROP = 1ns (propagation deay through the current feedback oop). For wide input votage range appications, as the input votage increases, the max peak inductor current aso increases due to the duty cyce decreasing. It is recommended to utiize the output current imiting feature to reduce the max peak inductor current given by the foowing equation: V I L_PEAK = ISPN R SENSE2 (1DC) DC 2 f L where. V ISPN = 57mV max for noninverting converters and 6mV max for inverting converters. Note that these equations offer conservative resuts for the required inductor current ratings. The current ratings coud be ower for appications with ight oads, and if the SS capacitor is sized appropriatey to imit inductor currents at start-up. POWER MOSFET SELECTION The requires two externa power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. It is important to seect MOSFETs for optimizing efficiency. For choosing an NFET and PFET, the important device parameters are: 1. Breakdown votage (BV DSS ) 2. Gate threshod votage (V GSTH ) 3. On-resistance (r DSON ) 4. Tota gate charge (Q G ) 5. Turn-off deay time (t D(OFF) ) 6. Package has exposed padde The drain-to-source breakdown votage of the NFET and PFET power MOSFETs must exceed: BV DSS > for boost converter BV DSS > for SEPIC or dua inductor inverting converter If operating cose to the BV DSS rating of the MOSFET, check the eakage specifications on the MOSFET because eakage can decrease the efficiency of the converter. The NFET and PFET gate-to-source drive is approximatey 6.3V and 6.18V respectivey, so ogic eve MOSFETs are required. The BG gate driver can begin switching when the INTV CC votage exceeds ~4V, so ensure the seected NFET is in the inear mode of operation with 4V of gateto-source drive to prevent possibe damage to the NFET. The TG gate driver can begin switching when the BIAS- INTV EE votage exceeds ~3.42V, so it is optima that the PFET be in the inear mode of operation with 3.42V of gate-to-source drive. However, the PFET is ess ikey to get damaged if it s not operating in the inear region since the drain-to-source votage is camped by its body diode during the NFET s off-time. Having said that, try to choose a PFET with a ow body diode reverse recovery time to minimize stored charge in the PFET. The stored charge in the PFET body diode gets removed when the NFET switch turns on and can ead to efficiency hits especiay in appications where the V DS of the PFET (during off-time) is high. For these appications, it may be beneficia to put a Schottky diode across the PFET to reduce the amount of charge in the PFET body diode. In appications where the output votage is high in magnitude, it may be better to repace the PFET with a Schottky diode since the converter may be more efficient with a Schottky. Power MOSFET on-resistance and tota gate charge go hand-in-hand and are typicay inversey proportiona to each other; the ower the on-resistance, the higher tota gate charge. Choose MOSFETs with an on-resistance to give a votage drop to be ess than 3mV at the peak 33

34 AppENDIX current. At the same time, choose MOSFETs with a ower tota gate charge to reduce power dissipation and MOSFET switching osses. The turn-off deay time (t D(OFF) ) of avaiabe NFETs is generay smaer than the s non-overap time. However, the turn-off time of the avaiabe PFETs shoud be ooked at before deciding on a PFET for a given appication. The turn-off time must be ess than the non-overap time of the or ese the NFET and PFET coud be on at the same time and damage to externa components may occur. If the PFET turn-off deay time as specified in the data sheet is ess than the non-overap time, then the PFET is good to use. If the turn-off deay time is onger than the non-overap time, it doesn t necessariy mean it can t be used. It may be uncear how the PFET manufacturer measures the turn-off deay time, so it is best to measure the PFET turn-off deay time with respect to the PFET gate votage. Finay, both the NFET and PFET power MOSFETs shoud be in a package with an exposed padde for the drain connection to be abe to dissipate heat. The on-resistance of MOSFETs is proportiona to temperature, so it s more efficient if the MOSFETs are running coo with the hep of the exposed padde. See Tabe 6 for a ist of power MOSFET manufacturers. Tabe 6. Power MOSFET (NFET and PFET) Manufacturers Fairchid Semiconductor On-Semiconductor Vishay Diodes Inc. INPUT AND OUTPUT CAPACITOR SELECTION Input and output capacitance is necessary to suppress votage rippe caused by discontinuous current moving in and out of the reguator. A parae combination of capacitors is typicay used to achieve high capacitance and ow ESR (equivaent series resistance). Tantaum, specia poymer, auminum eectroytic and ceramic capacitors are a avaiabe in surface mount packages. Capacitors with ow ESR and high rippe current ratings, such as OS-CON and POSCAP are aso avaiabe. Ceramic capacitors shoud be paced near the reguator input and output to suppress high frequency switching noise. A minimum 1µF ceramic capacitor shoud aso be paced from to GND and from BIAS to GND as cose to the pins as possibe. Due to their exceent ow ESR characteristics, ceramic capacitors can significanty reduce rippe votage and hep reduce power oss in the higher ESR buk capacitors. X5R or X7R dieectrics are preferred, as these materias retain their capacitance over wide votage and temperature ranges. Many ceramic capacitors, particuary 85 or 63 case sizes, have greaty reduced capacitance at the desired operating votage. Input Capacitor, C IN The input capacitor, C IN, sees the rippe current of the input inductor, L 1, which eases the capacitance requirements of C IN. Beow is the equation for cacuating the capacitance of C IN for.5% input votage rippe: C IN > where: DC 8 L f 2.5 DC = Switch duty cyce (see Power Switch Duty Cyce section) L = L BOOST or L DUAL (see Inductor Seection section) f = Switching frequency The worst-case for the input capacitor (argest capacitance needed) is when the input votage is at its owest because the duty cyce is the highest. Keep in mind that the votage rating of the input capacitor needs to be greater than the maximum input votage. This equation cacuates the capacitance vaue during steady-state operation and may need to be adjusted for desired transient response. Aso, this assumes no ESR, so the input capacitance may need to be arger depending on the equivaent ESR of the input capacitor(s). Output Capacitor, C OUT The output capacitor, C OUT, in a boost or SEPIC topoogy has chopped current fowing through it, whereas the output capacitor in a dua inductor inverting topoogy sees the 34

35 AppENDIX inductor rippe current. Beow is the equation for cacuating the capacitance of C OUT for.5% output votage rippe: or I C OUT > OUT DC f.5 C OUT > where: 1DC 8 L f 2.5 I OUT = Maximum output current of converter DC = Switch duty cyce (see Power Switch Duty Cyce section) L f = L BOOST or L DUAL (see Inductor Seection section) = Switching frequency The worst-case for the output capacitor (argest capacitance needed) is when the output reguation votage is reativey ow. This equation cacuates the capacitance vaue during steady-state operation and may need to be adjusted for desired transient response. Aso, this assumes no ESR, so the output capacitance may need to be arger depending on the equivaent ESR of the output capacitor(s). See Tabe 7 for a ist of ceramic capacitor manufacturers. Tabe 7. Ceramic Capacitor Manufacturers TDK Murata Taiyo Yuden Boost or SEPIC Topoogies Dua Inductor Inverting Topoogy the optimum vaue for R C can be found. The series capacitor can be reduced or increased from 4.7nF to speed up the converter or sow down the converter, respectivey. For the circuit in Figure 7, a 3.3nF series cap was used. Figures 21a to 21c iustrate this process for the circuit of Figure 7 with a oad current stepped between 2A and 5.5A with an input votage of 9V. Figure 21a shows the transient response with R C equa to 1k. The phase margin is poor as evidenced by the excessive ringing in the output votage and inductor current. In Figure 21b, the vaue of R C is increased to 4k, which resuts in a more damped response. Figure 21c shows the resuts when R C is increased further to 11.5k. The transient response is nicey damped and the compensation procedure is compete. 2mV/DIV AC-COUPLED LOAD STEP 5A/DIV I L1 I L2 5A/DIV Figure 21a. Transient Response Shows Excessive Ringing 2mV/DIV AC-COUPLED LOAD STEP 5A/DIV R C = 1k 2µs/DIV 875 F21a COMPENSATION ADJUSTMENT To compensate the feedback oop of the, a series resistor capacitor network in parae with an optiona singe capacitor shoud be connected from the V C pin to GND. For most appications, choose a series capacitor in the range of 1nF to 1nF with 4.7nF being a good starting vaue. The optiona parae capacitor shoud range in vaue from 47pF to 22pF with 1pF being a good starting vaue. The compensation resistor, R C, is usuay in the range of 5k to 5k. A good technique to compensate a new appication is to use a 1k potentiometer in pace of the series resistor R C. With the series and parae capacitors at 4.7nF and 1pF respectivey, adjust the potentiometer whie observing the transient response and I L1 I L2 5A/DIV 2mV/DIV AC-COUPLED LOAD STEP 5A/DIV I L1 I L2 5A/DIV R C = 4k 2µs/DIV 875 F21b Figure 21b. Transient Response is Better R C = 11.5k 2µs/DIV 875 F21c Figure 21c. Transient Response is We Damped 35

36 AppENDIX COMPENSATION THEORY Like a other current mode switching reguators, the needs to be compensated for stabe and efficient operation. Two feedback oops are used in the : a fast current oop which does not require compensation, and a sower votage oop which does. Standard bode pot anaysis can be used to understand and adjust the votage feedback oop. As with any feedback oop, identifying the gain and phase contribution of the various eements in the oop is critica. Figure 22 shows the key equivaent eements of a boost converter. Because of the fast current contro oop, the power stage of the IC, inductor and PFET have been repaced by a combination of the equivaent transconductance ampifier g mp and the current controed current source (which converts I VIN to η I VIN ). G mp acts as a current source where the peak input current, I VIN, is proportiona to the V C votage and current sense resistor, R SENSE1. C F R C C C V C R O g mp g ma I VIN 1.213V REFERENCE C PL C C : COMPENSATION CAPACITOR C OUT : OUTPUT CAPACITOR C PL : PHASE LEAD CAPACITOR C F : HIGH FREQUENCY FILTER CAPACITOR g ma : TRANSCONDUCTANCE AMPLIFIER INSIDE IC g mp : POWER STAGE TRANSCONDUCTANCE AMPLIFIER R C : COMPENSATION RESISTOR R L : OUTPUT RESISTANCE DEFINED AS /I LOADMAX R O : OUTPUT RESISTANCE OF g ma R2, R FBX : FEEDBACK RESISTOR DIVIDER NETWORK R ESR : OUTPUT CAPACITOR ESR η: CONVERTER EFFICIENCY (~9% AT HIGHER CURRENTS) R2 R FBX Figure 22. Boost Converter Equivaent Mode η V R IN L R ESR I V VIN OUT C OUT R2 FBX R L 871 F22 Note that the maximum output currents of g mp and g ma are finite. The externa current sense resistor, R SENSE1, sets the vaue of: 1 g mp 6 R SENSE1 The error ampifier, g ma, is nominay about 2µmhos with a source and sink current of about 12µA and 19µA respectivey. From Figure 22, the DC gain, poes and zeros can be cacuated as foows: DC GAIN: A DC =g ma R O g mp η R L 2.5R 2 R FBX.5R 2 2 Output Poe: P1= 2 π R L C OUT 1 Error AmpPoe:P2= 2 π (R O R C )C C 1 Error Amp Zero: Z1= 2 π R C C C 1 ESR Zero: Z2= 2 π R ESR C OUT V RHP Zero: Z3= 2 IN R L 2 π V 2 OUT L HighFrequency Poe:P3> f S 3 1 Phase Lead Zero: Z4= 2 π R FBX C PL 1 Phase LeadPoe:P4= 2 π R FBX.5R 2 C R FBX.5R PL 2 1 C Error AmpFiter Poe:P5= 2 π R C R,C F < C O C 1 R C R F O The current mode zero (Z3) is a right haf pane zero which can be an issue in feedback contro design, but is manageabe with proper externa component seection. 36

37 AppENDIX Using the circuit in Figure 24 with a 4A oad as an exampe, Tabe 9 shows the parameters used to generate the bode pot shown in Figure 23. Tabe 9: Bode Pot Parameters PARAMETER VALUE UNITS COMMENT R L 3 Ω Appication Specific C OUT 88 µf Appication Specific R ESR 2 mω Appication Specific R O 35 kω Not Adjustabe C C 33 pf Adjustabe C F 1 pf Optiona/Adjustabe C PL pf Optiona/Adjustabe R C 18 kω Adjustabe R FBX 13 kω Adjustabe R kω Not Adjustabe 12 V Appication Specific 5 V Appication Specific g ma 2 µmho Not Adjustabe g mp 167 mho Appication Specific L 1.3 µh Appication Specific f OSC 4 khz Adjustabe Figure 23. Bode Pot for Exampe Boost Converter From Figure 23, the phase is 135 when the gain reaches db giving a phase margin of 45. The crossover frequency is 2kHz, which is about three times ower than the frequency of the RHP zero Z3 to achieve adequate phase margin. GAIN (db) GAIN 45 AT 2kHz PHASE k 1k 1k 1M FREQUENCY (Hz) 871 F PHASE (DEG) 5V L1 1.3µH 1m MN 2 R SENSE1 MP R SENSE2 5m 12V 6A C OUT 22µF 4 BG CSN CSP TG C IN2 33µF C IN1 22µF 4 R IN1 13.3k R IN2 1k 2.2µF R T 88.7k EN/FBIN MODE INTV CC RT SYNC GND IMON C IMON 47nF SS ISP ISN BIAS INTV EE FBX FLAG V C C SS 22nF 2.2µF C F 1pF R FBX 13k R C 18k C C 3.3nF 871 F24 Figure 24. 5V to 12V Boost Converter 37

38 Typica Appication 3kHz, 4.5V to 25V Input to 5V Output Deivers Up to 7A Output Current 4.5V TO 25V C IN1 1µF 4 L1 2.2µH 1.5m MN C1 1µF 2 R SENSE1 499Ω.47µF D1 4m MP L2 2.2µH R SENSE2 5V 7A C OUT2 33µF C IN2 12µF 13.3k 1k 2.2µF BG EN/FBIN MODE CSN CSP TG ISN ISP BIAS INTV EE INTV CC 2.2µF 6.4k C OUT1 1µF 2 INTV CC FBX 118k RT SYNC GND FLAG V C IMON SS 1pF 11.5k 47nF 22nF 3.3nF 871 TA2a L1, L2: WÜRTH 2.2µH WE-CFWI MN: FAIRCHILD FDMS8333L MP: FAIRCHILD FDD4141 R SENSE1 : 1.5mΩ 21 R SENSE2 : 4mΩ 2512 D1: NXP PMEG21EA C IN1 : 1µF, 5V, 121, X7S C IN2 : OSCON 12µF, 35V, 35SVPF12M C OUT1 : 1µF, 6.3V, 1812, X5R C OUT2 : OSCON 33µF, 16V, 16SEQP33M C1: 1µF, 5V, 121, X7S Efficiency and Power Loss Transient Response with 2A to 5.5A to 2A Output Load Step ( = 12) 1 8 EFFICIENCY (%) POWER LOSS (W) 2mV/DIV AC-COUPLED LOAD STEP 5A/DIV I L1 I L2 5A/DIV = 5V = 12V LOAD CURRENT (A) 871 TA2b µs/DIV 871 TA2c 38

39 Typica Appication 3kHz, SuperCap Backup Power 12V ±5% INPUT POWER SOURCE CAN BE REMOVED D IN C IN2 12µF V SYSTEM = WHEN IS PRESENT 1.5V WHEN IS REMOVED L1, 1µH C1, 1µF D1 15V 1k C IN1 22µF k 1k 2.2µF R T 118k BG INTV CC MODE RT 5m EN/FBIN SYNC GND MN R SENSE1 CSN CSP IMON L2 1µH MP TG ISP SS ISN BIAS INTV EE FBX FLAG V C R SENSE2 5m 5.1Ω 5.1Ω 4.7nF 4.7nF 2.2µF 1pF 14.3k 165k C OUT 22µF 2 1.2k 1.2k 1.2k 1.2k 1.2k 1.2k 15V C S1 6F C S2 6F C S3 6F C S4 6F C S5 6F C S6 6F 47nF 22nF 2.2nF 871 TA3a L1, L2: COILCRAFT 1µH MSD ML C IN1 : 22µF, 25V, 1812, X7R MN: FAIRCHILD FDMC8327L C OUT : 22µF, 25V, 1812, X7R MP: VISHAY Si7611DN C1: 1µF, 25V, 121, X7R R SENSE1 : 5mΩ 21 C S1-6 : POWERSTOR HB184-2R566-R R SENSE2 : 5mΩ 2512 D1: CENTRAL SEMI CMDZ5245B-LTZ D IN : APPROPRIATE SCHOTTKY DIODE OR IDEAL DIODE SUCH AS LTC4358, LTC4352, LTC4412, ETC. SuperCaps Charging When Is Appied HOLD-UP TIME (s) System Hod-Up Time vs System Load Current V SYSTEM = 1.5V DURING HOLD-UP LOAD CURRENT (A) TA3b 1V/DIV 1V/DIV V IMON 1V/DIV I L1 I L2 5A/DIV 1V/DIV 1V/DIV V IMON 1V/DIV 3s/DIV 871 TA3c SuperCaps Hod-Up System at 1.5V for ~83s When Is Removed (I SYSTEM = 1A) I L1 I L2 5A/DIV 3s/DIV 871 TA3d 39

40 Typica Appication 4kHz, 12V Boost Converter Deivers Up to 6A from a 4.5V to 9V Input 4.5 TO 9V C IN1 22µF 4 L1 1.3µH 1m MN 2 R SENSE1 MP R SENSE2 5m C OUT1 22µF 4 C OUT2 33µF 12V 6A BG CSN CSP TG ISP C OUT2 33µF 13.3k 1k 2.2µF EN/FBIN MODE ISN BIAS INTV EE 2.2µF 13k INTV CC FBX 88.7k RT SYNC GND IMON FLAG V C SS 1pF 18k 47nF 22nF 3.3nF 871 TA4a L1: WÜRTH 1.3µH WE-HCI MN: VISHAY SiR82DP MP: VISHAY Si7635DP R SENSE1 : 1mΩ 2512 R SENSE2 : 5mΩ 2512 C IN1 : 22µF, 16V, 126, X5R C IN2 : OSCON 33µF, 16V, 16SEQP33M C OUT1 : 22µF, 25V, 1812, X7R C OUT2 : OSCON 33µF, 16V, 16SEQP33M Efficiency and Power Loss Transient Response with 2A to 5A to 2A Output Load Step ( = 5V) mV/DIV AC-COUPLED EFFICIENCY (%) POWER LOSS (W) LOAD STEP 2A/DIV I L1 I L2 5A/DIV 3 2 = 5V 1 = 8V LOAD CURRENT (A) 871 TA4b 2µs/DIV 871 TA4c 4

41 Typica Appication 3kHz, 5V to 5V Output Ceany Transitions Through V with 3A Source and Sink Capabiity* R SENSE2 1m MP 11V TO 13V C IN2 33µF ISN ISP L1 4.4µH C IN1 22µF 4 2.2µF 118k TG BG EN/FBIN MODE 3m INTV CC RT SYNC GND C1 1µF 2 MN R SENSE1 CSN CSP TG TG ISP ISN BIAS INTV EE FBX FLAG V C L2 4.4µH ISP ISN 2.2µF D1 6.4k 6.4k 39.2k IMON SS 1pF 47nF 22nF 2.2nF 5V TO 5V ±3A C OUT 1µF 3 DC = 2 FET BV DSS > 2 CI VRATING > V CNTL =.5V FOR = V V FOR = 5V 1nF 1V FOR = 5V Schematic and Equations for Cacuating 871 TA5a L1, L2: WÜRTH 4.4µH WE-CFWI MN: FAIRCHILD FDMS8333L MP: FAIRCHILD FDD4141 R SENSE1 : 3mΩ 21 R SENSE2 : 1mΩ 2512 C IN1 : 22µF, 25V, 1812, X7R C IN2 : OSCON 33µF, 16V, 16SEQP33M C OUT : 1µF, 6.3V, 1812, X5R C1: 1µF, 25V, 121, X7R D1: CENTRAL SEMI CMPD11 FBX ~9.6mV ~83.1µA R FBX R CNTL V CNTL * PATENT PENDING = 9.6mV 83.1µA R FBX 871 TA5b R FBX (V CNTL 9.6mV) R CNTL Ceany Transitions Through V with a 1V, 1Hz Sine Wave CNTL Signa (R LOAD = 2Ω) Transient Response with Stepping V CNTL from V to 1V to V with 2Ω Output Load V CNTL 1V/DIV V CNTL 1V/DIV 5V/DIV I L1 I L2 1A/DIV 5V/DIV I L1 I L2 1A/DIV 5ms/DIV 871 TA5c 5µs/DIV 871 TA5d 41