LT V Synchronous 4-Switch Buck-Boost DC/DC Slave Controller for LT8708 Multiphase System

Transcription

1 80V Synchronous 4-Switch Buck-Boost DC/DC Save Controer for LT8708 Mutiphase System FEATURES nn nn nn nn nn nn nn nn APPLICATIONS nn nn nn Save Chip of LT8708 to Deiver Additiona Power Good Current Matching to the Average Output Current of LT8708 Through Current Reguation Easiy Paraeed with LT8708 Through Four Pins Synchronized Start-Up with LT8708 Same Conduction Modes as LT8708 Synchronous Rectification: Up to 98% Efficiency Frequency Range: 100kHz to 400kHz Avaiabe in 40-Lead (5mm 8mm) QFN with High Votage Pin Spacing High Votage Buck-Boost Converters Bidirectiona Charging Systems Automotive 48V Systems A registered trademarks and trademarks are the property of their respective owners. DESCRIPTION The LT is a high performance buck-boost switching reguator controer that is paraeed with the LT8708 to add power and phases to an LT8708 system. The aways operates as a save to the master LT8708 and has the capabiity of deivering as much current or power as the master. One or more saves can be connected to a singe master, proportionay increasing power and current capabiity of the system. The has the same conduction modes as LT8708, aowing the to conduct current and power in the same direction(s) as the master. The master contros the overa current and votage imits for an LT8708 mutiphase system, and the saves compy with these imits. s can be easiy paraeed with the LT8708 by connecting four signas together. Two additiona current imits (forward V IN current and reverse V IN current) are avaiabe on each save that can be set independenty. TYPICAL APPLICATION The Two-Phase 12V Bidirectiona Dua Battery System with FHCM and RHCM Efficiency 10V TO 16V BATTERY V BAT1 V BAT2 10V TO 16V BATTERY TO DIODE DB1 TO DIODE DB2 EFFICIENCY (%) MASTER *REFER TO LT8708 DATA SHEET FOR MASTER SETUP RVS (0V) FWD (3V) LD033 LT8708* SWEN RVSOFF CLKOUT ICP DIR ICN TG1 BOOST1 SW1 BG1 CSP CSN CSNIN CSPIN V INCHIP SHDN SWEN RVSOFF SYNC ICP ICN VINHIMON DIR FBIN LD033 MODE V C SLAVE GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTV CC VOUTLOMON INTV CC GATEV CC IMON_OP IMON_ON IMON_INP IMON_INN RT SS CLKOUT FBOUT LD033 DB DB2 TO TO BOOST1 BOOST2 V BAT2 = 13.5V V BAT2 CHARGING CURRENT = 30A V BAT1 (V) TA01b POWER TRANSFER DECISION LOGIC LD kHz TA01a Document Feedback 1

2 TABLE OF CONTENTS Features... 1 Appications... 1 Typica Appication... 1 Description... 1 Absoute Maximum Ratings... 3 Order Information... 3 Pin Configuration... 3 Eectrica Characteristics... 4 Typica Performance Characteristics... 8 Pin Functions Bock Diagram Operation Common and LT8708 Features Adding Phases to an LT8708 Appication Adding Phases: The Master LT Adding Phases: The Save Start-Up Start-Up: SWEN Pin Start-Up: Soft-Start of Switching Reguator Contro Overview Power Switch Contro Unidirectiona and Bidirectiona Conduction Error Ampifiers Transfer Function: I OUT(SLAVE) Vs I OUT(MASTER)...20 Transfer Function: CCM...21 Transfer Function: DCM, HCM and Burst Mode Operation...21 Current Monitoring and Limiting...21 Monitoring: I OUT(SLAVE)...21 Monitoring and Limiting: I IN(SLAVE)...21 Mutiphase Cocking...22 Appications Information Quick-Start Mutiphase Setup...23 Quick Setup: Design the Master Phase...23 Quick Setup: Design the Save Phase(s)...23 Quick Setup: Evauation...23 Choosing the Tota Number of Phases...23 Operating Frequency Seection C IN and C OUT Seection C IN and C OUT Seection: V IN Capacitance C IN and C OUT Seection: V OUT Capacitance...25 VINHIMON, VOUTLOMON and RVSOFF...25 Configuring the I IN(SLAVE) Current Limits...26 Reguating I OUT(SLAVE)...26 I OUT(SLAVE) : Circuit Description...26 I OUT(SLAVE) : Configuration...28 Loop Compensation...28 Votage Lockouts...29 Circuit Board Layout Checkist...29 Design Exampe...29 Typica Appications Package Description Typica Appication Reated Parts

3 ABSOLUTE MAXIMUM RATINGS (Note 1) V CSP V CSN, V CSPIN V CSNIN, V CSPOUT V CSNOUT V to 0.3V CSP, CSN Votage V to 3V V C Votage (Note 2) V to 2.2V RT, FBOUT, SS Votage V to 5V IMON_INP, IMON_INN, IMON_OP, IMON_ON, ICP, ICN Votage V to 5V SYNC Votage V to 5.5V INTV CC, GATEV CC Votage V to 7V V BOOST1 V SW1, V BOOST2 V SW V to 7V SWEN, RVSOFF Votage V to 7V SWEN Current...0.5mA RVSOFF Current...1mA FBIN, SHDN Votage V to 30V VINHIMON Votage V to 30V VOUTLOMON Votage V to 5V DIR, MODE Votage V to 5V CSNIN, CSPIN, CSPOUT, CSNOUT Votage...0.3V to 80V V INCHIP, EXTV CC Votage V to 80V SW1, SW2 Votage... 81V (Note 6) BOOST1, BOOST2 Votage V to 87V BG1, BG2, TG1, TG2...(Note 5) LDO33, CLKOUT... (Note 8) Operating Junction Temperature Range E (Notes 3, 8)...40 C to 125 C I (Notes 3, 8)...40 C to 125 C H (Notes 3, 8)...40 C to 150 C Storage Temperature Range...65 C to 150 C PIN CONFIGURATION CLKOUT SS SHDN CSN CSP ICN DIR FBIN FBOUT V C 10 IMON_INP 11 IMON_INN 12 RT 13 SYNC 14 LDO TOP VIEW GND IMON_ON BG1 IMON_OP GATEVCC MODE 41 GND BG2 SWEN UHG PACKAGE 40-LEAD (5mm 8mm) PLASTIC QFN T JMAX = 150 C, θ JA = 36 C/W, θ JC = 38 C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB INTVCC BOOST2 TG2 VINCHIP SW CSPIN CSNIN CSNOUT CSPOUT EXTV CC ICP VINHIMON VOUTLOMON RVSOFF BOOST1 TG1 SW1 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8708EUHG-1#PBF LT8708EUHG-1#TRPBF Lead (5mm 8mm) Pastic QFN 40 C to 125 C LT8708IUHG-1#PBF LT8708IUHG-1#TRPBF Lead (5mm 8mm) Pastic QFN 40 C to 125 C LT8708HUHG-1#PBF LT8708HUHG-1#TRPBF Lead (5mm 8mm) Pastic QFN 40 C to 150 C Consut ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Tape and ree specifications. Some packages are avaiabe in 500 unit rees through designated saes channes with #TRMPBF suffix. 3

4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C. V INCHIP =12V, SHDN = 3V, DIR = 3.3V uness otherwise noted. (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS Votage Suppies and Reguators V INCHIP Operating Votage Range EXTV CC = 0V EXTV CC = 7.5V V INCHIP Quiescent Current Not Switching, V EXTVCC = 0 SWEN = 3.3V SWEN = 0V V INCHIP Quiescent Current in Shutdown V SHDN = 0V 0 1 EXTV CC Switchover Votage I INTVCC = 20mA, V EXTVCC Rising V EXTV CC Switchover Hysteresis 0.2 V INTV CC Current Limit INTV CC Votage Max Current Draw from INTV CC and LDO33 Pins Combined. Reguated from V INCHIP or EXTV CC (12V) INTV CC = 5.25V INTV CC = 4.4V Reguated from V INCHIP, I INTVCC = 20mA Reguated from EXTV CC (12V), I INTVCC = 20mA INTV CC Load Reguation I INTVCC = 0mA to 50mA % INTV CC, GATEV CC Undervotage Lockout INTV CC Faing, GATEV CC Connected to INTV CC V INTV CC, GATEV CC Undervotage Lockout Hysteresis GATEV CC Connected to INTV CC 160 mv INTV CC Reguator Dropout Votage V INCHIP V INTVCC, I INTVCC = 20mA 245 mv LDO33 Pin Votage 5mA from LDO33 Pin V LDO33 Pin Load Reguation I LDO33 = 0.1mA to 5mA % LDO33 Pin Current Limit SYNC = 3V ma LDO33 Pin Undervotage Lockout LDO33 Faing V LDO33 Pin Undervotage Lockout Hysteresis 35 mv Switching Reguator Contro Maximum Current Sense Threshod (V CSP V CSN ) Boost Mode, Minimum M3 Switch Duty Cyce mv Maximum Current Sense Threshod (V CSN V CSP ) Buck Mode, Minimum M2 Switch Duty Cyce mv Maximum Current Sense Threshod (V CSN V CSP ) Boost Mode, Minimum M3 Switch Duty Cyce mv Maximum Current Sense Threshod (V CSP V CSN ) Buck Mode, Minimum M2 Switch Duty Cyce mv Gain from V C to Max Current Sense Votage (V CSP V CSN ) (A5 in the Bock Diagram) Boost Mode Buck Mode SHDN Input Votage High SHDN Rising to Enabe the Device V SHDN Input Votage High Hysteresis 40 mv SHDN Input Votage Low SHDN Pin Bias Current Device Disabed, Low Quiescent Current (LT8708E-1, LT8708I-1) (LT8708H-1) V SHDN = 3V V SHDN = 12V SWEN Rising Threshod Votage V SWEN Threshod Votage Hysteresis 22 mv SWEN Output Votage Low I SWEN = 200 SHDN = 0V or V INCHIP = 0V SHDN = 3V SWEN Interna Pu-Down Reease Votage SHDN = 3V V V V ma ma ma ma V V mv/v mv/v V V V V 4

5 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C. V INCHIP =12V, SHDN = 3V, DIR = 3.3V uness otherwise noted. (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS MODE Pin Continuous Conduction Mode (CCM) Threshod 0.4 V MODE Pin Hybrid DCM/CCM Mode (HCM) Range V MODE Pin Discontinuous Conduction Mode (DCM) Range V MODE Pin Burst Mode Operation Threshod 2.4 V DIR Pin Forward Operation Threshod 1.6 V DIR Pin Reverse Operation Threshod 1.2 V RVSOFF Output Votage Low I RVSOFF = V RVSOFF Faing Threshod Votage V RVSOFF Threshod Votage Hysteresis 165 mv Soft-Start Charging Current V SS = 0V V SS = 0.5V IMON_ON Rising Threshod for FDCM Operation MODE = 1V (HCM), DIR = 3.3V mv IMON_ON Faing Threshod for CCM Operation MODE = 1V (HCM), DIR = 3.3V mv IMON_INP Rising Threshod for RDCM Operation MODE = 1V (HCM), DIR = 0V mv IMON_INP Faing Threshod for CCM Operation MODE = 1V (HCM), DIR = 0V mv ICP Rising Threshod for Start Switching mv ICN Rising Threshod for Start Switching mv ICP Rising Threshod for Enabing Non-CCM Offset Current mv ICP Faing Threshod for Disabing Non-CCM Offset Current mv ICN Rising Threshod for Enabing Non-CCM Offset Current mv ICN Faing Threshod for Disabing Non-CCM Offset Current mv Votage Reguation Loops (Refer to Bock Diagram to Locate Ampifiers) Reguation Votage for FBOUT Reguate V C to 1.2V V Reguation Votage for FBIN Reguate V C to 1.2V V Line Reguation for FBOUT and FBIN Error Amp Reference Votage V INCHIP = 12V to 80V, Not Switching %/V FBOUT Pin Bias Current Current Out of Pin 15 na FBOUT Error Amp EA4 g m 345 µmho FBOUT Error Amp EA4 Votage Gain 245 V/V VOUTLOMON Votage Activation Threshod Faing V VOUTLOMON Threshod Votage Hysteresis 24 mv VOUTLOMON Pin Bias Current V VOUTLOMON = 1.24V, Current Into Pin V VOUTLOMON = 1.17V, Current Into Pin FBIN Pin Bias Current Current Out of Pin 10 na FBIN Error Amp EA3 g m 235 µmho FBIN Error Amp EA3 Votage Gain 150 V/V VINHIMON Votage Activation Threshod Rising V VINHIMON Threshod Votage Hysteresis 24 mv VINHIMON Pin Bias Current V VINHIMON = 1.17V, Current Into Pin V VINHIMON = 1.24V, Current Out of Pin

6 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C. V INCHIP =12V, SHDN = 3V, DIR = 3.3V uness otherwise noted. (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS Current Reguation Loops (Refer to Bock Diagram to Locate Ampifiers) Reguation Votages for IMON_INP and IMON_OP V C = 1.2V V Reguation Votages for IMON_INN V C = 1.2V V Line Reguation for IMON_INP, IMON_INN and IMON_OP Error Amp Reference Votage CSPIN Bias Current CSNIN Bias Current V INCHIP = 12V to 80V %/V V CSPIN = 12V V CSPIN = 1.5V BOOST Capacitor Charge Contro Bock Not Active V SWEN = 3.3V, V CSPIN = V CSNIN = 12V V SWEN = 3.3V, V CSPIN = V CSNIN = 1.5V V SWEN = 0V CSPIN, CSNIN Common Mode Operating Votage Range 0 80 V CSPIN, CSNIN Differentia Mode Operating Votage Range mv IMON_INP Output Current IMON_INN Output Current V CSPIN V CSNIN = 50mV, V CSNIN = 5V V CSPIN V CSNIN = 50mV, V CSNIN = 5V V CSPIN V CSNIN = 5mV, V CSNIN = 5V V CSPIN V CSNIN = 5mV, V CSNIN = 5V V CSNIN V CSPIN = 50mV, V CSNIN = 5V V CSNIN V CSPIN = 50mV, V CSNIN = 5V V CSNIN V CSPIN = 5mV, V CSNIN = 5V V CSNIN V CSPIN = 5mV, V CSNIN = 5V IMON_INP and IMON_INN Max Output Current 120 IMON_INP Error Amp EA5 g m 190 µmho IMON_INP Error Amp EA5 Votage Gain 130 V/V IMON_INN Error Amp EA1 g m FBIN = 0V, FBOUT = 3.3V 190 µmho IMON_INN Error Amp EA1 Votage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V CSPOUT Bias Current CSNOUT Bias Current V CSPOUT = 12V V CSPOUT = 1.5V BOOST Capacitor Charge Contro Bock Not Active V SWEN = 3.3V, V CSPOUT = V CSNOUT = 12V V SWEN = 3.3V, V CSPOUT = V CSNOUT = 1.5V V SWEN = 0V CSPOUT, CSNOUT Common Mode Operating Votage Range 0 80 V CSPOUT, CSNOUT Differentia Mode Operating Votage Range mv IMON_ON Output Current V CSNOUT V CSPOUT = 50mV, V CSNOUT = 5V V CSNOUT V CSPOUT = 50mV, V CSNOUT = 5V V CSNOUT V CSPOUT = 5mV, V CSNOUT = 5V V CSNOUT V CSPOUT = 5mV, V CSNOUT = 5V V CSNOUT V CSPOUT = 5mV, V CSNOUT = 5V V CSNOUT V CSPOUT = 5mV, V CSNOUT = 5V IMON_ON Max Output Current 120 CSPOUTCSNOUT Reguation Votage Reguate V C to 1.2V R IMON_OP = Ω V CSNOUT = 12V ICP = 1.218V, ICN = 0V mv ICP = 0V, ICN = 1.218V mv ICP = ICN = 0.348V mv 6

7 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the specified operating junction temperature range, otherwise specifications are at T A = 25 C. V INCHIP =12V, SHDN = 3V, DIR = 3.3V uness otherwise noted. (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS NMOS Gate Drivers TG1, TG2 Rise Time C LOAD = 3300pF (Note 4) 20 ns TG1, TG2 Fa Time C LOAD = 3300pF (Note 4) 20 ns BG1, BG2 Rise Time C LOAD = 3300pF (Note 4) 20 ns BG1, BG2 Fa Time C LOAD = 3300pF (Note 4) 20 ns TG1 Off to BG1 On Deay C LOAD = 3300pF Each Driver 90 ns BG1 Off to TG1 On Deay C LOAD = 3300pF Each Driver 80 ns TG2 Off to BG2 On Deay C LOAD = 3300pF Each Driver 90 ns BG2 Off to TG2 On Deay C LOAD = 3300pF Each Driver 80 ns Min On-Time for Main Switch in Boost Operation (t ON(M3,MIN) ) Switch M3, C LOAD = 3300pF 200 ns Min On-Time for Synchronous Switch in Buck Operation (t ON(M2,MIN) ) Switch M2, C LOAD = 3300pF 200 ns Min Off-Time for Main Switch in Steady-State Boost Operation Switch M3, C LOAD = 3300pF 230 ns Min Off-Time for Synchronous Switch in Steady-State Buck Operation Switch M2, C LOAD = 3300pF 230 ns Osciator Switch Frequency Range SYNCing or Free Running khz Switching Frequency, f OSC R T = 365k R T = 215k R T = 124k SYNC High Leve for Synchronization 1.3 V SYNC Low Leve for Synchronization 0.5 V SYNC Cock Puse Duty Cyce V SYNC = 0V to 2V % Recommended Min SYNC Ratio f SYNC /f OSC 3/4 CLKOUT Output Votage High V LDO33 V CLKOUT, 1mA Out of CLKOUT Pin, I LDO33 = khz khz khz mv CLKOUT Output Votage Low 1mA Into CLKOUT Pin mv CLKOUT Duty Cyce T J = 40 C T J = 25 C T J = 125 C CLKOUT Rise Time C LOAD = 200pF 20 ns CLKOUT Fa Time C LOAD = 200pF 20 ns CLKOUT Phase Deay SYNC Rising to CLKOUT Rising, f OSC = 100kHz Degree % % % Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: Do not force votage on the V C pin. Note 3: The LT8708E-1 is guaranteed to meet performance specifications from 0 C to 125 C junction temperature. Specifications over the 40 C to 125 C operating junction temperature range are assured by design, characterization and correation with statistica process contros. The LT8708I-1 is guaranteed over the fu 40 C to 125 C junction temperature range. The LT8708H-1 is guaranteed over the fu 40 C to 150 C operating junction temperature range. Note 4: Rise and fa times are measured using 10% and 90% eves. Deay times are measured using 50% eves. Note 5: Do not appy a votage or current source to these pins. They must be connected to capacitive oads ony, otherwise permanent damage may occur. Note 6: Negative votages on the SW1 and SW2 pins are imited, in an appication, by the body diodes of the externa NMOS devices, M2 and M3, or parae Schottky diodes when present. The SW1 and SW2 pins are toerant of these negative votages in excess of one diode drop beow ground, guaranteed by design. Note 7: This IC incudes overtemperature protection that is intended to protect the device during momentary overoad conditions. Junction temperature wi exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reiabiity. Note 8: Do not force votage or current into these pins. 7

8 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. EFFICIENCY (%) Efficiency vs Output Current (Boost Region Page 32) V IN = 11.5V V OUT = 14.5V 20 HCM 10 DCM CCM I OUT (A) G01 EFFICIENCY (%) Efficiency vs Output Current (Buck Region Page 32) 30 V IN = 16V V OUT = 12V 20 HCM 10 DCM CCM I OUT (A) G02 EFFICIENCY (%) Efficiency vs Output Current (Buck-Boost Region Page 32) V IN = 14.5V V OUT = 14.5V HCM DCM CCM I OUT (A) G03 CSPOUTCSNOUT VOLTAGES (mv) CSPOUT CSNOUT Votages (ICP = 1.218V, ICN = 0V) (Five Parts) V C 1.3V CSNOUTCSPOUT VOLTAGES (mv) CSNOUT CSPOUT Votages (ICP = 1.218V, ICN = 0V) (Five Parts) V C = ~1.3V IMON_OP CURRENT () IMON_OP Output Current ICP = ICN = 0.348V TEMPERATURE ( C) G TEMPERATURE ( C) G CSPOUTCSNOUT (mv) G Maximum and Minimum V C vs ICP_ICN (SS = 0) T J = 25 C MAXIMUM V C Maximum and Minimum V C vs SS (ICP = ICN =0.348V) T J = 25 C MAXIMUM V C Maximum and Minimum V C vs SS (ICP or ICN = 1V) T J = 25 C MAXIMUM V C V C (V) V C (V) V C (V) MINIMUM V C 0.5 MINIMUM V C 0.5 MINIMUM V C ICP/ICN VOLTAGE (V) G SS (V) G SS (V) G09 8

9 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C, uness otherwise noted. Load Step (Page 32) V IN = 12V V OUT = 14.5V Load Step (Page 32) V IN = 14.5V V OUT = 14.5V LT8708 I L 10A/DIV LT8708 I L 10A/DIV I L 10A/DIV I L 10A/DIV 500μs/DIV V BAT1 = 12V, V BAT2 REGULATED TO 14.5V LOAD STEP = 10A TO 25A LOAD APPLIED AT V BAT2 WITH BATTERY DISCONNECTED G10 500μs/DIV V BAT1 = 14.5V, V BAT2 REGULATED TO 14.5V LOAD STEP = 10A TO 25A LOAD APPLIED AT V BAT2 WITH BATTERY DISCONNECTED G11 Load Step (Page 32) V IN = 16V V OUT = 14.5V Load Step (Page 33) V IN = 48V V OUT = 14.5V LT8708 I L 10A/DIV I L 10A/DIV LT8708 I L 20A/DIV I L 20A/DIV I L 20A/DIV I L 20A/DIV PHASE 1 PHASE 2 PHASE 3 PHASE 4 500μs/DIV V BAT1 = 16V, V BAT2 REGULATED TO 14.5V LOAD STEP = 10A TO 25A LOAD APPLIED AT V BAT2 WITH BATTERY DISCONNECTED G12 500μs/DIV V BAT1 = 48V, V BAT2 REGULATED TO 14.5V LOAD STEP = 20A TO 55A LOAD APPLIED AT V BAT2 WITH BATTERY DISCONNECTED G13 9

10 PIN FUNCTIONS CLKOUT (Pin 1): Cock Output Pin. Use this pin to synchronize one or more compatibe switching reguator ICs. CLKOUT togges at the same frequency as the interna osciator or as the SYNC pin, but is approximatey 180 out of phase. CLKOUT may aso be used as a temperature monitor since the CLKOUT duty cyce varies ineary with the part s junction temperature. The CLKOUT pin can drive capacitive oads up to 200pF. SS (Pin 2): Soft-Start Pin. Pace a capacitor from this pin to ground. A capacitor identica to the SS pin capacitor used on the master LT8708 is recommended. Upon startup, this pin wi be charged by an interna resistor to 3.3V. SHDN (Pin 3): Shutdown Pin. Tie high to enabe chip. Ground to shut down and reduce quiescent current to a minimum. Do not foat this pin. CSN (Pin 4): The () Input to the Inductor Current Sense and DCM Detect Comparator. CSP (Pin 5): The () Input to the Inductor Current Sense and DCM Detect Comparator. The V C pin votage and buitin offsets between CSP and CSN pins, in conjunction with the R SENSE vaue, set the inductor current trip threshod. It is recommended to use the same vaue R SENSE as the master LT8708. ICN (Pin 6): Negative V OUT Current Command Pin. The votage on this pin determines the negative V OUT current for to reguate to. Connect this pin to the master LT8708 s ICN pin. See the Appications Information section for more information. DIR (Pin 7): Direction pin when MODE is set for DCM (discontinuous conduction mode) or HCM (hybrid conduction mode) operation. Otherwise this pin is ignored. Connect the pin to GND to process power from the V OUT to V IN. Connect the pin to LDO33 to process power from the V IN to V OUT. Drive this pin with the same contro signa, or connect this pin to the same votages as the master LT8708. FBIN (Pin 8): V IN Feedback Pin. This pin is connected to the input of error ampifier EA3. Typicay, connect this pin to LDO33 to disabe the EA3. FBOUT (Pin 9): V OUT Feedback Pin. This pin is connected to the input of error ampifier EA4. Typicay, connect this pin to GND to disabe the EA4. V C (Pin 10): Error Ampifier Output Pin. Tie externa compensation network to this pin. IMON_INP (Pin 11): Positive V IN Current Monitor and Limit Pin. The current out of this pin is 20 pus a current proportiona to the positive average V IN current. IMON_INP aso connects to error ampifier EA5 and can be used to imit the maximum positive V IN current. See the Appications Information section for more information. IMON_INN (Pin 12): Negative V IN Current Monitor and Limit Pin. The current out of this pin is 20 pus a current proportiona to the negative average V IN current. IMON_INN aso connects to error ampifier EA1 and can be used to imit the maximum negative V IN current. See the Appications Information section for more information. RT (Pin 13): Timing Resistor Pin. Adjusts the switching frequency. Pace a resistor from this pin to ground to set the frequency. It is recommended to use the same vaue R T resistor as the master LT8708. Do not foat this pin. SYNC (Pin 14): To synchronize the switching frequency to an outside cock, simpy drive this pin with a cock. The high votage eve of the cock needs to exceed 1.3V, and the ow eve shoud be ess than 0.5V. In a two-phase system, connect this pin to the master LT8708 s CLKOUT pin to have a 180 phase shift. See the Appications Information section for more information. BG1, BG2 (Pin 16, Pin 18): Bottom Gate Drive. Drives the gate of the bottom N-channe MOSFETs between ground and GATEV CC. GATEV CC (Pin 17): Power suppy for bottom gate drivers. Must be connected to the INTV CC pin. Do not power from any other suppy. Locay bypass to GND. It is recommended to use the same vaue bypass cap as the master LT

11 PIN FUNCTIONS BOOST1, BOOST2 (Pin 24, Pin 19): Boosted Foating Driver Suppy. The () termina of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode votage beow GATEV CC up to V IN GATEV CC. The BOOST2 pin swings from a diode votage beow GATEV CC up to V OUT GATEV CC. TG1, TG2 (Pin 23, Pin 20): Top Gate Drive. Drives the top N-channe MOSFETs with votage swings equa to GATEV CC superimposed on the switch node votages. SW1, SW2 (Pin 22, Pin 21): Switch Nodes. The () terminas of the bootstrap capacitors connect here. RVSOFF (Pin 25): Reverse Conduction Disabe Pin. This is an input/output open-drain pin that requires a pu-up resistor. Puing this pin ow disabes reverse current operation. Typicay, connect this pin to the LT8708 s RVSOFF pin. See the Unidirectiona and Bidirectiona Conduction section for more information. VOUTLOMON (Pin 26): V OUT Low Votage Monitor Pin. Connect a ±1% resistor divider between V OUT, VOUTLOMON and GND to set an undervotage eve on V OUT. When V OUT is ower than this eve, reverse conduction is disabed to prevent drawing current from V OUT. See the Appications Information section for more information. VINHIMON (Pin 27): V IN High Votage Monitor Pin. Connect a ±1% resistor divider between V IN, VINHIMON and GND in order to set an overvotage eve on V IN. When V IN is higher than this eve, reverse conduction is disabed to prevent current fow into V IN. See the Appications Information section for more information. ICP (Pin 28): Positive V OUT Current Command Pin. The votage on this pin determines the positive V OUT current for to reguate to. Connect this pin to LT8708 s ICP pin. See the Appications Information section for more information. EXTV CC (Pin 29): Externa V CC Input. When EXTV CC exceeds 6.4V (typica), INTV CC wi be powered from this pin. When EXTV CC is ower than 6.4V, the INTV CC wi be powered from V INCHIP. It is recommended to use the same vaue bypass cap as the master LT8708. CSPOUT (Pin 30): The () Input to the V OUT Current Monitor Ampifier. This pin and the CSNOUT pin measure the votage across the sense resistor, R SENSE2, to provide the V OUT current signas. It is recommended to use the same vaue R SENSE2 between the CSPOUT and CSNOUT pins as the master LT8708. See Appications Information section for proper use of this pin. CSNOUT (Pin 31): The () Input to the V OUT Current Monitor Ampifier. See Appications Information section for proper use of this pin. CSNIN (Pin 32): The () Input to the V IN Current Monitor Ampifier. This pin and the CSPIN pin measure the votage across the sense resistor, R SENSE1, to provide the V IN current signas. Connect this pin to V IN when not in use. See Appications Information section for proper use of this pin. CSPIN (Pin 33): The () Input to the V IN Current Monitor Ampifier. Connect this pin to V IN when not in use. See Appications Information section for proper use of this pin. V INCHIP (Pin 34): Main Input Suppy Pin for the LT It must be ocay bypassed to ground. It is recommended to use the same vaue bypass cap as the master LT8708. INTV CC (Pin 35): 6.35V Reguator Output. Must be connected to the GATEV CC pin. INTV CC is powered from EXTV CC when the EXTV CC votage is higher than 6.4V, otherwise INTV CC is powered from V INCHIP. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor. It is recommended to use the same vaue bypass cap as the master LT8708. SWEN (Pin 36): Switching Reguator Enabe Pin. Tie high through a resistor to enabe the switching. Ground to disabe switching. This pin is pued down during shutdown, a therma ockout or when an interna UVLO (Under Votage Lockout) is detected. Do not foat this pin. Connect this pin to the LT8708 s SWEN pin for synchronized start-up. See the Start-Up: SWEN Pin section for more detais. 11

12 PIN FUNCTIONS MODE (Pin 37): Conduction Mode Seect Pin. The votage appied to this pin sets the conduction mode of the controer. Appy ess than 0.4V to enabe continuous conduction mode (CCM). Appy 0.8V to 1.2V to enabe the hybrid conduction mode (HCM). Appy 1.6V to 2.0V to enabe the discontinuous conduction mode (DCM). Appy more than 2.4V to enabe Burst Mode operation. It is recommended to drive this pin with the same contro signa, or connect this pin to the same vaue resistor dividers or votages as the master LT8708. IMON_OP (Pin 38): Average V OUT Current Reguation Pin. This pin servos to 1.207V to reguate the average output current based on the ICP and ICN votages. Aways connect a resistor in parae with a compensation network from this pin to GND. See the Appications Information section for more information. IMON_ON (Pin 39): Negative V OUT Current Monitor Pin. The current out of this pin is 20 pus a current proportiona to the negative average V OUT current. See the Appications Information section for more information. LDO33 (Pin 40): 3.3V Reguator Output. Bypass this pin to ground with a minimum 0.1µF ceramic capacitor. It is recommended to use the same vaue bypass cap as the master LT8708. GND (Pin 15, Exposed Pad Pin 41): Ground. Tie directy to oca ground pane. 12

13 BLOCK DIAGRAM TO LT8708 s V IN R SENSE1 R SENSE TO LT8708 s SWEN CSNIN CSPIN V INCHIP IMON_INN A3 CSN CSP SWEN A4 A5 RVS CONTROL AND STATE LOGIC BOOST1 TG1 SW1 GATEV CC BG1 GND C B1 M1 M2 D B1 D1 (OPT) D2 (OPT) IMON_INP BOOST CAPACITOR CHARGE CONTROL BG2 RT TO LT8708 s CLKOUT LDO33 LDO33 CLKOUT SYNC DIR MODE 3.3V OSC RVS A2 A6 TO LT8708 s R RVSOFF TO LT8708 s V IN SS UV_INTV CC OT R SHDN1 SHDN START-UP LOGIC UV_LDO33 UV_V IN UV_GATEV CC EA6 TO LT8708 s ICN TO LT8708 s ICP R SHDN V 1.207V EA V SW2 TG2 BOOST2 RVSOFF VINHIMON VOUTLOMON IMON_OP C B2 R HIMON3 R LOMON3 D B2 M4 M3 D3 (OPT) D4 (OPT) R HIMON1 R HIMON2 CSPOUT A1 CSNOUT R SENSE V EA8 ICN ICP IMON_ON V OUT R LOMON1 EA5 IMON_INP R LOMON2 EXTV CC INTV CC 6.3V LDO REG 6.4V EN EN V IN 6.3V LDO REG LDO REG INTERNAL SUPPLY2 INTERNAL SUPPLY1 3.3V LDO REG EA3 EA V 1.207V EA1 FBIN 1.21V IMON_INN FBOUT TO LT8708 s V IN R FBIN1 R FBIN2 R FBOUT1 LDO33 V C R FBOUT2 Figure 1. Bock Diagram F01 13

14 OPERATION The is a high performance 4-switch buck-boost save controer that is paraeed with the master LT8708 to increase power capabiity. Using (s) with the LT8708, an appication can command power to be deivered from V IN to V OUT or from V OUT to V IN as needed. COMMON AND LT8708 FEATURES The and LT8708 share many common functions and features that are aready documented in the LT8708 data sheet. Tabe 1 ists the LT8708 data sheet sections that aso appy to the. For some of these features, additiona specific information is provided in this data sheet, as indicated in Tabe 1. The focus of this data sheet is on how to use the to increase the number of switching phases in an LT8708 based appication. As such, functionaity that is identica in both the LT8708 and wi not necessariy be repeated here. It is assumed that readers of this data sheet are aready famiiar with the LT8708. ADDING PHASES TO AN LT8708 APPLICATION In a mutiphase LT8708 appication, a singe LT8708 is the master of the system. One or more s are saves that provide additiona current as needed. As the master of the mutiphase system, the LT8708 and its respective error ampifiers, determine the current necessary to reguate the V IN votage, V OUT votage, V IN current and V OUT current. The save operates by sensing the I OUT(MASTER) (see Figure 2) and deivering a proportiona amount of I OUT(SLAVE). Again, since I OUT(SLAVE) is proportiona to I OUT(MASTER), the master LT8708 is in contro of setting reguation votages and current imits to the system. Each LT8708 and, connected in parae, is hereon referred to as a phase, the master and save V IN current is referred to as I IN(MASTER) and I IN(SLAVE), respectivey. For mutiphase operation, the LT8708 shoud be configured according to the LT8708 data sheet. Configuration of s shoud foow instructions in this data sheet. Figure 2 shows a simpified drawing of a mutiphase system with one LT8708 and mutipe Tabe 1. LT8708 Data Sheet Sections that Appy to the LT8708 DATA SHEET SECTION Operation Start-Up: SHDN Pin Power Switch Contro Unidirectiona and Bidirectiona Conduction INTV CC /EXTV CC /GATEV CC /LDO33 Power CLKOUT and Temperature Sensing Appications Information Interna Osciator SYNC Pin and Cock Synchronization CLKOUT Pin and Cock Synchronization Inductor Current Sensing and Sope Compensation R SENSE Seection and Maximum Current R SENSE Fitering Inductor (L) Seection Power MOSFET Seection Schottky Diode (D1, D2, D3, D4) Seection Topside MOSFET Driver Suppy (C B1, D B1, C B2, D B2 ) VINHIMON, VOUTLOMON and RVSOFF INTV CC Reguators and EXTV CC Connection LDO33 Reguator Votage Lockouts Junction Temperature Measurement Therma Shutdown Efficiency Considerations Circuit Board Layout Checkist ADDITIONAL INFORMATION IN THIS DATA SHEET s. It iustrates the basic connections needed to add s to a mutiphase system. Adding Phases: The Master LT8708 The master contros the overa current deivered by the mutiphase system. For exampe, the LT8708 contros the V IN and V OUT reguation votages through its FBIN and FBOUT pins. Since the saves primariy dupicate the master s I OUT(MASTER) current, the save s FBIN and FBOUT pins and reated circuitry are typicay not used. See the Error Ampifiers section on how they can affect V C and how to disabe them. Yes Yes Yes Yes 14

15 OPERATION I IN(MASTER) I OUT(MASTER) V IN R IN 4-SWITCH BUCK-BOOST R OUT VOUT CSNIN CSPOUT LD033 CSPIN V INCHIP FBIN LD033 DIR LT8708 MASTER CSNOUT FBOUT IMON_OP IMON_ON IMON_INP IMON_INN SWEN RVSOFF SYNC ICP ICN FWD (>1.6V)/ RVS (<1.2) SWEN LD033 RVSOFF LD033 ICP CLK1 ICN CLK2 SWEN DIR RVSOFF SYNC ICP ICN IMON_OP V INCHIP SLAVE CSPIN CSNIN CSNOUT CSPOUT 4-SWITCH BUCK-BOOST R IN I IN(SLAVE) R OUT I OUT(SLAVE) SWEN RVSOFF CLKn ICP ICN SWEN DIR RVSOFF SYNC ICP ICN IMON_OP V INCHIP SLAVE CSPIN CSNIN CSNOUT CSPOUT 4-SWITCH BUCK-BOOST R IN I IN(SLAVE) R OUT I OUT(SLAVE) F01 Figure 2. Simpified Mutiphase Configuration Diagram 15

16 OPERATION As another exampe, the master LT8708 s current reguation pins (IMON_INP, IMON_INN, IMON_OP, IMON_ON) monitor and imit the per-phase V IN current and V OUT current. The compies with these imits by reguating the I OUT(SLAVE) proportionay. The save s IMON pins are typicay used differenty than on the LT8708. See the I OUT(SLAVE) : Configuration section and the Current Monitoring and Limiting section for more information. Finay, the VINHIMON and VOUTLOMON pins can be used to set up V IN overvotage and V OUT undervotage ockouts on both the LT8708 and the. Typicay, however, divider networks are ony necessary on the master LT8708 since activation of the VINHIMON or VOUTLOMON comparator, on any phase, is communicated to a phases through the shared RVSOFF pin connection. Utiizing the VINHIMON and VOUTLOMON pins on additiona phases offers redundancy for those functions. See the VINHIMON, VOUTLOMON and RVSOFF section for more detais. Adding Phases: The Save Further information about the in Figure 2 is as foows: The ICP and ICN signas connect between the LT8708 and a the s. They are used to deiver the positive and negative I OUT(MASTER) information from the LT8708 to the (s), and hence set the average reguated I OUT(SLAVE). Typicay, the operates by reguating its I OUT(SLAVE) to a proportion of the I OUT(MASTER). The s IMON_OP pin reguates to 1.209V as a part of this reguation. This IMON_OP function differs from the LT8708 in that the s IMON_OP is not part of the positive I OUT(SLAVE) monitor function. Aways connect a resistor in parae with a compensation network from this pin to ground on the. The IMON_ON pin is used to monitor the negative I OUT(SLAVE). The current imiting function of this pin on is disabed and is instead controed by the master LT8708. The LT8708 and empoy different soft-start mechanisms, and the SS pins ramp up differenty. See the Start-Up: Soft-Start of Switching Reguator section for more detais. Apart from the information expained above from Figure 2, a few other pins aso need to be considered when configuring a mutiphase system. A summary of pins and their recommended usage is provided in Tabe 2. Tabe 2. Summary of Pin Connections SHORT PINS BETWEEN LT8708 AND PIN NAME(S) NOTES YES MAYBE NO SWEN, RVSOFF ICP, ICN MODE, DIR FBOUT, IMON_INN IMON_INP VINHIMON, VOUTLOMON Open-drain communication between a phases. Keeps LT8708/ (s) in same states. Send LT8708 s I OUT(SLAVE) information to. Typicay, pins are driven to the same states as LT8708. Disabe these error amps on (s), or set to same or higher imits than LT8708 if used for secondary imits. If using RHCM, connect a resistor and parae fiter capacitor from this pin to ground. Otherwise, disabe this error amp or set to same or higher imit than LT8708 if used for secondary I IN(SLAVE) imit. Comparator states are shared between LT8708/ (s) through RVSOFF pins. Pins on can be disabed or used as redundant detectors. IMON_OP On, connect a resistor and a compensation network from this pin to ground. IMON_ON SS, RT LDO33, INTV CC, GATEV CC Limiting function is disabed on. If using FHCM, connect a resistor in parae with a fiter capacitor from this pin to ground to propery detect ight oad. Use same vaue capacitor, resistor as LT8708. Typicay woud have same capacitors as LT

17 OPERATION In addition, a s V IN and V OUT shoud be connected to the LT8708 s V IN and V OUT, respectivey. See the Quick-Start Mutiphase Setup Guideines section in the Appications Information for a step-by-step design procedure to add s to your system. START-UP Figure 3 iustrates the start-up sequence for the. Start-Up: SWEN Pin The and LT8708 s SWEN pins share the same functionaity. Refer to Start-Up: SWEN Pin of the LT8708 data sheet for more detais. SWEN is internay pued down by the LT8708 and/or (s) when the respective switching reguator is unabe or not ready to operate (see CHIP OFF and SWITCHER OFF 1 states in Figure 3). In a mutiphase system, the SWEN pins are connected between a phases. Due to the interna SWEN pu-down on the LT8708 and, the externa pu-up for the common SWEN node shoud aways have a current imiting resistor. Typicay, the common SWEN node is pued up, through a resistor, to the LT8708 s LDO33 pin. In other cases, the common SWEN node can be digitay driven through a current imiting resistor. SHDN < 1.181V OR V INCHIP < 2.5V OR T JUNCTION > 165 C T JUNCTION < 160 C AND SHDN > 1.221V AND V INCHIP > 2.5V AND ((INTV CC AND GATEV CC < 4.65V) OR LDO33 < 3.04V) CHIP OFF SWITCHER OFF LDOs OFF SWEN PULLED LOW SWITCHER OFF 1 SWITCHER DISABLED INTV CC AND LDO33 OUTPUTS ENABLED SWEN AND SS PULLED LOW (INTV CC AND GATEV CC > 4.81V) AND LDO33 > 3.075V AND SWEN < 0.8V SWITCHER OFF 2 SWITCHER DISABLED INTV CC AND LDO33 OUTPUTS ENABLED SS PULLED LOW INITIALIZE (INTV CC AND GATEV CC > 4.81V) AND LDO33 > 3.075V AND SWEN > 1.208V SS PULLED LOW V C FORCED TO COMMAND NEAR ZERO CURRENT LIMIT SS < 50mV ICP AND ICN < 510mV SOFT-START 2 SS CHARGES UP SS > 0.8V SS CHARGES UP SOFT-START 1 SOFT-START 3 SS CHARGES UP SWITCHER ENABLED M1, M4 ON-TIME SOFT-START V C IS FREE TO SLEW ICP OR ICN > 510mV SS > 1.8V NORMAL MODE NORMAL OPERATION F02 Figure 3. Start-Up Sequence (A Vaues are Typica) 17

18 OPERATION SWEN is used to synchronize the start-up between a phases of the system. If one or more of the phases is unabe to operate, SWEN is pued ow by those chips, thus preventing the entire system from starting. After a phases are ready to operate and SWEN has been pued down beow 0.8V (typica) SWEN rises, due to the puup resistor, and start-up proceeds, for a phases, to the SWITCHER OFF 2 state. When the common SWEN node rises above 1.208V (typica), a the phases proceed to the INITIALIZE state at the same time. Start-Up: Soft-Start of Switching Reguator The soft-start sequence, described in this section, happens independenty and in parae for each phase since each phase has its own SS pin, externa capacitor and reated circuitry. The remaining discussion concerns the soft-start behavior. The LT8708 soft-start differs sighty. In the INITIALIZE state, the SS pin is pued ow to prepare for soft-starting the switching reguator. Aso, V C is forced to command near zero current, and IMON_OP is forced to ~1.209V (typica) to improve the transient behavior when the subsequenty starts switching. After SS has been discharged to ess than 50mV, the SOFT-START 1 state begins. In this state, an integrated 180k (typica) resistor from 3.3V pus SS up. The rising ramp rate of the SS pin votage is set by this 180k resistor and the externa capacitor connected to this pin. After SS reaches 0.2V (typica), the s integrated pu-up resistor is reduced from 180k to 90k to increase the rising ramp rate of the SS pin votage. This ensures that the save chip enters the norma mode in Figure 3 before the master chip, preventing saturation of the reguation oop during start-up. Switching remains disabed unti either (1) ICP or ICN votage becomes higher than 510mV (typica) (SOFT- START 3) or (2) SS reaches 0.8V (typica) (SOFT-START 2). As soon as switching is enabed, V C is free to sew under the contro of the interna error ampifiers (EA1EA6). This aows the average I OUT(SLAVE) to quicky foow the average I OUT(MASTER) without saturating the save s reguation oop. During soft-start the empoys the same switch contro mechanism as the LT8708. See the Switch Contro: Soft-Start section of the LT8708 data sheet for more information. When SS reaches 1.8V (typica), the exits soft-start and enters norma mode. Typica vaues for the externa soft-start capacitor range from 220nF to 2µF. It is recommended to use the same brand and vaue SS capacitor for a the synchronized LT8708/ (s). Using a save SS capacitor vaue significanty higher than the master SS capacitor vaue can resut in undesirabe start-up behavior. CONTROL OVERVIEW The is a save current mode controer that reguates the average I OUT(SLAVE) based on the master s ICP and ICN votages, or equivaenty, the average I OUT(MASTER). The main reguation oop invoves EA6 (see Figure 1). In a simpe exampe of I OUT(SLAVE) reguation, the CSPOUTCSNOUT pins receive the I OUT(SLAVE) feedback signa which is summed with the ICP and ICN signas from the LT8708 to generate the IMON_OP votage using A1 (see Figure 1). The IMON_OP votage is compared to the interna reference votage using EA6. Low IMON_OP votages raise V C, which causes I OUT(SLAVE) to become more positive (or ess negative) and increases the current out of the IMON_OP pin. Conversey, higher IMON_OP votages reduce V C, which causes I OUT(SLAVE) to become ess positive (or more negative) and reduces the current fowing out of the IMON_OP pin. The V C votage typicay has a Min to Max range of about 1.2V. The maximum V C votage commands the most positive inductor current, and thus, commands the most power fow from V IN to V OUT. The minimum V C votage commands the most negative inductor current, and thus, commands the most power fow from V OUT to V IN. V C is the combined output of five interna error ampifiers EA1EA6 as shown in Tabe 3. In a common appication, I OUT(SLAVE) woud be reguated using the main reguation error ampifier EA6, whie error ampifiers EA1 and EA5 are monitoring for excessive input current and EA3 and EA4 are disabed. 18

19 OPERATION Tabe 3. Error Ampifiers (EA1EA6) AMPLIFIER NAME PIN NAME USED TO LIMIT OR REGULATE EA1 IMON_INN Negative I IN(SLAVE) EA3 FBIN V IN Votage EA4 FBOUT V OUT Votage EA5 IMON_INP Positive I IN(SLAVE) EA6 IMON_OP I OUT(SLAVE) Note that the current and power fow can aso be restricted to one direction, as needed, by the seected conduction mode discussed in the Unidirectiona and Bidirectiona Conduction section. POWER SWITCH CONTROL The empoys the same power switch contro as the LT8708 (see Power Switch Contro section of the LT8708 data sheet). Figure 4 shows a simpified diagram of how the four power switches are connected to the inductor, V IN, V OUT and ground. TG1 BG1 V IN M1 SW1 M2 L R SENSE F03 Figure 4. Simpified Diagram of the Buck-Boost Switches M4 SW2 M3 V OUT UNIDIRECTIONAL AND BIDIRECTIONAL CONDUCTION As with the LT8708, the has one bidirectiona and three unidirectiona current conduction modes (CCM, HCM, DCM and Burst Mode operation, respectivey). The s MODE, DIR and RVSOFF pins operate in the same way as in the LT8708 to seect the desired conduction modes. (See the Unidirectiona and Bidirectiona Conduction section of the LT8708 data sheet for detais). In genera, it is highy recommended to keep a phases of an LT8708 system in the same conduction mode. This is done by setting a MODE and DIR pins to the same states, or shorting a MODE pins together and a DIR TG2 BG2 pins together. In addition, the RVSOFF pins of a phases shoud be connected together. Note that when operating in the forward hybrid conduction mode (FHCM), the operation differs sighty from the LT8708. Instead of measuring the ICN pin votage for ight oad detection, the measures the IMON_ON pin. Light oad is detected when IMON_ON is above 245mV (typica). Therefore, FHCM operation requires a resistor, and a parae fiter capacitor, from ground to the IMON_ ON pin of the. Reverse hybrid conduction mode (RHCM) operates identicay in the LT8708 and. See the Unidirectiona and Bidirectiona Conduction: HCM section of the LT8708 data sheet for detais. ERROR AMPLIFIERS Five interna error ampifiers combine to drive V C according to Tabe 4, with the highest priority being at the top. Tabe 4. Error Amp Priorities TYPICAL CONDITION if IMON_INN > 1.21V ese if ese FBIN < 1.205V or FBOUT > 1.207V or IMON_INP > 1.209V or IMON_OP > 1.209V then V C Rises then V C Fas V C Rises PURPOSE to Reduce Negative I IN(SLAVE) to Reduce Positive I IN(SLAVE) or Increase Negative I IN(SLAVE) to Reduce Positive I OUT(SLAVE) or Increase Negative I IN(SLAVE) to Reduce Positive I IN(SLAVE) to Reduce Positive I OUT(SLAVE) Defaut Note that certain error ampifiers are disabed under the conditions shown in Tabe 5. A disabed error ampifier is unabe to affect V C and can be treated as if its associated row is removed from Tabe 4. Tabe 5. Automaticay Disabed Error Amp Conditions ERROR AMP EA1 PIN NAME IMON_INN VOUTLOMON ASSERTED VINHIMON ASSERTED EA3 FBIN 2* RDCM or RHCM EA4 FBOUT 1* 3* EA5 EA6 IMON_INP IMON_OP 19

20 OPERATION A 1* to 3* indicates that the error ampifier isted for that row is disabed under that coumn s condition. The purposes of disabing the respective ampifiers are: 1* This improves transient response when VOUTLOMON de-asserts. 2* This improves transient response when VINHIMON de-asserts. 3* Since power can ony transfer from V OUT to V IN, this prevents higher FBOUT/V OUT votages from interfering with the FBIN/V IN votage reguation. The primary reguation oop for the invoves EA6, which reguates the average I OUT(SLAVE) based on the ICP and ICN input votages. Therefore, the IMON_OP pin must aways have a proper compensation network connected. See the Loop Compensation section for more information. The remaining error ampifiers can be disabed or used to imit their respective votages or currents. When unused, the respective input pin(s) shoud be driven so that they do not interfere with the operation of the remaining ampifiers. Use Tabe 6 as a guide. Tabe 6. Disabing Unused Ampifiers AMPLIFIER NAME PIN NAME TIE TO DISABLE EXAMPLE DISABLED PIN CONNECTION EA1 IMON_INN < 0.9V GND EA3 FBIN > 1.5V LDO33 EA4 EA5 FBOUT IMON_INP < 0.9V GND TRANSFER FUNCTION: I OUT(SLAVE) VS I OUT(MASTER) The reguates I OUT(SLAVE) proportionay to I OUT(MASTER) foowing the transfer functions 1 shown in Figure 5 and Figure 6. The currents are measured (sensed) by the differentia CSPOUTCSNOUT pin votages for each phase and the information is sent from the master to the saves via the ICP and ICN pins. The transfer functions are represented by the save s current sense votage (V (CSPOUTCSNOUT)S ) vs the master s current sense votage (V (CSPOUTCSNOUT)M ). To convert the axes of Figure 5 and Figure 6 to I OUT(SLAVE) vs I OUT(MASTER), simpy divide V (CSPOUTCSNOUT)S (mv) V(CSPOUTCSNOUT)S (mv) Figure 5. Typica V (CSPOUTCSNOUT)S vs V (CSPOUTCSNOUT)M in CCM V (CSPOUTCSNOUT)M (mv) F V (CSPOUTCSNOUT)M (mv) F06 Figure 6. Typica V (CSPOUTCSNOUT)S vs V (CSPOUTCSNOUT)M in FDCM, FHCM and Burst Mode Operation 1 V (CSPOUTCSNOUT)S and V (CSPOUTCSNOUT)M by the save s and master s R SENSE2 vaues, respectivey. Figure 5 shows that increasing the master s average current sense votage V (CSPOUTCSNOUT)M above ±60mV resuts in no additiona current from the save LT As such, the average of V (CSPOUTCSNOUT)M shoud be imited to ±50mV by connecting appropriate resistors from the IMON_OP and IMON_ON pins of the LT8708 to ground (see the I IN and I OUT Current Monitoring and Limiting section of the LT8708 data sheet). 1. The ICP and ICN pins must be connected between the master and save chips. resistors and appropriate parae capacitors are aso required from those pins to ground. 20

21 OPERATION Transfer Function: CCM Figure 5 shows the transfer function of the save s reguated current sense votage (V (CSPOUTCSNOUT)S ) vs the master s current sense votage (V (CSPOUTCSNOUT)M ) when the MODE pin is seecting CCM operation. At ight current eves ( V (CSPOUTCSNOUT)M <20mV), I OUT(SLAVE) is reguated sighty ower than I OUT(MASTER). This ensures that the deivers zero current when the master is deivering zero current and aso ensures a smooth transition from positive to negative I OUT. At high current eves ( V (CSPOUTCSNOUT)M > 20mV), I OUT(SLAVE) is reguated to be the same as I OUT(MASTER), offering good current sharing and therma baance between the phases. Note: If the is configured to be in CCM whie RVSOFF is being pued ow, use the FDCM transfer function in the next section. Transfer Function: DCM, HCM and Burst Mode Operation Figure 6 shows the transfer function of the save s reguated current sense votage (V (CSPOUTCSNOUT)S ) vs the master s current sense votage (V (CSPOUT CSNOUT)M ) when the MODE pin is seecting FDCM, FHCM or Burst Mode operation. The transfer function, in the non-ccm modes, is shown in Figure 6 and has three distinct regions: 1. V (CSPOUTCSNOUT)M < 10mV: In this region, where the master s current is reativey sma, the save phases deiver zero current mV < V (CSPOUTCSNOUT)M < 20.5mV: In this region, where the master s current is moderate, the save phases deiver ess current than the master. The transfer function is hysteretic in this region. Therefore, the save current wi operate from 0mV to 13.5mV or from 6.7mV to 20.5mV if the master s V (CSPOUT CSNOUT)M was most recenty beow 10mV or above 20.5mV, respectivey. 3. V (CSPOUTCSNOUT)M > 20.5mV: In this region of moderate to high current from the master, the save deivers the same current as the master. The transfer function is a mirror image of Figure 6 when operating in the RDCM and RHCM conduction modes for V (CSPOUTCSNOUT)M < 0mV. Simpy mutipy the vaues on the X and Y axes of Figure 6 by 1 to iustrate the transfer function. CURRENT MONITORING AND LIMITING Monitoring: I OUT(SLAVE) The can monitor V OUT current (I OUT(SLAVE) ) in the negative direction. An externa resistor is connected from the IMON_ON pin to ground, and the resuting votage is ineary proportiona to negative I OUT(SLAVE). Unike the LT8708 s IMON_ON pin, the s IMON_ON pin does not reguate or imit I OUT(SLAVE) in the negative direction. See the I IN and I OUT Current Monitoring and Limiting section of the LT8708 data sheet for how to configure the IMON_ON current monitoring. Monitoring and Limiting: I IN(SLAVE) The can monitor V IN current (I IN(SLAVE) ) in both the positive and negative directions by measuring the votage across a current sense resistor R SENSE1 using the CSPIN and CSNIN pins. The votage is ampified and a proportiona current is forced out of the IMON_INP and IMON_INN pins to aow for monitoring and imiting. This function is identica to the LT8708 and more information can be found in the Current Monitoring and Limiting section of the LT8708 data sheet. As described above, the has circuitry aowing for independent input current imiting of each phase. This per-phase current imiting is intended to be secondary to the imits imposed by the master. Typicay, the master is configured to imit its own input current (I IN(MASTER) ) thus imiting the command current to the save. However, since the save has its own independent input current sensing 21

22 OPERATION and imiting circuitry, it can be configured with redundant current imiting. It is recommended to set the save input current imit magnitudes to be the same or higher than those set by the master. See the Appications Information section for more information about the I IN(SLAVE) current monitoring and imiting. As with the LT8708, the requires a resistor and parae fiter capacitor to be connected from ground to the IMON_INP pin when using the RHCM conduction mode. If, in this case, it is aso desired to set the s positive I IN(SLAVE) current imit higher than the LT8708 s positive I IN(MASTER) imit, reduce the vaue of the s R SENSE1 resistor as compared to the LT8708 s R SENSE1 vaue. See Configuring the I IN(SLAVE) Current Limits section for detais. MULTIPHASE CLOCKING A mutiphase appication usuay has switching reguators operating at the same frequency but at different phases to reduce votage and current rippe. The SYNC pin can be used to synchronize the s switching frequency at a specific phase reative to the master LT8708 chip. A separate cock chip, e.g., LTC6902, LTC6909 etc., can be used to generate the cock signas and drive the SYNC pins of the LT8708 and (s). If ony two phases are needed for the mutiphase appication, i.e., 0 and 180, the s SYNC pin can be connected to the LT8708 s CLKOUT pin to obtain the 180 phase shift. The master LT8708 can be synchronized to an externa source or can be free-running based on the externa R T resistor. It is recommended that the is aways synchronized to the same frequency as the LT8708 through the SYNC pin. 22

23 APPLICATIONS INFORMATION This Appications Information section provides additiona detais for setting up a mutiphase appication using the (s) and LT8708. Topics incude quick mutiphase setup guideines, choosing the tota number of phases, cock synchronization, and seection of various externa components. In addition, more information is provided about votage ockouts, current monitoring, PCB ayout considerations. This section wraps up with a design exampe. QUICK-START MULTIPHASE SETUP This section provides a step-by-step summary on how to setup a mutiphase system using the (s) and LT8708. Quick Setup: Design the Master Phase Design the LT8708 appication circuit according to the LT8708 data sheet. Make sure the maximum CSPOUT CSNOUT current sense votage is imited to ±50mV by setting the IMON_OP and IMON_ON resistor vaues equa to or higher than. This is the master phase. Quick Setup: Design the Save Phase(s) Step 1 Power Stage: Appy the same power stage design from the LT8708 appication circuit to the circuit. This incudes the inductor, power MOSFETs and their gate resistors, R SENSE, R SENSE fitering, R SENSE1, R SENSE2, CSPINCSNIN fitering, CSPOUTCSNOUT fitering, topside MOSFET driver suppy (C B1, D B1, C B2, D B2 ) and Schottky diodes D1, D2, D3, D4 (if used). See the C IN and C OUT Seection section on how to optimize the capacitor vaues. Step 2 Periphera Pins: The foowing components shoud be identica on the LT8708 as the : R T resistor SS pin capacitor INTV CC, GATEV CC, V INCHIP and LDO33 pin bypass capacitors Connect identica resistor divider networks on SHDN as we as on VINHIMON and VOUTLOMON (if used). If not used, connect VINHIMON to GND and/or VOUTLOMON to the s LDO33. Connect the s FBOUT pin to GND and the FBIN pin to the s LDO33 node. Step 3 Interconnect: Connect the s ICP, ICN, EXTV CC, SWEN and RVSOFF pins to their counterparts on the LT8708. Connect the same contro signas, or connect the same vaue resistor dividers or votages to the MODE pins and the DIR pins of the LT8708 and LT8708 1, respectivey. Connect the LT8708 s CLKOUT signa or a cock chip s phase shifted cock to the LT s SYNC pin. Step 4 Reguation and Limiting: Connect a resistor in parae with a compensation network from IMON_OP to GND. Connect a resistor in parae with a fiter capacitor from IMON_ON to GND for current monitoring. Connect resistors in parae with fiter capacitors from IMON_INP and IMON_INN to GND, respectivey, to set the magnitudes of the I IN(SLAVE) current imits to be equa to or higher than their counterparts on the LT8708. Step 5: Repeat steps 1 through 4 to add any additiona phases. Quick Setup: Evauation Test and optimize the stabiity of the mutiphase system. See the Loop Compensation section for more detais. CHOOSING THE TOTAL NUMBER OF PHASES In genera, the number of phases needed is seected to meet a mutiphase system s tota power requirement as we as each phase s therma requirement. In genera, for a given appication, the more phases that the system has, the ess power that each phase needs to deiver, and the better the therma performance that each phase has. In many cases, the tota number of phases is seected to optimize the tota input or output RMS current rippe. See the C IN and C OUT Seection section for more detais. 23

24 APPLICATIONS INFORMATION OPERATING FREQUENCY SELECTION 0.60 The uses a constant frequency architecture operating between 100kHz and 400kHz. The shoud be synchronized to the same frequency as the LT8708 by connecting a cock signa to the SYNC pin. An appropriate resistor must be paced from the RT pin to ground. In genera, use the same vaue R T resistor for a the synchronized LT8708 and (s). See the Operating Frequency Seection section of the LT8708 data sheet on how to seect the LT8708 s switching frequency. I(IN,RMS)/IOUT PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE C IN AND C OUT SELECTION 0.15 V IN and V OUT capacitance is necessary to suppress votage rippe caused by discontinuous current moving in and out of the reguator. A parae combination of capacitors is typicay used to achieve high capacitance and ow ESR (equivaent series resistance). Dry tantaum, specia poymer, auminum eectroytic and ceramic capacitors are a avaiabe in surface mount packages. Capacitors with ow ESR and high rippe current ratings, such as OS-CON and POSCAP are aso avaiabe. Ceramic capacitors shoud be paced near the reguator input and output to suppress high frequency switching spikes. A ceramic capacitor, of at east 1µF at the maximum V INCHIP operating votage, shoud aso be paced from V INCHIP to GND as cose to the pins as possibe. Due to their exceent ow ESR characteristics, ceramic capacitors can significanty reduce input rippe votage and hep reduce power oss in the higher ESR buk capacitors. X5R or X7R dieectrics are preferred, as these materias retain their capacitance over wide votage and temperature ranges. Many ceramic capacitors, particuary 0805 or 0603 case sizes, have greaty reduced capacitance at the desired operating votage. C IN and C OUT Seection: V IN Capacitance Discontinuous V IN current is highest in the buck region due to the M1 switch togging on and off. Ensure that the C IN capacitor network has ow enough ESR and is sized to hande the maximum RMS current. Figure 7 shows the tota input capacitor RMS rippe current for one to six phases with the V OUT to V IN ratios in buck operation V OUT /V IN F06 Figure 7. Normaized Tota Input RMS Rippe Current vs V OUT /V IN for One to Six Phases in Buck Operation The tota input RMS rippe current I (IN,RMS) is normaized against the tota output current of the mutiphase system (I OUT ). The graph can be used in pace of tedious cacuations. From the graph, the minimum tota input RMS rippe current can be achieved when the product of the number of phases (N) and the output votage V OUT is approximatey equa to integer mutipes of the input votage V IN or: V OUT /V IN = n/n where n = 1, 2,, N-1 Therefore, the number of phases can be chosen to minimize the input capacitance for given input and output votages. Figure 7 aso shows the maximum tota normaized input RMS current for one to six phases. Choose an adequate C IN capacitor network to hande this RMS current. C IN is aso necessary to reduce the V IN votage rippe caused by discontinuities and rippe of I IN. The effects of ESR and the buk capacitance must be considered when choosing the correct capacitor for a given V IN rippe. A ow ESR input capacitor sized for the maximum RMS current must be used. Add enough ceramic capacitance to 24

25 TYPICAL APPLICATIONS make sure V IN votage rippe is adequatey ow for the appication. C IN and C OUT Seection: V OUT Capacitance Discontinuous V OUT current is highest in the boost region due to the M4 switch togging on and off. Make sure that the C OUT capacitor network has ow enough ESR and is sized to hande the maximum RMS current. Figure 8 shows the output capacitor RMS rippe current for one to six phases with the (V OUT V IN ) to V OUT ratios in boost operations. The tota output RMS rippe current I (OUT,RMS) is normaized against the tota output current of the mutiphase system (I OUT ). The graph can be used in pace of tedious cacuations. From the graph, the minimum tota output RMS rippe current can be achieved when the product of the number of phases (N) and duty cyce (V OUT V IN )/V OUT is approximatey equa to integers or: (V OUT V IN )/V OUT = n/n where n = 1,2,, N-1 Therefore, the number of phases be chosen to minimize the output capacitance for given input and output votages. Figure 8 aso shows the maximum tota normaized output RMS current for one to six phases. Choose an adequate C OUT capacitor network to hande this RMS current. C OUT is aso necessary to reduce the V OUT rippe caused by discontinuities and rippe of I OUT. The effects of ESR and the buk capacitance must be considered when choosing the right capacitor for a given V OUT rippe. A ow ESR input capacitor sized for the maximum RMS current must be used. Add enough ceramic capacitance to make sure V OUT votage rippe is adequate for the appication. Figure 7 and Figure 8 show that the peak tota RMS input current in buck operation and the peak tota RMS output current in boost operation are reduced ineary, inversey proportiona to the number of phases used. It is important to note that the ESR-reated power oss is proportiona to the RMS current squared, and therefore a 3-phase impementation resuts in 90% ess power oss when compared to a singe-phase design. Battery/input protection fuse resistance (if used) PCB trace and connector resistance osses are aso reduced by the reduction of the rippe I (OUT,RMS) /I OUT PHASE 2PHASE 3PHASE 4PHASE 6PHASE (V OUT V IN )/V OUT Figure 8. Normaized Output RMS Rippe Current vs (V OUT V IN )/V IN for One to Six Phases in Boost Operation current in a mutiphase system. The required amount of input and output capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current puses. VINHIMON, VOUTLOMON AND RVSOFF F08 VINHIMON and VOUTLOMON offer the identica functions on the LT8708 and (s). See the VINHIMON, VOUTLOMON and RVSOFF section of the LT8708 data sheet for more detais. If the VINHIMON and VOUTLOMON functions are used on the (s) as redundant monitoring functions, in genera use the same vaue resistor dividers as on the LT8708. If the VINHIMON and/or VOUTLOMON functions are not used on the (s), tie VINHIMON to GND and/or VOUTLOMON to the respective s LDO33 pin. The RVSOFF pin has an interna comparator with a rising threshod of 1.374V (typica) and a faing threshod of 1.209V (typica). A ow state on this pin inhibits reverse current and power fow. It is recommended to tie the RVSOFF pins of a the synchronized LT8708 and (s) together. In a mutiphase system, if one or 25

26 g m = 1m Ω APPLICATIONS INFORMATION more chips VINHIMON or VOUTLOMON comparator is triggered, the RVSOFF pin is pued ow to prevent the entire mutiphase system from deivering reverse current and power. The mutiphase system wi exit the RVSOFF operation when a the VINHIMON and VOUTLOMON comparators are de-asserted. CONFIGURING THE I IN(SLAVE) CURRENT LIMITS As discussed in the Monitoring and Limiting: I IN(SLAVE) section, the can monitor and imit the input current independenty of the master. The current imiting discussed in this section is intended to be secondary, or redundant, since the master is primariy in contro of the amount of current commanded from the save. As shown in Figure 9, the measures I IN(SLAVE) with the CSPIN and CSNIN pins and can independenty monitor and imit the current in both positive and negative directions. The operation of the input current monitor circuits is identica to the LT8708. More information about configuring these circuits can be found in the I IN and I OUT Current Monitoring and Limiting section of the LT8708 data sheet. When setting the I IN(SLAVE) current imits, it is recommended to set them equa to or higher than the magnitudes of the I IN(MASTER) imits. Consider that if the save reaches input current imiting before the master, the save can no onger deiver additiona current as requested by the master. With equa I IN(SLAVE) and I IN(MASTER) imits, sight output current mismatch, and hence sight therma imbaance can sti happen due to device toerance. Bench evauation shoud be carried out to ensure the seected I IN(SLAVE) imits meet the appication s therma and stabiity requirements. REGULATING I OUT(SLAVE) I OUT(SLAVE) : Circuit Description This section describes the contro circuitry in the that reguates the output current I OUT(SLAVE). The master LT8708 sends the ICP and ICN contro signas to the save to set I OUT(SLAVE). See the Transfer Function: I OUT(SLAVE) vs I OUT(MASTER) section for reated information. Figure 10 shows the primary circuits invoved in the reguation of I OUT(SLAVE). Additiona circuitry is shown in Figure 1. I OUT(SLAVE) is reguated by a feedback oop with ICP and ICN setting the desired current. The feedback oop invoves the foowing sections: The V C pin contros the inductor current, thus indirecty controing I OUT(SLAVE). Higher V C votage FROM SYSTEM V IN R SENSE1 I IN(SLAVE) TO CONTROLLER V IN FROM CONTROLLER V OUT R SENSE2 I OUT(SLAVE) TO SYSTEM V OUT CSPIN CSNIN ICP ICN FROM FROM MASTER MASTER 20μA A3 1.21V EA1 TO INDUCTOR CURRENT CONTROL CSPOUT A1 CSNOUT ICP ICN TO INDUCTOR CURRENT CONTROL 20μA IMON_INN 1.209V IMON_INP EA5 V C F08 70μA 1.209V IMON_OP EA6 V C F09 R IMON_INN C IMON_INN R IMON_INP C IMON_INP R IMON_OP C IMON_OP 26 Figure 9. I IN(SLAVE) Current Monitor and Limit Figure 10. I OUT(SLAVE) Current Reguation and Monitor

27 TYPICAL APPLICATIONS resuts in higher I OUT(SLAVE) current and vice versa. V C is driven by error ampifier EA6 during I OUT(SLAVE) reguation. During reguation, the IMON_OP votage is very cose to the EA6 reference of 1.209V. Sma changes in IMON_OP votage make arge adjustments to V C, and thus the I OUT(SLAVE) current. Resistor R SENSE2 converts the I OUT(SLAVE) current into a votage that can be measured by ampifier A1. This votage is denoted as V (CSPOUTCSNOUT)S in Figure 10. Transconductance ampifier A1 makes sure that I OUT(SLAVE) is equa to the current set by the ICP and ICN signas. If I OUT(SLAVE) becomes higher than requested by ICP and ICN, additiona current is deivered out of A1. This raises IMON_OP which reduces V C and reduces I OUT(SLAVE). Conversey, if I OUT(SLAVE) becomes ower than requested by ICP and ICN, the current out of A1 is reduced. This owers IMON_OP which raises V C and increases I OUT(SLAVE). Figure 11 iustrates, in CCM mode, the typica reationship between the master s output current I OUT(MASTER), the resuting ICP and ICN contro votages, and the further resuting I OUT(SLAVE) current. Figure 11 can best be expained with a few exampes. In these exampes, the output current sense resistors are R SENSE2 = 10mΩ for the master and the save devices. First, assume the master s output current I OUT(MASTER) is 4A. This resuts in the master LT8708 measuring a ICP, ICN VOLTAGE (V) V(CSPOUTCSNOUT)S ICN 60 ICP V (CSPOUTCSNOUT)M (mv) F V (CSPOUTCSNOUT)S (mv) current sense votage of V (CSPOUTVCSNOUT)M = 4A 10mΩ = 40mV. Locate 40mV aong the X-axis of Figure 11. The corresponding ICP and ICN votages are ~1V and 0V, respectivey. These ICP and ICN votages are sent from the LT8708 to the. As a resut, the reguates I OUT(SLAVE) to: I OUT(SLAVE) = V (CSPOUT CSNOUT)S R SENSE2 = 40mV (from Figure 10) = 4A 10mΩ Aternativey, if the master s output current I OUT(MASTER) is 2A. Then the master LT8708 wi measure a current sense votage of V (CSPOUTVCSNOUT)M = 2A 10mΩ = 20mV. Locate 20mV aong the X-axis of Figure 11. The corresponding ICP and ICN votages are 0V and ~0.7V, respectivey. These ICP and ICN votages are sent from the LT8708 to the. As a resut, the reguates I OUT(SLAVE) to: I OUT(SLAVE) = V (CSPOUT CSNOUT)S R SENSE2 = 20mV (from Figure 10) 10mΩ = 2A Figure 12 iustrates the reationship between I OUT(MASTER), ICP, ICN and I OUT(SLAVE) in FDCM, FHCM and Burst Mode operation. Use Figure 12, instead of Figure 11, to understand the contro votage reationships when operating in FDCM, FHCM or Burst Mode Operation. Figure 12 can ICP, ICN VOLTAGE (V) V(CSPOUTCSNOUT)S ICN ICP V (CSPOUTCSNOUT)M (mv) F Figure 11. I OUT(SLAVE) Contro Votage Reationships (CCM) Figure 12. I OUT(SLAVE) Contro Votage Reationships (FDCM, FHCM and Burst Mode Operation) 27

28 APPLICATIONS INFORMATION aso be used to understand RDCM and RHCM operation by mutipying the V (CSPOUTCSNOUT)M and the V (CSPOUT CSNOUT)S axis vaues by 1. As mentioned previousy, resistors must be connected from the ICP and ICN pins to ground. Proper resistor connections are required to produce the correct ICP and ICN votages, and resut in the correct I OUT(SLAVE) currents. I OUT(SLAVE) : Configuration I OUT(SLAVE) reguation is the main reguation oop for the and shoud aways be enabed. Therefore, aways connect a resistor in parae with a compensation network from the IMON_OP pin to ground. Note that the IMON_OP pin cannot be used for monitoring the I OUT(SLAVE) current. Figure 5 and Figure 11 show that increasing the master s average current sense votage V (CSPOUTCSNOUT)M above ±60mV resuts in no additiona current from the save. As such, the target average of V (CSPOUT CSNOUT)M shoud be imited to ±50mV by connecting appropriate resistors from the IMON_OP and IMON_ON pins of the LT8708 to ground (see the I IN and I OUT Current Monitoring and Limiting section of the LT8708 data sheet). In addition, the instantaneous differentia votage V (CSPOUTCSNOUT)S shoud remain between 100mV and 100mV due to the imited current that can be driven out of IMON_OP. If the instantaneous V (CSPOUTCSNOUT)S exceeds these imits but the average V (CSPOUTCSNOUT)S is between 50mV and 50mV, consider incuding the current sense fiter described in the I IN and I OUT Current Monitoring and Limiting section of the LT8708 data sheet. The fiter can reduce the instantaneous votage whie preserving the average. In genera, use the same vaue current sense fiter for a the synchronized LT8708 and (s). Finay, IMON_OP shoud be compensated and fitered with capacitor C IMON_OP. At east a few nf of capacitance is usuay necessary. LOOP COMPENSATION To compensate a mutiphase system of the LT8708 and (s), most of the initia compensation component seection can be done by anayzing the individua votage reguator and/or current reguator(s) independenty of each other. Use the tota input and output buk capacitance of the mutiphase system in the stabiity anaysis for each of the foowing steps. 1. Anayze the stabiity of the LT8708 as a singe phase without any additiona phases incuded. This incudes a the reguation oops that wi be used by the master LT8708, such as votage reguation (FBOUT, FBIN) and/or current reguation (IMON_INP, IMON_INN, IMON_OP, IMON_ON). Determine the initia vaues for the V C pin compensation network, and the reevant IMON_XX pin capacitors for the master LT8708. Further adjustment of these vaues wi be done in Step 4. Adjustment to C IN and C OUT may aso be necessary as part of this anaysis. See the Loop Compensation section of the LT8708 data sheet for more detais. LTspice transient simuation can be hepfu for this step. 2. Anayze the stabiity of the I OUT(SLAVE) current reguation oop of a standaone phase. Adjust the V C and IMON_OP compensation networks of the to achieve stabiity and maximum bandwidth. Bench stabiity evauation of a standaone can be carried out by driving the ICP and ICN pins with externa votage sources. A simiar approach to that used for anayzing the LT8708 in constant-current reguation can be empoyed in compensating the standaone current reguator. An IMON_OP capacitor of at east a few nf is necessary to maintain I OUT(SLAVE) reguation oop stabiity. In addition, adding a resistor of a few hundred Ohms in series with this capacitor can often provide additiona phase margin. If any of the I IN(SLAVE) reguation oops, i.e. IMON_INP and IMON_INN, is used for secondary or redundant current imiting, carry out the corresponding stabiity anaysis on the standaone. Use the same 28

29 TYPICAL APPLICATIONS approach that is used for compensating the LT8708 s input current reguation oops. 3. Compete the mutiphase system with the LT8708 and (s). A few nf of capacitance shoud be paced on the ICP and ICN pins near the LT8708 for proper compensation. In addition, adding a few hundred Ohms in series with these capacitors can often provide extra phase margin to the mutiphase system. See Figure 2 as an exampe. 4. Perform the oop stabiity anaysis in simuation and/ or on the bench. Primariy, adjust the LT8708 s V C compensation network for stabiity. A trim pot and seectabe capacitor bank can be used on the V C pin to determine the optima vaues. Typicay, the LT8708 shoud be adjusted to have ower bandwidth than the phases. This can be achieved by increasing the capacitance and/or reducing the series resistance of the LT8708 s V C compensation network. If the LT8708 operates in constant current imit, as set by one or more of the IMON_xx pins, adjust the respective LT8708 IMON_xx fiter capacitors as we to achieve optima oop stabiity. VOLTAGE LOCKOUTS The offers the same votage detectors as the LT8708 to make sure the chip is under proper operating conditions. See the Votage Lockouts section of the LT8708 data sheet for more detais. Athough aowed with a standaone LT8708, a resistor divider connected to the SWEN pins shoud never be used for undervotage detection in a mutiphase system (see the Start-Up: SWEN Pin section for proper ways to connect or drive the SWEN pin in a mutiphase system). Instead, an externa comparator chip can be used to monitor undervotage conditions, and its output drives the common SWEN node in a mutiphase system through a current imiting resistor. CIRCUIT BOARD LAYOUT CHECKLIST The LT8708 s circuit board ayout guideines aso appy to the (s). Refer to the Circuit Board Layout Checkist section of the LT8708 data sheet for detais. In addition: Route the ICP and ICN traces together with minimum PCB trace spacing from the LT8708 to the LT8708 1(s). Avoid having these traces pass through noisy areas, such as switch nodes. Star connect the V IN and V OUT power buses as we as the power GND bus to each LT8708/ (s). Minimize the votage difference between oca V IN, V OUT and power GNDs, respectivey. DESIGN EXAMPLE In this section, we start with the Design Exampe in the LT8708 data sheet, and expand it into a 2-phase reguator. The design requirements from the LT8708 data sheet are isted beow with the tota output current (I OUT ) and the tota input current (I IN ) specifications doubed for two phases. V IN = 8V to 25V V IN_FBIN = 12V (V IN reguation votage set by LT8708 FBIN oop) V OUT_FBOUT = 12V (V OUT reguation votage set by LT8708 FBOUT oop) I OUT(MAX, FWD) = 10A I IN(MAX, RVS) = 6A f =150kHz This design operates in CCM. Maximum ambient temperature = 60 C Use the same R T, R SENSE, R SENSE2 resistors, inductor, externa MOSFETs and capacitors from the Design Exampe of the LT8708 data sheet for. SYNC Pin: Since this is a 2-phase system, the save chip operates 180 out of phase from the master chip. Connect the LT8708 s CLKOUT pin to the s SYNC pin. 29

30 APPLICATIONS INFORMATION MODE Pin: Connect the MODE pin to GND for CCM operation. SWEN and RVSOFF Pins: Connect the SWEN and RVSOFF pins together for the LT8708 and, respectivey. This synchronizes the start-up and operation mode between the two chips. ICP and ICN Pins: Connect two resistors from the ICP and ICN pins to GND, respectivey. Pace them next to the LT8708 chip and route the ICP and ICN traces to the s counterparts, respectivey. R IMON_OP Seection: Connect from IMON_OP to GND for the. R IMON_ON Seection: s IMON_ON is ony used to monitor the I OUT(SLAVE) in the reverse direction. A same vaue resistor of 24.9k from the LT8708 design exampe is seected here to provide an IMON_ON reading on the same scae as the one on the LT8708. R SENSE1, R IMON_INP, R IMON_INN seection: IMON_INP and IMON_INN are used to provide current imits for the ony. They are set to be equa to the maximum per phase V IN current in the forward and reverse directions, respectivey. The maximum save V IN current in the forward direction is: And the maximum save V IN current in the reverse direction is: I IN(MAX,RVS,SLAVE) = I IN(IMON_ON,MASTER) = 3.6A Choose R IMON_INP to be around, so that the LT s V CSPINCSNIN imit becomes 50mV, and the R SENSE1 is cacuated to be: R SENSE1 = 50mV 9A 6mΩ Using the equation given in the I IN and I OUT Current Monitoring and Limiting section of the LT8708 data sheet, R IMON_INP is recacuated to be: R IMON_INP = I IN(MAX, FWD,SLAVE) 1m A Ω 16.2kΩ V R SENSE2 20 And R IMON_INN is cacuated to be: 1.21 R IMON_INN = I IN(MAX, RVS,SLAVE) 1m A Ω 29.4kΩ V R SENSE2 20 FBOUT Pin: Connect FBOUT pin to GND to disabe the FBOUT pin. FBIN Pin: Connect FBIN pin to LDO33 of the to disabe the FBIN pin. I IN(MAX,FWD,SLAVE) = I (IMON_OP,MASTER) V OUT V IN,MIN = 6A 12V = 9A 8V 30

31 TYPICAL APPLICATIONS 2-Phase 12V Bidirectiona Dua Battery System with FHCM and RHCM 10V TO 16V RVS (0V) V BAT1 BATTERY TO DIODE 10Ω TO DIODE DB1 1nF DB2 POWER TRANSFER DECISION LOGIC FWD (3V) DIR_CTRL *SEE THE UNI AND BIDIRECTIONAL CONDUCTION SECTION OF THE LT8708 DATA SHEET IIN LD k M6 C IN4 2 C IN3 CIN1 C IN2 93.1k 27.4k M5 665k 100k 1μF 12.1k M7 100Ω 20k 2mΩ 47nF LD k 127k 4.7μF 100nF M1 TG1 BOOST1 SW1 BG1 CSP CSN CSNIN CSPIN VINCHIP SHDN FBIN VINHIMON DIR SWEN LDO33 RVSOFF MODE 54.9k 0.22μF VC 10k 1nF 33nF LT8708 RT L1 3.3μH M2 M3 1nF 10Ω 2mΩ GND BG2SW2 BOOST2TG2 CSPOUT SS 365k 1μF SYNC 0.22μF M4 CSNOUT EXTVCC VOUTLOMON FBOUT ICP ICN INTVCC GATEV CC IMON_OP IMON_ON IMON_INP IMON_INN CLKOUT 47nF COUT1 100Ω 47nF 2mΩ 23.7k C OUT2 C OUT nF 100k 47nF 220pF 68.1k XOR 2mΩ M8 L2 3.3μH M11 2mΩ 665k 100k C IN5 2 CIN6 1μF 100Ω LD033 47nF LD k 127k 4.7μF C IN7 100nF TG1 BOOST1 SW1 BG1 CSP CSN CSNIN CSPIN VINCHIP SHDN VOUTLOMON FBIN FBOUT VINHIMON SWEN DIR LDO33 RVSOFF MODE TO DIODE DB3 54.9k 0.22μF VC 10k 470pF 8.2nF M9 M10 10Ω 1nF RT 1nF 10Ω 2mΩ GND BG2SW2 BOOST2TG2 CSPOUT SS 365k 1μF SYNC TO DIODE DB4 0.22μF CSNOUT EXTVCC ICP ICN INTVCC GATEV CC IMON_OP IMON_ON IMON_INP IMON_INN CLKOUT 120kHz COUT5 100Ω 47nF 4.7μF C OUT6 COUT nF D B1, D B2, D B3, D B4 : CENTRAL SEMI CMMR1U-02-LTE L1, L2: 3.3μH, WURTH XOR: DIODES INC. 74AHC1G86SE-7 M1M4, M8M11: INFINEON BSC010N04LS C OUT3, C IN3 : 470μF, 50V CIN2, CIN7, COUT1, COUT5: 10µF, 50V, X7R M5M7: T2N7002AK, TOSHIBA C IN4, C IN5, C OUT4, C OUT6 : SUNCON, 18μF, 40V 40HVP18M 154k 20k 200Ω 10nF I OUT VBAT2 C OUT3 133k 12.1k 4.7μF 4.7μF 3.3Ω 23.7k TO LT8708 S BOOST1 D B1 D B2 TO LT8708 S BOOST2 200Ω 4.7μF 3.3Ω DB3 DB4 TO S BOOST1 TO LT7081 S BOOST TA03a 10V TO 16V BATTERY 200Ω 31

32 TYPICAL APPLICATIONS 2-Phase 12V Bidirectiona Dua Battery System with FHCM and RHCM Forward Conduction V BAT1 = ~12V, V BAT2 = ~14V, I OUT = ~30A Reverse Conduction V BAT1 = ~12V, V BAT2 = ~14V, I IN = ~30A I L1 AND I L2 10A/DIV LT8708 SW1 10V/DIV SW1 10V/DIV I L2 I L1 I L1 AND I L2 10A/DIV LT8708 SW1 10V/DIV SW1 10V/DIV I L2 I L1 3μs/DIV TA03b 3μs/DIV TA03c Direction Change with V BAT1 = ~12V, V BAT2 = ~12V DIR 5V/DIV I L1 20A/DIV I L2 20A/DIV 60ms/DIV TA03d 32

33 TYPICAL APPLICATIONS 4-Phase 48V to 12V Bidirectiona Dua Battery System with FHCM and RHCM 24V TO 55V RVS (0V) VBAT1 BATTERY C IN2 TO DIODE 10Ω TO DIODE DB1 1nF DB2 POWER TRANSFER DECISION LOGIC FWD (3V) DIR_CTRL *SEE THE UNI AND BIDIRECTIONAL CONDUCTION SECTION OF THE LT8708 DATA SHEET IIN CIN3 LD k M6 CIN k 16.9k M5 340k 20k C IN1 1μF 18.2k M7 100Ω 20k 5mΩ 47nF LD k 127k 4.7μF 100nF M1 TG1 BOOST1 SW1 BG1CSP CSN CSNIN CSPIN VINCHIP SHDN FBIN VINHIMON DIR SWEN LDO33 RVSOFF MODE 54.9k 0.22μF V C 10k 3.3nF 1nF 68nF LT8708 RT L1 10μH M2 M3 1nF 10Ω 1.5mΩ GND BG2SW2 BOOST2TG2 CSPOUT SS 365k 1μF SYNC 0.22μF CSNOUT EXTVCC VOUTLOMON FBOUT ICP ICN INTVCC GATEV CC IMON_OP IMON_ON IMON_INP IMON_INN CLKOUT 120kHz M4 47nF COUT1 100Ω 47nF 2mΩ 30.1k COUT2 COUT nF 13.3k 17.8k 200Ω 22nF 93.1k 12.1k 220pF 68.1k XOR 5mΩ M8 L2, 10μH M11 2mΩ **4-PHASE CLOCK SIGNALS FROM CLOCK CHIP SUCH AS LTC6909 CLK1 CLK2 CLK3 CLK4 340k 20k CIN5 2 CIN6 1μF 100Ω LD033 47nF LD k 127k 4.7μF CIN7 100nF TG1 BOOST1 SW1 BG1 CSP CSN CSNIN CSPIN VINCHIP SHDN VOUTLOMON FBIN FBOUT VINHIMON SWEN DIR LDO33 RVSOFF MODE TO DIODE DB3 54.9k 0.22μF V C 10k 3.3nF 470pF 12nF M9 M10 10Ω 1nF RT 1nF 10Ω 1.5mΩ GND BG2SW2 BOOST2TG2 CSPOUT SS 365k 1μF SYNC TO DIODE DB4 0.22μF PHASE 3 CSNOUT EXTVCC ICP ICN INTV CC GATEV CC IMON_OP IMON_ON IMON_INP IMON_INN CLKOUT 120kHz PHASE 2 COUT5 100Ω 47nF 4.7μF C OUT6 COUT nF 200Ω 10nF PHASE 4 D B1, D B2, D B3, D B4 : CENTRAL SEMI CMMR1U-02-LTE L1, L2: 10μH, COILCRAFT SER2918H-103KL XOR: DIODES INC. 74AHC1G86SE-7 M1M4, M8M11: INFINEON BSC010N04LS C OUT3, C IN3 : 470μF, 50V CIN2, C IN7, C OUT1, C OUT5 : 10µF, 50V, X7R M5M7: T2N7002AK, TOSHIBA C IN4, C IN5, C OUT6, C OUT7 : SUNCON, 18μF, 40V 40HVP18M I OUT VBAT2 C OUT3 133k 12.1k 4.7μF 4.7μF 3.3Ω 23.7k TO LT8708 S BOOST1 DB1 DB2 TO LT8708 S BOOST2 200Ω 4.7μF 3.3Ω D B3 D B4 TO S BOOST1 TO LT7081 S BOOST2 10V TO 16V BATTERY 200Ω TA04a 33

34 TYPICAL APPLICATIONS 4-Phase 48V to 12V Bidirectiona Dua Battery System with FHCM and RHCM Direction Change Phase 1 to 4 Inductor Current DIR 5V/DIV PHASE 1 I L 20A/DIV PHASE 2 I L 20A/DIV PHASE 1 TO PHASE 4 I L 5A/DIV PHASE 3 I L 20A/DIV 56ms/DIV TA04b 2μs/DIV TA04c 34