LTC1863/LTC /16-Bit, 8-Channel 200ksps ADCs FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM

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1 12-/16-Bit, 8-Chae 2ksps ADCs FEATURES APPLICATIONS Sampe Rate: 2ksps 16-Bit No Missing Codes and ±2LSB Max INL 8-Chae Mutipexer with: Singe Ended or Differentia Inputs and Unipoar or Bipoar Conversion Modes SPI/MICROWIRE Seria I/O Signa-to-Noise Ratio: 89dB Singe 5V Operation On-Chip or Externa Reference Low Power: 1.3mA at 2ksps,.76mA at 1ksps Seep Mode Automatic Nap Mode Between Conversions 16-Pin Narrow SSOP Package Industria Process Contro High Speed Data Acquisition Battery Operated Systems Mutipexed Data Acquisition Systems Imaging Systems DESCRIPTION The LTC 1863/LTC1867 are pin-compatibe, 8-chae 12-/16-bit A/D converters with seria I/O, and an interna reference. The ADCs typicay draw ony 1.3mA from a singe 5V suppy. The 8-chae input mutipexer can be configured for either singe-ended or differentia inputs and unipoar or bipoar conversions (or combinations thereof). The automatic nap and seep modes benefit power sensitive appications. The LTC1867 s DC performance is outstanding with a ±2LSB INL specification and no missing codes over temperature. The signa-to-noise ratio (SNR) for the LTC1867 is typicay 89dB, with the interna reference. Housed in a compact, narrow 16-pin SSOP package, the LTC1863/LTC1867 can be used in space-sensitive as we as ow-power appications. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. BLOCK DIAGRAM 2. Integra Noninearity vs Output Code (LTC1867) CH CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM ANALOG INPUT MUX 12-/16-BIT 2ksps ADC INTERNAL 2.5V REF LTC1863/LTC1867 SERIAL PORT V DD GND SDI SDO SCK CS/CONV V REF INL (LSB) REFCOMP BD OUTPUT CODE GO1 1

2 ABSOLUTE MAXIMUM RATINGS (Note 1, 2) Suppy Votage (V DD )....3V to 6V Anaog Input Votage CH-CH7/COM (Note 3)....3V to (V DD.3V) V REF, REFCOMP (Note 4)....3V to (V DD.3V) Digita Input Votage (SDI, SCK, CS/CONV) (Note 4)....3V to 1V Digita Output Votage (SDO)....3V to (V DD.3V) Power Dissipation... 5mW Operating Temperature Range LTC1863C/LTC1867C/LTC1867AC... C to 7 C LTC1863I/LTC1867I/LTC1867AI... 4 C to 85 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec)...3 C PIN CONFIGURATION CH 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7/COM 8 TOP VIEW 16 V DD 15 GND 14 SDI 13 SDO 12 SCK 11 CS/CONV 1 V REF 9 REFCOMP GN PACKAGE 16-LEAD NARROW PLASTIC SSOP T JMAX = 11 C, θ JA = 95 C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1863CGN#PBF LTC1863CGN#TRPBF Lead Narrow Pastic SSOP C to 7 C LTC1863IGN#PBF LTC1863IGN#TRPBF Lead Narrow Pastic SSOP 4 C to 85 C LTC1867CGN#PBF LTC1867CGN#TRPBF Lead Narrow Pastic SSOP C to 7 C LTC1867IGN#PBF LTC1867IGN#TRPBF Lead Narrow Pastic SSOP 4 C to 85 C LTC1867ACGN#PBF LTC1867ACGN#TRPBF Lead Narrow Pastic SSOP C to 7 C LTC1867AIGN #PBF LTC1867AIGN#TRPBF Lead Narrow Pastic SSOP 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: CONVERTER CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. With externa reference (Notes 5, 6) LTC1863 LTC1867 LTC1867A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resoution Bits No Missing Codes Bits Integra Linearity Error Unipoar (Note 7) Bipoar Differentia Linearity Error ± LSB Transition Noise LSB RMS Offset Error Unipoar (Note 8) Bipoar Offset Error Match Unipoar Bipoar ±1 ±1 ±3 ±4 ±1 ±1 ±4 ±4 ±32 ±64 ±2 ±2 ±2 ±2.5 ±32 ±64 ±2 ±2 LSB LSB LSB LSB LSB LSB 2

3 CONVERTER CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. With externa reference (Notes 5, 6) LTC1863 LTC1867 LTC1867A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Offset Error Drift ±.5 ±.5 ±.5 ppm/ C Gain Error Unipoar Bipoar ±6 ±6 ±96 ±96 ±64 ±64 LSB LSB Gain Error Match ±1 ±4 ±2 LSB Gain Error Tempco Interna Reference Externa Reference ±15 ±2.7 ±15 ±2.7 ±15 ±2.7 ppm/ C ppm/ C Power Suppy Sensitivity V DD = 4.75V 5.25V ±1 ±5 ±5 LSB DYNAMIC ACCURACY (Note 5) LTC1863 LTC1867/LTC1867A SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS SNR Signa-to-Noise Ratio 1kHz Input Signa db S/(ND) Signa-to-(Noise Distortion) Ratio 1kHz Input Signa db THD Tota Harmonic Distortion 1kHz Input Signa, Up to 5th Harmonic db Peak Harmonic or Spurious Noise 1kHz Input Signa db Chae-to-Chae Isoation 1kHz Input Signa db Fu Power Bandwidth 3dB Point MHz ANALOG INPUT The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Anaog Input Range Unipoar Mode (Note 9) V Bipoar Mode ±2.48 V C IN Anaog Input Capacitance for CH to Between Conversions (Sampe Mode) 32 pf CH7/COM During Conversions (Hod Mode) 4 pf t ACQ Sampe-and-Hod Acquisition Time µs Input Leakage Current On Chaes, CHX = V or V DD ±1 µa INTERNAL REFERENCE CHARACTERISTICS (Note 5) LTC1863/LTC1867/LTC1867A PARAMETER CONDITIONS MIN TYP MAX UNITS V REF Output Votage I OUT = V V REF Output Tempco I OUT = ±15 ppm/ C V REF Line Reguation 4.75V V DD 5.25V.43 mv/v V REF Output Resistance I OUT.1mA 6 kω REFCOMP Output Votage I OUT = 4.96 V 3

4 DIGITAL INPUTS AND DIGITAL OUTPUTS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Leve Input Votage V DD = 5.25V 2.4 V V IL Low Leve Input Votage V DD = 4.75V.8 V I IN Digita Input Current V IN = V to V DD ±1 µa C IN Digita Input Capacitance 2 pf V OH High Leve Output Votage (SDO) V DD = 4.75V, I O = 1µA V DD = 4.75V, I O = 2µA 4 V OL Low Leve Output Votage (SDO) V DD = 4.75V, I O = 16µA V DD = 4.75V, I O = 1.6mA I SOURCE Output Source Current SDO = V 32 ma I SINK Output Sink Current SDO = V DD 19 ma Hi-Z Output Leakage Hi-Z Output Capacitance Data Format CS/CONV = High, SDO = V or V DD CS/CONV = High (Note 1) Unipoar Bipoar ±1 15 Straight Binary Two s Compement V V V V µa pf POWER REQUIREMENTS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) SYMBOL PARAMETER CONDITIONS LTC1863/LTC1867/LTC1867A MIN TYP MAX V DD Suppy Votage (Note 9) V I DD Suppy Current f SAMPLE = 2ksps NAP Mode SLEEP Mode ma µa µa P DISS Power Dissipation mw UNITS 4

5 TIMING CHARACTERISTICS LTC1863/LTC1867 The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SAMPLE Maximum Samping Frequency 2 khz t CONV Conversion Time µs t ACQ Acquisition Time µs f SCK SCK Frequency 4 MHz t 1 CS/CONV High Time Short CS/CONV Puse Mode 4 1 ns t 2 SDO Vaid After SCK C L = 25pF (Note 11) ns t 3 SDO Vaid Hod Time After SCK C L = 25pF 5 11 ns t 4 SDO Vaid After CS/CONV C L = 25pF 1 3 ns t 5 SDI Setup Time Before SCK 15 6 ns t 6 SDI Hod Time After SCK 1 4 ns t 7 SLEEP Mode Wake-Up Time C REFCOMP = 1µF, C VREF = 2.2µF 6 ms t 8 Bus Reinquish Time After CS/CONV C L = 25pF 2 4 ns Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime Note 2: A votage vaues are with respect to GND (uness otherwise noted). Note 3: When these pin votages are taken beow GND or above V DD, they wi be camped by interna diodes. This product can hande input currents up to 1mA without atchup. Note 4: When these pin votages are taken beow GND, they wi be camped by interna diodes. This product can hande input currents up to 1mA beow GND without atchup. These pins are not camped to V DD. Note 5: V DD = 5V, f SAMPLE = 2ksps at 25 C, t r = t f = 5ns and V IN = 2.5V for bipoar mode uness otherwise specified. Note 6: Linearity, offset and gain error specifications appy for both unipoar and bipoar modes. The INL and DNL are tested in bipoar mode. Note 7: Integra noninearity is defined as the deviation of a code from a straight ine passing through the actua endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Unipoar offset is the offset votage measured from 1/2LSB when the output code fickers between and 1 for LTC1867 and between and 1 for LTC1863. Bipoar offset is the offset votage measured from 1/2LSB when output code fickers between and for LTC1867, and between and for LTC1863. Note 9: Recommended operating conditions. The input range of ±2.48V for bipoar mode is measured with respect to V IN = 2.5V. Note 1: Guaranteed by design, not subject to test. Note 11: t 2 of 25ns maximum aows f SCK up to 2MHz for rising capture with 5% duty cyce and f SCK up to 4MHz for faing capture (with 3ns setup time for the receiving ogic). 5

6 TYPICAL PERFORMANCE CHARACTERISTICS (LTC1867) Integra Noninearity vs Output Code Differentia Noninearity vs Output Code Histogram for 496 Conversions INL (LBS).5.5 DNL (LSB).5.5 COUNTS OUTPUT CODE OUTPUT CODE CODE GO GO GO3 AMPLITUDE (db) Points FFT Pot (f IN = 1kHz) SNR = 88.8dB SINAD = 87.9dB THD = 95dB f SAMPLE = 2ksps INTERNAL REFERENCE AMPLITUDE (db) Points FFT Pot (f IN = 1kHz, REFCOMP = Externa 5V) SNR = 9dB SINAD = 88.5dB THD = 94dB f SAMPLE = 2ksps V REF = V REFCOMP = EXT 5V RESULTING AMPLITUDE ON SELECTED CHANNEL (db) Crosstak vs Input Frequency ADJACENT PAIR NONADJACENT PAIR FREQUENCY (khz) FREQUENCY (khz) ACTIVE CHANNEL INPUT FREQUENCY (khz) G G G6 1 Signa-to-Noise Ratio vs Frequency 1 Signa-to-(Noise Distortion) vs Input Frequency 2 Tota Harmonic Distortion vs Input Frequency AMPLITUDE (db) AMPLITUDE (db) AMPLITUDE (db) INPUT FREQUENCY (khz) INPUT FREQUENCY (khz) INPUT FREQUENCY (khz) G G G9 6

7 TYPICAL PERFORMANCE CHARACTERISTICS (LTC1863/LTC1867) LTC1863/LTC1867 SUPPLY CURRENT (ma) Suppy Current vs f SAMPLE Suppy Current vs Suppy Votage Suppy Current vs Temperature V DD = 5V SUPPLY CURRENT (ma) V DD = 5V f SAMPLE = 2ksps SUPPLY CURRENT (ma) V DD = 5V f SAMPLE = 2ksps f SAMPLE (ksps) SUPPLY VOLTAGE (V) TEMPERATURE ( C) G G G12 INL (LBS) Integra Noninearity vs Output Code (LTC1863) OUTPUT CODE G13 DNL (LBS) Differentia Noninearity vs Output Code (LTC1863) OUTPUT CODE G14 7

8 PIN FUNCTIONS CHO-CH7/COM (Pins 1-8): Anaog Input Pins. Anaog inputs must be free of noise with respect to GND. CH7/ COM can be either a separate chae or the common minus input for the other chaes. REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass to GND with 1µF tantaum capacitor in parae with.1µf ceramic capacitor (4.96V Nomina). To overdrive REFCOMP, tie V REF to GND. V REF (Pin 1): 2.5V Reference Output. This pin can aso be used as an externa reference buffer input for improved accuracy and drift. Bypass to GND with 2.2µF tantaum capacitor in parae with.1µf ceramic capacitor. CS/CONV (Pin 11): This input provides the dua function of initiating conversions on the ADC and aso frames the seria data transfer. SCK (Pin 12): Shift Cock. This cock synchronizes the seria data transfer. SDO (Pin 13): Digita Data Output. The A/D conversion resut is shifted out of this output. Straight binary format for unipoar mode and two s compement format for bipoar mode. SDI (Pin 14): Digita Data Input Pin. The A/D configuration word is shifted into this input. GND (Pin 15): Anaog and Digita GND. V DD (Pin 16): Anaog and Digita Power Suppy. Bypass to GND with 1µF tantaum capacitor in parae with.1µf ceramic capacitor. TYPICAL CONNECTION DIAGRAM ±2.48V DIFFERENTIAL INPUTS CH CH1 V DD GND 5V CH2 SDI 4.96V SINGLE-ENDED INPUT CH3 CH4 CH5 LTC1863/ LTC1867 SDO SCK CS/CONV DIGITAL I/O CH6 CH7/COM V REF REFCOMP 4.96V 1µF 2.5V 2.2µF TCD TEST CIRCUITS Load Circuits for Access Timing 5V Load Circuits for Output Foat Deay 5V 3k 3k DN DN DN DN 3k C L C L 3k C L C L (A) Hi-Z TO V OH AND V OL TO V OH (B) Hi-Z TO V OL AND V OH TO V OL (A) V OH TO Hi-Z (B) V OL TO Hi-Z TC TC2 8

9 TIMING DIAGRAMS t1 (For Short Puse Mode) t 1 LTC1863/LTC1867 t 2 (SDO Vaid Before SCK ), t 3 (SDO Vaid Hod Time After SCK ) t 2 CS/CONV 5% 5% SCK.4V t 3 SDO 2.4V.4V t 4 (SDO Vaid After CONV ) t 5 (SDI Setup Time Before SCK ), t 6 (SDI Hod Time After SCK ) t 4 t 5 t 6 CS/CONV.4V SCK 2.4V SDO Hi-Z 2.4V.4V SDI 2.4V.4V 2.4V.4V t 7 (SLEEP Mode Wake-Up Time) t 8 (BUS Reinquish Time) t 7 t 8 SCK 5% CS/CONV 2.4V SLEEP BIT (SLP = ) READ-IN CS/CONV 5% SDO 9% Hi-Z 1% 1867 TD APPLICATIONS INFORMATION Overview The LTC1863/LTC1867 are compete, ow power mutipexed ADCs. They consist of a 12-/16-bit, 2ksps capacitive successive approximation A/D converter, a precision interna reference, a configurabe 8-chae anaog input mutipexer (MUX) and a seria port for data transfer. Conversions are started by a rising edge on the CS/CONV input. Once a conversion cyce has begun, it caot be restarted. Between conversions, the ADCs receive an input word for chae seection and output the conversion resut, and the anaog input is acquired in preparation for the next conversion. In the acquire phase, a minimum time of 1.5µs wi provide enough time for the sampe-and-hod capacitors to acquire the anaog signa. During the conversion, the interna differentia 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the east significant bit (LSB). The input is successivey compared with the binary weighted charges suppied by the differentia capacitive DAC. Bit decisions are made by a ow-power, differentia comparator. At the end of a conversion, the DAC output baances the anaog input. The SAR contents (a 12-/16-bit data word) that represent the anaog input are oaded into the 12-/16-bit output atches. 9

10 APPLICATIONS INFORMATION Anaog Input Mutipexer The anaog input mutipexer is controed by a 7-bit input data word. The input data word is defined as foows: SD OS S1 S COM UNI SLP SD = SINGLE/DIFFERENTIAL BIT OS = ODD/SIGN BIT S1 = ADDRESS SELECT BIT 1 S = ADDRESS SELECT BIT COM = CH7/COM CONFIGURATION BIT UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT Exampes of Mutipexer Options 4 Differentia ( ) CH () ( ) () ( ) () ( ) () { { { { CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM 7 Singe-Ended to CH7/COM CH CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM ( ) 8 Singe-Ended CH CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND ( ) Combinations of Differentia and Singe-Ended { { CH CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND ( ) AI1 Changing the MUX Assignment On the Fy 1st Conversion CH2 { CH3 { CH4 CH5 CH7/COM (UNUSED) 2nd Conversion CH7/COM ( ) Tabes 1 and 2 show the configurations when COM =, and COM = 1. Tabe 1. Chae Configuration (When COM =, CH7/COM Pin Is Used as CH7) Chae Configuration SD OS S1 S COM CH CH1 1 CH2 CH3 1 CH4 CH5 1 1 CH6 CH7 1 CH1 CH 1 1 CH3 CH2 1 1 CH5 CH CH7 CH6 1 CH GND 1 1 CH2 GND 1 1 CH4 GND CH6 GND 1 1 CH1 GND CH3 GND CH5 GND CH7 GND Tabe 2. Chae Configuration (When COM = 1, CH7/COM Pin Is Used as COMMON) Chae Configuration SD OS S1 S COM 1 1 CH CH7/COM CH2 CH7/COM CH4 CH7/COM CH6 CH7/COM CH1 CH7/COM CH3 CH7/COM CH5 CH7/COM { { CH2 CH3 CH4 CH AI2 1

11 APPLICATIONS INFORMATION Driving the Anaog Inputs The anaog inputs of the LTC1863/LTC1867 are easy to drive. Each of the anaog inputs can be used as a singeended input reative to the GND pin (CH-GND, CH1-GND, etc) or in pairs (CH and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differentia inputs. In addition, CH7 can act as a COM pin for both singe-ended and differentia modes if the COM bit in the input word is high. Regardess of the MUX configuration, the and inputs are samped at the same instant. Any unwanted signa that is common mode to both inputs wi be reduced by the common mode rejection of the sampe-and-hod circuit. The inputs draw ony one sma current spike whie charging the sampe-and-hod capacitors during the acquire mode. In conversion mode, the anaog inputs draw ony a sma eakage current. If the source impedance of the driving circuit is ow then the LTC1863/LTC1867 inputs can be driven directy. More acquisition time shoud be aowed for a higher impedance source. The foowing ist is a summary of the op amps that are suitabe for driving the LTC1863/LTC1867. More detaied information is avaiabe in the Linear Technoogy data books or Linear Technoogy website. LT17 - Low noise precision ampifier. 2.7mA suppy current ±5V to ±15V suppies. Gain bandwidth product 8MHz. DC appications. LT197 - Low cost, ow power precision ampifier. 3µA suppy current. ±5V to ±15V suppies. Gain bandwidth product.7mhz. DC appications. LT MHz video current feedback ampifier. 1mA suppy current. ±5V to ±15V suppies. Low noise and ow distortion. LTC1863/LTC1867 LT136-37MHz votage feedback ampifier. 3.8mA suppy current. ±5V to ±15V suppies. Good AC/DC specs. LT1363-5MHz votage feedback ampifier. 6.3mA suppy current. Good AC/DC specs. LT1364/LT Dua and quad 5MHz votage feedback ampifiers. 6.3mA suppy current per ampifier. Good AC/DC specs. LT1468-9MHz, 22V/µs 16-bit accurate ampifier LT Dua LT1468 Input Fitering The noise and the distortion of the input ampifier and other circuitry must be considered since they wi add to the LTC1863/LTC1867 noise and distortion. Noisy input circuitry shoud be fitered prior to the anaog inputs to minimize noise. A simpe 1-poe RC fiter is sufficient for many appications. For instance, Figure 1 shows a 5Ω source resistor and a 2pF capacitor to ground on the input wi imit the input bandwidth to 1.6MHz. The source impedance has to be kept ow to avoid gain error and degradation in the AC performance. The capacitor aso acts as a charge reservoir for the input sampe-and-hod and isoates the ADC input from samping gitch sensitive circuitry. High quaity capacitors and resistors shoud be used since these components can add distortion. NPO and siver mica type dieectric capacitors have exceent inearity. Carbon surface mount resistors can aso generate distortion from sef heating and from damage that may occur during sodering. Meta fim surface mount resistors are much ess susceptibe to both probems. 11

12 APPLICATIONS INFORMATION ANALOG INPUT DIFFERENTIAL ANALOG INPUTS 5Ω 5Ω 5Ω 2pF 1µF 1pF 1pF 1pF 1µF 1867 F1a DC Performance One way of measuring the transition noise associated with a high resoution ADC is to use a technique where a DC signa is appied to the input of the ADC and the resuting output codes are coected over a arge number of conversions. For exampe, in Figure 2 the distribution of output codes is shown for a DC input that had been digitized 496 times. The distribution is Gaussian and the RMS code transition noise is about.74lsb. CH GND LTC1863/ LTC1867 REFCOMP Figure 1a. Optiona RC Input Fitering for Singe-Ended Input CH CH1 LTC1863/ LTC1867 REFCOMP 1867 F1b Figure 1b. Optiona RC Input Fitering for Differentia Inputs Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC s frequency response, distortion and noise at the rated throughput. By appying a ow distortion sine wave and anayzing the digita output using an FFT agorithm, the ADC s spectra content can be examined for frequencies outside the fundamenta. Signa-to-Noise Ratio The Signa-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS ampitude of the fundamenta input frequency to the RMS ampitude of a other frequency components at the A/D output. The output is band imited to frequencies from above DC and beow haf the samping frequency. Figure 3 shows a typica SINAD of 87.9dB with a 2kHz samping rate and a 1kHz input. When an externa 5V is appied to REFCOMP (tie V REF to GND), a signa-to-noise ratio of 9dB can be achieved. AMPLITUDE (db) SNR = 88.8dB SINAD = 87.9dB THD = 95dB f SAMPLE = 2ksps INTERNAL REFERENCE FREQUENCY (khz) G4 Figure 3. LTC1867 Nonaveraged 496 Point FFT Pot 12 COUNTS CODE GO3 Figure 2. LTC1867 Histogram for 496 Conversions Tota Harmonic Distortion Tota Harmonic Distortion (THD) is the ratio of the RMS sum of a harmonics of the input signa to the fundamenta itsef. The out-of-band harmonics aias into the frequency band between DC and haf the samping frequency. THD is expressed as: THD = 2og V 2 2 V 3 2 V V N 2 V 1

13 APPLICATIONS INFORMATION where V 1 is the RMS ampitude of the fundamenta frequency and V 2 through V N are the ampitudes of the second through Nth harmonics. Interna Reference The LTC1863/LTC1867 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.5V. It is internay coected to a reference ampifier and is avaiabe at V REF (Pin 1). A 6k resistor is in series with the output so that it can be easiy overdriven by an externa reference if better drift and/or accuracy are required as shown in Figure 4. The reference ampifier gains the V REF votage by 1.638V/V to 4.96V at REFCOMP (Pin 9). This reference ampifier compensation pin, REFCOMP, must be bypassed with a 1µF ceramic or tantaum in parae with a.1µf ceramic for best noise performance. 2.5V 4.96V 1 2.2µF 1µF 9 15 V REF REFCOMP GND R3 REFERENCE AMP R2 R1 6k BANDGAP REFERENCE LTC1863/LTC1867 LTC1863/LTC1867 Digita Interface The LTC1863/LTC1867 have a very simpe digita interface that is enabed by the contro input, CS/CONV. A ogic rising edge appied to the CS/CONV input wi initiate a conversion. After the conversion, taking CS/CONV ow wi enabe the seria port and the ADC wi present digita data in two s compement format in bipoar mode or straight binary format in unipoar mode, through the SCK/SDO seria port. Interna Cock The interna cock is factory trimmed to achieve a typica conversion time of 3µs and a maximum conversion time, 3.5µs, over the fu operating temperature range. The typica acquisition time is 1.1µs, and a throughput samping rate of 2ksps is tested and guaranteed. Automatic Nap Mode The LTC1863/LTC1867 go into automatic nap mode when CS/CONV is hed high after the conversion is compete (see Figure 6). With a typica operating current of 1.3mA and automatic 15µA nap mode between conversions, the power dissipation drops with reduced sampe rate. The ADC ony keeps the V REF and REFCOMP votages active when the part is in the automatic nap mode. The sower the sampe rate aows the power dissipation to be ower (see Figure 5) F4a Figure 4a. LTC1867 Reference Circuit 2. V DD = 5V 5V V IN LT119A-2.5 V OUT 1µF 1 2.2µF 9.1µF 15 V REF LTC1863/ LTC1867 REFCOMP GND 1867 F4b SUPPLY CURRENT (ma) f SAMPLE (ksps) Figure 4b. Using the LT as an Externa Reference G1 Figure 5. Suppy Current vs f SAMPLE 13

14 APPLICATIONS INFORMATION If the CS/CONV returns ow during a bit decision, it can create a sma error. For best performance ensure that the CS/CONV returns ow either within 1ns after the conversion starts (i.e. before the first bit decision) or after the conversion ends. If CS/CONV is ow when the conversion ends, the MSB bit wi appear on SDO at the end of the conversion and the ADC wi remain powered up (see Figure 7). Seep Mode If the SLP = 1 is seected in the input word, the ADC wi enter SLEEP mode and draw ony eakage current (provided that a the digita inputs stay at GND or V DD ). After reease from the SLEEP mode, the ADC need 6ms to wake up (2.2µF/1µF bypass capacitors on V REF / REFCOMP pins). Board Layout and Bypassing To obtain the best performance, a printed circuit board with a ground pane is required. Layout for the printed circuit board shoud ensure digita and anaog signa ines are separated as much as possibe. In particuar, care shoud be taken not to run any digita signa aongside an anaog signa. A anaog inputs shoud be screened by GND. V REF, REFCOMP and V DD shoud be bypassed to this ground pane as cose to the pin as possibe; the ow impedance of the common return for these bypass capacitors is essentia to the ow noise operation of the ADC. The width for these tracks shoud be as wide as possibe. Timing and Contro Conversion start is controed by the CS/CONV digita input. The rising edge transition of the CS/CONV wi start a conversion. Once initiated, it caot be restarted unti the conversion is compete. Figures 6 and 7 show the timing diagrams for two types of CS/CONV puses. Exampe 1 (Figure 6) shows the LTC1863/LTC1867 operating in automatic nap mode with CS/CONV signa staying HIGH after the conversion. Automatic nap mode provides power reduction at reduced sampe rate. The ADCs can aso operate with the CS/CONV signa returning LOW before the conversion ends. In this mode (Exampe 2, Figure 7), the ADCs remain powered up. For best performance, it is recommended to keep SCK, SDI, and SDO at a constant ogic high or ow during acquisition and conversion, even though these signas may be ignored by the seria interface (DON T CARE). Communication with other devices on the bus shoud not coincide with the conversion period (t CONV ). Figures 8 and 9 are the transfer characteristics for the bipoar and unipoar mode. t ACQ 1/f SCK CS/CONV t CONV NAP MODE NOT NEEDED FOR LTC1863 SCK DON'T CARE DON'T CARE SDI DON'T CARE SD S S1 S COM UNI SLP DON'T CARE SDO (LTC1863) Hi-Z MSB D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D SDO (LTC1867) Hi-Z MSB D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D 1867 F6 Figure 6. Exampe 1, CS/CONV Starts a Conversion and Remains HIGH Unti Next Data Transfer. With CS/CONV Remaining HIGH After the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sampe Rate. 14

15 APPLICATIONS INFORMATION LTC1863/LTC1867 CS/CONV t ACQ NOT NEEDED FOR LTC1863 SCK DON'T CARE SDI DON'T CARE SD S S1 S COM UNI SLP DON'T CARE SDO (LTC1863) SDO (LTC1867) Hi-Z Hi-Z t CONV t CONV MSB = D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D MSB = D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D 1867 F7 Figure 7. Exampe 2, CS/CONV Starts a Conversion With Short Active HIGH Puse. With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up. OUTPUT CODE (TWO S COMPLEMENT) BIPOLAR ZERO FS = LSB = FS/2 n 1LSB = (LTC1863) = 1mV 1LSB = (LTC1867) = 62.5µV OUTPUT CODE UNIPOLAR ZERO FS = LSB = FS/2 n 1LSB = (LTC1863) = 1mV 1LSB = (LTC1867) = 62.5µV FS/2 1 V 1 LSB LSB INPUT VOLTAGE (V) FS/2 1LSB 1867 F8 V INPUT VOLTAGE (V) FS 1LSB 1867 F9 Figure 8. LTC1863/LTC1867 Bipoar Transfer Characteristics (Two s Compement) Figure 9. LTC1863/LTC1867 Unipoar Transfer Characteristics (Straight Binary) 15

16 PACKAGE DESCRIPTION Pease refer to for the most recent package drawings. GN Package 16-Lead Pastic SSOP (Narrow.15 Inch) (Reference LTC DWG # Rev B).45 ± * ( ) (.229) REF.254 MIN ( ) ** ( ).165 ±.15 RECOMMENDED SOLDER PAD LAYOUT.25 BSC ( ).15 ±.4 (.38 ±.1) 45 8 TYP ( ).4.98 ( ).16.5 ( ) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.1" (.254mm) PER SIDE.8.12 (.23.35) TYP.25 (.635) BSC GN16 REV B

17 REVISION HISTORY LTC1863/LTC1867 REV DATE DESCRIPTION PAGE NUMBER B 6/14 Fixed the Order Information. 2 C 5/15 Adjusted Notes 3 and 4 to specify input currents up to 1mA. 5 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the intercoection For more of its circuits information as described herein wi not infringe on existing patent rights. 17

18 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC Bit, 4ksps Seria ADC 2mW, Unipoar or Bipoar, Interna Reference, SSOP-16 Package LT146 Micropower Precision Series Reference Bandgap, 13µA Suppy Current, 1ppm/ C, SOT-23 Package LT1468/LT1469 Singe/Dua 9MHz, 22V/µs, 16-Bit Accurate Op Amps Low Input Offset: 75µV/125µV LTC Bit, 2ksps Seria ADC 65mW, Configurabe Bipoar and Unipoar Input Ranges, 5V Suppy LT179 Micropower Low Dropout Reference 6µA Suppy Current, 1ppm/ C, SOT-23 Package LTC185/LTC Bit/12-Bit, 8-Chae, 1.25Msps ADC Parae Output, Programmabe MUX and Sequencer, 5V Suppy LTC1852/LTC Bit/12-Bit, 8-Chae, 4ksps ADC Parae Output, Programmabe MUX and Sequencer, 3V or 5V Suppy LTC186/LTC Bit, 1-/2-Chae 25ksps ADC in MSOP 85µA at 25ksps, 2µA at 1ksps, SO-8 and MSOP Packages LTC186L/LTC1861L 3V, 12-Bit, 1-/2-Chae 15ksps ADC 45µA at 15ksps, 1µA at 1ksps, SO-8 and MSOP Packages LTC1864/LTC Bit, 1-/2-Chae 25ksps ADC in MSOP 85µA at 25ksps, 2µA at 1ksps, SO-8 and MSOP Packages LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Chae 15ksps ADC in MSOP 45µA at 15ksps, 1µA at 1ksps, SO-8 and MSOP Packages 18 Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LT 515 REV C PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 28