LTC1096/LTC1096L LTC1098/LTC1098L Micropower Sampling 8-Bit Serial I/O A/D Converters FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION

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1 Micropower Samping 8-Bit Seria I/O A/D Converters FEATURES n 8 Maximum Suppy Current n na Typica Suppy Current in Shutdown n 5V Operation (LTC96/LTC98) n 3V Operation (LTC96L/LTC98L)(2.65V Min) n Sampe-and-Hod n 6μs Conversion Time n 33kHz Sampe Rate n ±.5LSB Tota Unadjusted Error Over Temp n Direct 3-Wire Interface to Most MPU Seria Ports and A MPU Parae I/O Ports n 8-Pin SO Pastic Package APPLICATIONS n Battery-Operated Systems n Remote Data Acquisition n Battery Monitoring n Battery Gas Gauges n Temperature Measurement n Isoated Data Acquisition L, LT, LTC and LTM are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. DESCRIPTION The LTC 96/LTC96L/ are micropower, 8-bit A/D converters that draw ony 8 of suppy current when converting. They automaticay power down to na typica suppy current whenever they are not performing conversions. They are packaged in 8-pin SO packages and have both 3V (L) and 5V versions. These 8-bit, switched-capacitor, successive approximation ADCs incude sampe-and-hod. The have a singe differentia anaog input. The offer a software seectabe 2-channe MUX. On-chip seria ports aow efficient data transfer to a wide range of microprocessors and microcontroers over three wires. This, couped with micropower consumption, makes remote ocation possibe and faciitates transmitting data through isoation barriers. These circuits can be used in ratiometric appications or with an externa reference. The high impedance anaog inputs and the abiity to operate with reduced spans (beow V fu scae) aow direct connection to sensors and transducers in many appications, eiminating the need for gain stages. TYPICAL APPLICATION μw, S8 Package, 8-Bit A/D Sampes at 2Hz and Runs Off a 5V Battery μf 5V Suppy Current vs Sampe Rate V CC = V REF = 5V ANALOG INPUT V TO 5V RANGE / V SHUTDOWN CC +IN LTC96 IN GND V REF MPU (e.g., 85) P.4 P.3 P.2 SUPPLY CURRENT, I CC () 968 TA. SAMPLE FREQUENCY, f SMPL (khz) 968 TA2 968fc

2 ABSOLUTE MAXIMUM RATINGS (Notes and 2) Suppy Votage (V CC ) to GND...2V Votage Anaog and Reference....3V to V CC +.3V Digita Inputs....3V to 2V Digita Outputs....3V to V CC +.3V Power Dissipation...5mW Storage Temperature Range C to 5 C Operating Temperature LTC96AC/LTC96C/LTC96LC/ LTC98AC/LTC98C/LTC98LC... C to 7 C LTC96AI/LTC96I/LTC96LI/ LTC98AI/LTC98I/LTC98LI... 4 C to 85 C Lead Temperature (Sodering, sec.)... 3 C PIN CONFIGURATION (Note 3) LTC96 LTC98 TOP VIEW TOP VIEW / SHUTDOWN +IN V CC / SHUTDOWN CH V CC (V REF) IN 3 6 CH 3 6 GND 4 5 V REF GND 4 5 D IN N8 PACKAGE 8-LEAD PLASTIC DIP S8 PACKAGE 8-LEAD PLASTIC SOIC T JMAX = 5 C, θ JA = 3 C/W (N8) T JMAX = 5 C, θ JA = 75 C/W (S8) N8 PACKAGE 8-LEAD PLASTIC DIP S8 PACKAGE 8-LEAD PLASTIC SOIC T JMAX = 5 C, θ JA = 3 C/W (N8) T JMAX = 5 C, θ JA = 75 C/W (S8) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC96ACN8#PBF LTC96ACN8#TRPBF LTC96ACN8 8-Lead Pastic DIP C to 7 C LTC96A8#PBF LTC96A8#TRPBF 96A 8-Lead Pastic SOIC C to 7 C LTC96AIN8#PBF LTC96AIN8#TRPBF LTC96AIN8 8-Lead Pastic DIP 4 C to 85 C LTC96AIS8#PBF LTC96AIS8#TRPBF 96AI 8-Lead Pastic SOIC 4 C to 85 C LTC96CN8#PBF LTC96CN8#TRPBF LTC96CN8 8-Lead Pastic DIP C to 7 C LTC968#PBF LTC968#TRPBF 96 8-Lead Pastic SOIC C to 7 C LTC96IN8#PBF LTC96IN8#TRPBF LTC96IN8 8-Lead Pastic DIP 4 C to 85 C LTC96IS8#PBF LTC96IS8#TRPBF 96I 8-Lead Pastic SOIC 4 C to 85 C LTC96L8#PBF LTC96L8#TRPBF 96L 8-Lead Pastic SOIC C to 7 C LTC96LIS8#PBF LTC96LIS8#TRPBF 96LI 8-Lead Pastic SOIC 4 C to 85 C LTC98ACN8#PBF LTC98ACN8#TRPBF LTC98ACN8 8-Lead Pastic DIP C to 7 C LTC98A8#PBF LTC98A8#TRPBF 98A 8-Lead Pastic SOIC C to 7 C LTC98CN8#PBF LTC98CN8#TRPBF LTC98CN8 8-Lead Pastic DIP C to 7 C LTC988#PBF LTC988#TRPBF 98 8-Lead Pastic SOIC C to 7 C LTC98IN8#PBF LTC98IN8#TRPBF LTC98IN8 8-Lead Pastic DIP 4 C to 85 C LTC98IS8#PBF LTC98IS8#TRPBF 98I 8-Lead Pastic SOIC 4 C to 85 C LTC98L8#PBF LTC98L8#TRPBF 98L 8-Lead Pastic SOIC C to 7 C LTC98LIS8#PBF LTC98LIS8#TRPBF 98LI 8-Lead Pastic SOIC 4 C to 85 C 2 968fc

3 ORDER INFORMATION LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC96ACN8 LTC96ACN8#TR LTC96ACN8 8-Lead Pastic DIP C to 7 C LTC96A8 LTC96A8#TR 96A 8-Lead Pastic SOIC C to 7 C LTC96AIN8 LTC96AIN8#TR LTC96AIN8 8-Lead Pastic DIP 4 C to 85 C LTC96AIS8 LTC96AIS8#TR 96AI 8-Lead Pastic SOIC 4 C to 85 C LTC96CN8 LTC96CN8#TR LTC96CN8 8-Lead Pastic DIP C to 7 C LTC968 LTC968#TR 96 8-Lead Pastic SOIC C to 7 C LTC96IN8 LTC96IN8#TR LTC96IN8 8-Lead Pastic DIP 4 C to 85 C LTC96IS8 LTC96IS8#TR 96I 8-Lead Pastic SOIC 4 C to 85 C LTC96L8 LTC96L8#TR 96L 8-Lead Pastic SOIC C to 7 C LTC96LIS8 LTC96LIS8#TR 96LI 8-Lead Pastic SOIC 4 C to 85 C LTC98ACN8 LTC98ACN8#TR LTC98ACN8 8-Lead Pastic DIP C to 7 C LTC98A8 LTC98A8#TR 98A 8-Lead Pastic SOIC C to 7 C LTC98CN8 LTC98CN8#TR LTC98CN8 8-Lead Pastic DIP C to 7 C LTC988 LTC988#TR 98 8-Lead Pastic SOIC C to 7 C LTC98IN8 LTC98IN8#TR LTC98IN8 8-Lead Pastic DIP 4 C to 85 C LTC98IS8 LTC98IS8#TR 98I 8-Lead Pastic SOIC 4 C to 85 C LTC98L8 LTC98L8#TR 98L 8-Lead Pastic SOIC C to 7 C LTC98LIS8 LTC98LIS8#TR 98LI 8-Lead Pastic SOIC 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: This product is ony offered in trays. For more information go to: RECOMMENDED OPERATING CONDITIONS LTC96/LTC98 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC Suppy Votage LTC96 LTC98 V CC = 5V Operation f Cock Frequency V CC = 5V 25 5 khz t CYC Tota Cyce Time LTC96, f = 5kHz LTC98, f = 5kHz t hdi Hod Time, D IN After V CC = 5V 5 ns t su Setup Time Before First (See Operating Sequence) V CC = 5V, LTC96 V CC = 5V, LTC98 t WAKEUP Wake-Up Time Before First After First (See Figure LTC96 Operating Sequence) Wake-Up Time Before MSBF Bit (See Figure 2 LTC98 Operating Sequence) V CC = 5V, LTC96 μs V CC = 5V, LTC98 μs t sudi Setup Time, D IN Stabe Before V CC = 5V 4 ns t WH High Time V CC = 5V.8 μs t WL Low Time V CC = 5V.8 μs 9 6 V V μs μs ns ns 968fc 3

4 RECOMMENDED OPERATING CONDITIONS LTC96/LTC98 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t WH High Time Between Data Transfer Cyces V CC = 5V μs t WL Low Time During Data Transfer LTC96, f = 5kHz LTC98, f = 5kHz V CC = 3V Operation f Cock Frequency V CC = 3V khz t CYC Tota Cyce Time LTC96, f = 25kHz LTC98, f = 25kHz t hdi Hod Time, D IN After V CC = 3V 45 ns t su Setup Time Before First (See Operating Sequence) V CC = 3V, LTC96 V CC = 3V, LTC98 t WAKEUP Wake-Up Time Before First After First (See Figure LTC96 Operating Sequence) Wake-Up Time Before MSBF Bit (See Figure 2 LTC98 Operating Sequence) V CC = 3V, LTC96 μs V CC = 3V, LTC98 μs t sudi Setup Time, D IN Stabe Before V CC = 3V μs t WH High Time V CC = 3V.6 μs t WL Low Time V CC = 3V.6 μs t WH High Time Between Data Transfer Cyces V CC = 3V 2 μs t WL Low Time During Data Transfer LTC96, f = 25kHz LTC98, f = 25kHz LTC96L/LTC98L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC Suppy Votage V f Cock Frequency V CC = 2.65V khz t CYC Tota Cyce Time LTC96L, f = 25kHz LTC98L, f = 25kHz t hdi Hod Time, D IN After V CC = 2.65V 45 ns t su Setup Time Before First (See Operating Sequence) V CC = 2.65V, LTC96L V CC = 2.65V, LTC98L t WAKEUP Wake-Up Time Before First After First (See Figure LTC96L Operating Sequence) Wake-Up Time Before MSBF Bit (See Figure 2 LTC98L Operating Sequence) V CC = 2.65V, LTC96L μs V CC = 2.65V, LTC98L μs t sudi Setup Time, D IN Stabe Before V CC = 2.65V μs t WH High Time V CC = 2.65V.6 μs t WL Low Time V CC = 2.65V.6 μs t WH High Time Between Data Transfer Cyces V CC = 2.65V 2 μs t WL Low Time During Data Transfer LTC96L, f = 25kHz LTC98L, f = 25kHz μs μs μs μs μs μs μs μs μs μs μs μs μs μs 4 968fc

5 CONVERTER AND MULTIPLEXER CHARACTERISTI LTC96/LTC98 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 5V, V REF = 5V, f = 5kHz, uness otherwise noted. LTC96A/LTC98A LTC96/LTC98 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resoution (No Missing Code) 8 8 Bits Offset Error ±.5 ±.5 LSB Linearity Error (Note 4) ±.5 ±.5 LSB Fu Scae Error ±.5 ±. LSB Tota Unadjusted Error (Note 5) V REF = 5.V ±.5 ±. LSB Anaog Input Range (Notes 6, 7).5V to V CC +.5V V REF Input Range (Notes 6, 7) 4.5 V CC 6V 6V < V CC 9V, LTC96.5V to V CC +.5V.5V to 6V V V Anaog Input Leakage Current (Note 8) ±. ±. LTC96/LTC98 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 3V, V REF = 2.5V, f = 25kHz, uness otherwise noted. LTC96A/LTC98A LTC96/LTC98 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resoution (No Missing Code) 8 8 Bits Offset Error ±.75 ±. LSB Linearity Error (Notes 4, 9) ±.5 ±. LSB Fu-Scae Error ±. ±. LSB Tota Unadjusted Error (Notes 5, 9) V REF = 2.5V ±. ±.5 LSB Anaog Input Range (Notes 6, 7).5V to V CC +.5V V REF Input Range (Notes 6, 7, 9) 3V V CC 6V.5V to V CC +.5V V Anaog Input Leakage Current (Notes 8, 9) ±. ±. LTC96L/LTC98L The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 2.65V, V REF = 2.5V, f = 25kHz, uness otherwise noted. LTC96A/LTC98A PARAMETER CONDITIONS MIN TYP MAX UNITS Resoution (No Missing Code) 8 Bits Offset Error ±. LSB Linearity Error (Note 4) ±. LSB Fu-Scae Error ±. LSB Tota Unadjusted Error (Note 5) V REF = 2.5V ±.5 LSB Anaog Input Range (Notes 6, 7).5V to V CC +.5V V REF Input Range (Note 6) 2.65V V CC 4.V.5V to V CC +.5V V Anaog Input Leakage Current (Note 8) ±. 968fc 5

6 DIGITAL AND DC ELECTRICAL CHARACTERISTI LTC96/LTC98 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 5V, V REF = 5V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Leve Input Votage V CC = 5.25V 2. V V IL Low Leve Input Votage V CC = 4.75V.8 V I IH High Leve Input Current V IN = V CC 2.5 I IL Low Leve Input Current V IN = V 2.5 V OH High Leve Output Votage V CC = 4.75V, I O = V CC = 4.75V, I O = 36 V OL Low Leve Output Votage V CC = 4.75V, I O =.6mA.4 V I OZ Hi-Z Output Leakage V IH ±3. I SOURCE Output Source Current V OUT = V 25 ma I SINK Output Sink Current V OUT = V CC 45 ma I REF Reference Current = V CC t CYC 2μs, f 5kHz t CYC = 29μs, f = 5kHz I CC Suppy Current = V CC. 3. LTC96, t CYC 2μs, f 5kHz LTC96, t CYC = 29μs, f = 5kHz LTC98, t CYC 2μs, f 5kHz LTC98, t CYC = 29μs, f = 5kHz LTC96/LTC98 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 3V, V REF = 2.5V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Leve Input Votage V CC = 3.6V.9 V V IL Low Leve Input Votage V CC = 3V.45 V I IH High Leve Input Current (Note 9) V IN = V CC 2.5 I IL Low Leve Input Current (Note 9) V IN = V 2.5 V OH High Leve Output Votage V CC = 3V, I O = V CC = 3V, I O = 36 V OL Low Leve Output Votage V CC = 3V, I O = 4.3 V I OZ Hi-Z Output Leakage (Note 9) V IH ±3. I SOURCE Output Source Current (Note 9) V OUT = V ma I SINK Output Sink Current (Note 9) V OUT = V CC 5 ma I REF Reference Current (Note 9) = V CC t CYC 2μs, f 5kHz t CYC = 58μs, f = 25kHz I CC Suppy Current (Note 9) = V CC. 3. LTC96, t CYC 2μs, f 5kHz LTC96, t CYC = 58μs, f = 25kHz LTC98, t CYC 2μs, f 5kHz LTC98, t CYC = 58μs, f = 25kHz V V V V 6 968fc

7 DIGITAL AND DC ELECTRICAL CHARACTERISTI LTC96L/LTC98L The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 2.65V, V REF = 2.5V, f = 25kHz, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Leve Input Votage V CC = 3.6V.9 V V IL Low Leve Input Votage V CC = 2.65V.45 V I IH High Leve Input Current V IN = V CC 2.5 I IL Low Leve Input Current V IN = V 2.5 V OH High Leve Output Votage V CC = 2.65V, I O = V CC = 2.65V, I O = 36 V OL Low Leve Output Votage V CC = 2.65V, I O = 4.3 V I OZ Hi-Z Output Leakage High ±3. I SOURCE Output Source Current V OUT = V ma I SINK Output Sink Current V OUT = V CC 5 ma I REF Reference Current = V CC t CYC 2μs, f 5kHz t CYC = 58μs, f = 25kHz I CC Suppy Current = V CC. 3. LTC96L, t CYC 2μs, f 5kHz LTC96L, t CYC = 58μs, f = 25kHz LTC98L, t CYC 2μs, f 5kHz LTC98L, t CYC = 58μs, f = 25kHz AC CHARACTERISTI LTC96/LTC98 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 5V, V REF = 5V, f = 5kHz, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t SMPL Anaog Input Sampe Time See Operating Sequence.5 Cyces f SMPL(MAX) Maximum Samping Frequency 33 khz t CONV Conversion Time See Operating Sequence 8 Cyces t ddo Deay Time, to Data Vaid See Test Circuits 2 45 ns t dis Deay Time, to Hi-Z See Test Circuits 7 45 ns t en Deay Time, to Enabe See Test Circuits 6 25 ns t hdo Time Output Data Remains Vaid After C LOAD = pf 8 ns t f Fa Time See Test Circuits 7 25 ns t r Rise Time See Test Circuits 25 ns C IN Input Capacitance Anaog Inputs On Channe Anaog Inputs Off Channe Digita Input 5 pf 25 5 V V pf pf 968fc 7

8 AC CHARACTERISTI LTC96/LTC98 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 3V, V REF = 2.5V, f = 25kHz, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t SMPL Anaog Input Sampe Time See Operating Sequence.5 Cyces f SMPL(MAX) Maximum Samping Frequency 6.5 khz t CONV Conversion Time See Operating Sequence 8 Cyces t ddo Deay Time, to Data Vaid See Test Circuits (Note 9) 5 ns t dis Deay Time, to Hi-Z See Test Circuits (Note 9) 22 8 ns t en Deay Time, to Enabe See Test Circuits (Note 9) 6 48 ns t hdo Time Output Data Remains Vaid After C LOAD = pf 4 ns t f Fa Time See Test Circuits (Note 9) 7 25 ns t r Rise Time See Test Circuits (Note 9) 5 5 ns C IN Input Capacitance Anaog Inputs On Channe Anaog Inputs Off Channe Digita Input 5 pf LTC96L/LTC98L The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. V CC = 2.65V, V REF = 2.5V, f = 25kHz, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t SMPL Anaog Input Sampe Time See Operating Sequence.5 Cyces f SMPL(MAX) Maximum Samping Frequency 6.5 khz t CONV Conversion Time See Operating Sequence 8 Cyces t ddo Deay Time, to Data Vaid See Test Circuits 5 ns t dis Deay Time, to Hi-Z See Test Circuits 22 8 ns t en Deay Time, to Enabe See Test Circuits 6 48 ns t hdo Time Output Data Remains Vaid After C LOAD = pf 4 ns t f Fa Time See Test Circuits 7 25 ns t r Rise Time See Test Circuits 5 2 ns C IN Input Capacitance Anaog Inputs On Channe Anaog Inputs Off Channe Digita Input 5 pf pf pf pf pf Note : Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A votage vaues are with respect to GND. Note 3: For the 8-ead PDIP, consut the factory. Note 4: Linearity error is specifi ed between the actua and points of the A/D transfer curve. Note 5: Tota unadjusted error incudes offset, fu scae, inearity, mutipexer and hod step errors. Note 6: Two on-chip diodes are tied to each reference and anaog input which wi conduct for reference or anaog input votages one diode drop beow GND or one diode drop above V CC. This spec aows 5mV forward bias of either diode. This means that as ong as the reference or 8 anaog input does not exceed the suppy votage by more than 5mV, the output code wi be correct. To achieve an absoute V to 5V input votage range wi therefore require a minimum suppy votage of 4.95V over initia toerance, temperature variations and oading. For 5.5V < V CC 9V, reference and anaog input range cannot exceed 5.55V. If reference and anaog input range are greater than 5.55V, the output code wi not be guaranteed to be correct. Note 7: The suppy votage range for the LTC96L/LTC98L is from 2.65V to 4V. The suppy votage range for the LTC96 is from 3V to 9V, but the suppy votage range for the LTC98 is ony from 3V to 6V. Note 8: Channe eakage current is measured after the channe seection. Note 9: These specifi cations are either correated from 5V specifi cations or guaranteed by design. 968fc

9 TYPICAL PERFORMANCE CHARACTERISTI SUPPLY CURRENT, I CC () Suppy Current vs Cock Rate for Active and Shutdown Modes = V V CC = 9V = V CC V CC = 5V FREQUENCY (khz) 968 G SUPPLY CURRENT, I CC () Suppy Current vs Suppy Votage Active and Shutdown Modes V REF = 2.5V ACTIVE MODE = SHUTDOWN MODE = V CC SUPPLY VOLTAGE,V CC (V) 968 G2 SUPPLY CURRENT, I CC () Suppy Current vs Sampe Frequency LTC96. V CC = V REF = 5V SAMPLE FREQUENCY, f SMPL (khz) 968 G3 MAGNITUDE OF OFFSET CHANGE (LSB = /256 V REF ) Change in Offset vs Reference Votage LTC96 V CC = 5V F = 5kHz REFERENCE VOLTAGE (V) 968 G4 MAGNITUDE OF OFFSET CHANGE (LSB) Change in Offset vs Suppy Votage V REF = 2.5V F = khz SUPPLY VOLTAGE, V CC (V) 968 G5 CHANGE IN LINEARITY (LSB) O.5 Change in Linearity vs Reference Votage LTC96 V CC = 5V F = 5kHz REFERENCE VOLTAGE (V) 968 G6 CHANGE IN LINEARTY (LSB) Change in Linearity vs Suppy Votage V REF = 2.5V F = khz SUPPLY VOLTAGE, V CC (V) 968 G7 CHANGE IN GAIN (LSB) Change in Gain vs Suppy Votage V REF = 2.5V F = khz SUPPLY VOLTAGE, V CC (V) 968 G8 CHANGE IN GAIN (LSB) O.5 Change in Gain vs Reference Votage LTC96 V CC = 5V F = 5kHz VOLTAGE REFERENCE (V) 968 G9 968fc 9

10 TYPICAL PERFORMANCE CHARACTERISTI MAXIMUM CLOCK FREQUENCY* (MHz) Maximum Cock Frequency vs Source Resistance V CC = V REF = 5V V IN + INPUT INPUT R SOURCE MAXIMUM CLOCK FREQUENCY (MHz) Maximum Cock Frequency vs Suppy Votage V REF = 2.5V LOGIC THRESHLD (V) Digita Input Logic Threshod vs Suppy Votage R SOURCE (kω) 968 G SUPPLY VOLTAGE (V) 968 G SUPPLY VOLTAGE, V CC (V) 968 G2 WAKE-UP TIME (μs) Wake-Up Time vs Suppy Votage V REF = 2.5V MINIMUM WAKE-UP TIME (μs) Minimum Wake-Up Time vs Source Resistance V REF = 5V V IN R SOURCE + + LEAKAGE CURRENT (na). Input Channe Leakage Current vs Temperature V REF = 5V V CC = 5V ON CHANNEL OFF CHANNEL SUPPLY VOLTAGE, V CC (V) 968 G3 R SOURCE (kω) 968 G TEMPERATURE ( C) 968 G5 MINIMUM CLOCK FREQUENCY (khz) Minimum Cock Frequency for.lsb Error vs Temperature ENOBs vs Frequency FFT Pot V REF = 5V V CC = 5V TEMPERATURE ( C) 968 G6 * Maximum frequency represents the cock frequency at which a.lsb shift in the error at any code transition from its.75mhz vaue is fi rst detected. As the frequency is decreased from 5kHz, minimum frequency (Δerror.LSB) represents the frequency at which a.lsb shift in any code transition from its 5kHz vaue is first detected. ENOBs V CC = V REF = 5V f SMPL = 3.25kHz FREQUENCY (khz) 968 G7 AMPLITUDE (db) V CC = V REF = 5V f SMPL = 3.25kHz f IN = 5.8kHz FREQUENCY (khz) 968 G8 968fc

11 PIN FUNCTIONS /SHDN (Pin ): Chip Seect Input. A ogic ow on this input enabes the. A ogic high on this input disabes the and disconnects the power to the. IN + (Pin 2): Anaog Input. This input must be free of noise with respect to GND. IN (Pin 3): Anaog Input. This input must be free of noise with respect to GND. GND (Pin 4): Anaog Ground. GND shoud be tied directy to an anaog ground pane. V REF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. (Pin 6): Digita Data Output. The A/D conversion resut is shifted out of this output. (Pin 7): Shift Cock. This cock synchronizes the seria data transfer. V CC (Pin 8): Power Suppy Votage. This pin provides power to the A/D converter. It must be free of noise and rippe by bypassing directy to the anaog ground pane. /SHDN (Pin ): Chip Seect Input. A ogic ow on this input enabes the. A ogic high on this input disabes the and disconnects the power to the. CH (Pin 2): Anaog Input. This input must be free of noise with respect to GND. CH (Pin 3): Anaog Input. This input must be free of noise with respect to GND. GND (Pin 4): Anaog Ground. GND shoud be tied directy to an anaog ground pane. D IN (Pin 5): Digita Data Input. The mutipexer address is shifted into this pin. (Pin 6): Digita Data Output. The A/D conversion resut is shifted out of this output. (Pin 7): Shift Cock. This cock synchronizes the seria data transfer. V CC (V REF )(Pin 8): Power Suppy Votage. This pin provides power and defines the span of the A/D converter. It must be free of noise and rippe by bypassing directy to the anaog ground pane. 968fc

12 BLOCK DIAGRAM V CC (V CC /V REF ) (D IN ) BIAS AND SHUTDOWN CIRCUIT SERIAL PORT IN + (CH) C SAMPLE IN (CH) SAR MICROPOWER COMPARATOR + CAPACITIVE DAC 968 BD GND V REF PIN NAMES IN PARENTHESES REFER TO THE TEST CIRCUITS On and Off Channe Leakage Current Load Circuit for t ddo, t r and t f 5V I ON A ON CHANNEL.4V I OFF A 3kΩ TEST POINT OFF CHANNEL pf 968 TC2 POLARITY 968 TC 2 968fc

13 TEST CIRCUITS Votage Waveforms for Deay Time, t ddo Votage Waveforms for Rise and Fa Times, t r, t f V IL t ddo V OH V OL V OH V OL t r t f 968 TC4 968 TC3 Load Circuit for t dis and t en Votage Waveforms for t dis 2.V TEST POINT 3k pf 5V t dis WAVEFORM 2, t en t dis WAVEFORM 968 TC5 WAVEFORM (SEE NOTE ) WAVEFORM 2 (SEE NOTE 2) t dis 9% % NOTE : WAVEFORM IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 968 TC6 968fc 3

14 TEST CIRCUITS Votage Waveforms for t en t WAKEUP V OL B7 t en 968 TC7 D IN START V OL B7 t en 968 TC fc

15 APPLICATIONS INFORMATION OVERVIEW The / are 8-bit micropower, switched-capacitor A/D converters. These samping ADCs typicay draw 2 of suppy current when samping up to 33kHz. Suppy current drops ineary as the sampe rate is reduced (see Suppy Current vs Sampe Rate on the first page of this data sheet). The ADCs automaticay power down when not performing conversion, drawing ony eakage current. They are packaged in 8-pin SO packages. The LTC96L/LTC98L operate on a singe suppy ranging from 2.65V to 4V. The LTC96 operates on a singe suppy ranging from 3V to 9V whie the LTC98 operates from 3V to 6V suppies. The / comprise an 8-bit, switched-capacitor ADC, a sampe-and-hod and a seria port (see Bock Diagram). Athough they share the same basic design, the LTC96(L) and LTC98(L) differ in some respects. The LTC96(L) has a differentia input and has an externa reference input pin. It can measure signas foating on a DC common mode votage and can operate with reduced spans down to 25mV. Reducing the span aows it to achieve mv resoution. The LTC98(L) has a 2-channe input mutipexer and can convert either channe with respect to ground or the difference between the two. SERIAL INTERFACE The LTC98(L) communicates with microprocessors and other externa circuitry via a synchronous, haf dupex, 4-wire seria interface whie the LTC96(L) uses a 3-wire interface (see Operating Sequence in Figures and 2). Power Down and Wake-Up Time The LTC96(L)/LTC98(L) draw power when the pin is ow and shut themseves down when that pin is high. In order to have a correct conversion resut, a μs wake-up time must be provided from faing to the first faing cock () after the first rising for the LTC96(L) and from faing to the MSBF bit faing for the LTC98(L) (see Operating Sequence). If the LTC96(L)/LTC98(L) are running with cock frequency ess than or equa to khz, the wake-up time is inherenty provided. Exampe Two cases are shown at right to iustrate the reationship among wake-up time, setup time and frequency for the LT96(L). In Case the cock frequency is khz. One cock cyce is μs which can be the wake-up time, whie haf of that can be the setup time. In Case 2 the cock frequency is 5kHz, haf of the cock cyce pus the setup time (=μs) can be the wake-up time. If the frequency is higher than khz, Figure shows the reationship between the wake-up time and setup time. t su t su t WAKEUP t WAKEUP μs NULL BIT Case. Timing Diagram Case 2. Timing Diagram B7 968 AI Ex 968fc 5

16 APPLICATIONS INFORMATION t CYC POWER DOWN t su t WAKEUP HI-Z NULL BIT B7 (MSB) B6 B5 t CONV B4 B3 B2 B B Hi-Z t CYC POWER DOWN Hi-Z t su t WAKEUP NULL BIT B7 (MSB) B6 B5 t CONV B4 B3 B2 B B B B2 B3 B4 B5 B6 B7* Hi-Z 968 F *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. Figure. LTC96(L) Operating Sequence The wake-up time is inherenty provided for the LTC98(L) with setup time = μs (see Figure 2). Data Transfer The synchronizes the data transfer with each bit being transmitted on the faing edge and captured on the rising edge in both transmitting and receiving systems. The LTC98(L) first receives input data and then transmits back the A/D conversion resut (haf dupex). Because of the haf dupex operation, D IN and may be tied together aowing transmission over just three wires:, and DATA (D IN / ). Data transfer is initiated by a faing chip seect () signa. After fas the LTC98(L) ooks for a start bit. After the start bit is received, the 3-bit input word is shifted into the D IN input which configures the LTC98(L) and starts the conversion. After one nu bit, the resut of the conversion SHIFT MUX ADDRESS IN D IN D IN 2 2 NULL BIT SHIFT A/D CONVERSION RESULT OUT 968 AI is output on the ine. At the end of the data exchange shoud be brought high. This resets the LTC98(L) in preparation for the next data exchange. The LTC96(L) does not require a confi guration input word and has no D IN pin. A faing initiates data transferas shown in the LTC96(L) operating sequence. After fas, the first puse enabes. After one nu bit, the A/D conversion resut is output on the ine. Bringing high resets the LTC96(L) for the next data exchange fc

17 APPLICATIONS INFORMATION MSB-FIRST DATA (MSBF = ) t CYC t WAKEUP POWER DOWN t su START ODD/ SIGN D IN DON'T CARE HI-Z SGL/ DIFF MSBF NULL BIT B7 B6 B5 B4 B3 B2 B B* Hi-Z (MSB) t SMPL t CONV MSB-FIRST DATA (MSBF = ) t CYC t WAKEUP POWER DOWN t su START ODD/ SIGN D IN DON'T CARE HI-Z SGL/ DIFF MSBF NULL BIT B7 B6 B5 B4 B3 B2 B B B B2 B3 B4 B5 B6 B7* Hi-Z (MSB) t SMPL t CONV 968 F2 *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. Figure 2. LTC98(L) Operating Sequence Exampe: Differentia Inputs (CH +, CH ) Input Data Word The LTC96(L) requires no D IN word. It is permanenty confi gured to have a singe differentia input. The conversion resut, in which output on the ine is MSB-first sequence, foowed by LSB sequence providing easy interface to MSB- or LSB-fi rst seria ports. The LTC98(L) cocks data into the D IN input on the rising edge of the cock. The input data words are defined as foows: Start Bit The first ogica one cocked into the D IN input after goes ow is the start bit. The start bit initiates the data transfer. The LTC98(L) wi ignore a eading zeros which precede this ogica one. After the start bit is received, the remaining bits of the input word wi be cocked in. Further inputs on the D IN pin are then ignored unti the next cyce. START SGL/ DIFF ODD/ SIGN MSBF MUX MSB-FIRST/ ADDRESS LSB-FIRST 968 AI2 968fc 7

18 APPLICATIONS INFORMATION Mutipexer (MUX) Address The bits of the input word foowing the START bit assign the MUX configuration for the requested conversion. For a given channe seection, the converter wi measure the votage between the two channes indicated by the + and signs in the seected row of the foowintg tabes. In singe-ended mode, a input channes are measured with respect to GND. Unipoar Transfer Curve The LTC96(L)/LTC98(L) are permanenty configured for unipoar ony. The input span and code assignment for this conversion type are shown in the foowing figures for a 5V reference. Unipoar Transfer Curve LTC98(L) Channe Seection SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE MSB-First/LSB-First (MSBF) MUX ADDRESS SGL/DIFF ODD/SIGN CHANNEL # GND 968 AI3 V LSB VREF 2LSB V REF LSB VREF V IN 968 AI4 The output data of the LTC98(L) is programmed for MSB-fi rst or LSB-fi rst sequence using the MSBF bit. When the MSBF bit is a ogica one, data wi appear on the ine in MSB-fi rst format. Logica zeros wi be fied in indefinitey foowing the ast data bit. When the MSBF bit is a ogica zero, LSB-first data wi foow the norma MSB-first data on the ine. (see Operating Sequence) OUTPUT CODE Unipoar Output Code INPUT VOLTAGE V REF LSB V REF 2LSB LSB V INPUT VOLTAGE (V REF = 5.V) 4.985V 4.969V.95V V 968 AI5 Operation with D IN and Tied Together The LTC98(L) can be operated with D IN and tied together. This eiminates one of the ines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a singe wire. The processor pin connected to this data ine shoud be configurabe as either an input or an output. The LTC98(L) wi take contro of 8 968fc

19 APPLICATIONS INFORMATION MSBF BIT LATCHED BY LTC98(L) DATA (D IN / ) START SGL/DIFF ODD/SIGN MSBF B7 B6 MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC98(L) PROCESSOR MUST RELEASE DATA LINE AFTER 4TH RISING AND BEFORE THE 4TH FALLING Figure 3. LTC98(L) Operation with D IN and Tied Together LTC98(L) CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU LTC98(L) TAKES CONTROL OF DATA LINE ON 4TH FALLING 968 F3 the data ine and drive it ow on the 4th faing edge after the start bit is received (see Figure 3). Therefore the processor port ine must be switched to an input before this happens, to avoid a conf ict. In the Typica Appications section, there is an exampe of interfacing the LTC98(L) with D IN and tied together to the Inte 85 MPU. ACHIEVING MICROPOWER PERFORMANCE With typica operating currents of 4 and automatic shutdown between conversions, the LTC96/LTC98 achieves extremey ow power consumption over a wide range of sampe rates (see Figure 4). In systems that convert continuousy, the LTC96/LTC98 wi draw SUPPLY CURRENT, I CC (). V CC = 5V Sampe Rate, f SAMPLE (khz) 968 F4 Figure 4. Automatic Power Shutdown Between Conversions Aows Power Consumption to Drop with Sampe Rate its norma operating power continuousy. Figure 5 shows that the typica current varies from 4 at cock rates beow 5kHz to at 5kHz. Severa things must be taken into account to achieve such a ow power consumption. SUPPLY CURRENT, I CC () k k k M CLOCK FREQUENCY (Hz) 968 F5 Figure 5. After a Conversion, When the Microprocessor Drives High, the ADC Automaticay Shuts Down Unti the Next Conversion. The Suppy Current, Which Is Very Low During cconversions, Drops to Zero in Shutdown Shutdown 4.2 SUPPLY CURRENT vs CLOCK RATE FOR ACTIVE AND SHUTDOWN MODES V CC = 5V ACTIVE ( LOW) SHUTDOWN ( HIGH) Figures and 2 show the operating sequence of the LTC96/LTC98. The converter draws power when the pin is ow and powers itsef down when that pin is high. If the pin is not taken to ground when it is ow and not taken to suppy votage when it is high, the input buffers 968fc 9

20 APPLICATIONS INFORMATION of the converter wi draw current. This current may be arger than the typica suppy current. It is worthwhie to bring the pin a the way to ground when it is ow and a the way to suppy votage when it is high to obtain the owest suppy current. When the pin is high (= suppy votage), the converter is in shutdown mode and draws ony eakage current. The status of the D IN and input have no effect on suppy current during this time. There is no need to stop D IN and with = high, except the MPU may benefit. Minimize Low Time In systems that have significant time between conversions, owest power drain wi occur with the minimum ow time. Bringing ow, waiting μs for the wake-up time, transferring data as quicky as possibe, and then bringing it back high wi resut in the owest current drain. This minimizes the amount of time the device draws power. Even though the device draws more power at high cock rates, the net power is ess because the device is on for a shorter time. Loading Capacitive oading on the digita output can increase power consumption. A pf capacitor on the pin can more than doube the suppy current drain at a 5kHz cock frequency. An extra or so of current goes into charging and discharging the oad capacitor. The same goes for digita ines driven at a high frequency by any ogic. The CxVxf currents must be evauated and the troubesome ones minimized. Lower Suppy Votage For ower suppy votages, LTC offers the LTC96L/ LTC98L. These pin compatibe devices offer specified performance to 2.65V MIN suppy. OPERATING ON OTHER THAN 5V SUPPLIES The LTC96 operates from 3V to 9V suppies and the LTC98 operates from 3V to 6V suppies. To operate the LTC96/LTC98 on other than 5V suppies, a few things must be kept in mind. 2 Wake-Up Time A μs wake-up time must be provided for the ADCs to convert correcty on a 5V suppy. The wake-up time is typicay ess than 3μs over the suppy votage range (see typica curve of Wake-Up Time vs Suppy Votage). With μs wake-up time provided over the suppy range, the ADCs wi have adequate time to wake up and acquire input signas. Input Logic Leves The input ogic eves of, and D IN are made to meet TTL on 5V suppy. When the suppy votage varies, the input ogic eves aso change. For the LTC96/LTC98 to sampe and convert correcty, the digita inputs have to meet ogic ow and high eves reative to the operating suppy votage (see typica curve of Digita Input Logic Threshod vs Suppy Votage). If achieving micropower consumption is desirabe, the digita inputs must go raito-rai between suppy votage and ground (see ACHIEVING MICROPOWER PERFORMANCE section). Cock Frequency The maximum recommended cock frequency is 5kHz for the LTC96/LTC98 running off a 5V suppy. With the suppy votage changing, the maximum cock frequency for the devices aso changes (see the typica curve of Maximum Cock Rate vs Suppy Votage). If the maximum cock frequency is used, care must be taken to ensure that the device converts correcty. Mixed Suppies It is possibe to have a microprocessor running off a 5V suppy and communicate with the LTC96/LTC98 operating on 3V or 9V suppies. The requirement to achieve this is that the outputs of, and D IN from the MPU have to be abe to trip the equivaent inputs of the ADCs and the output of from the ADCs must be abe to togge the equivaent input of the MPU (see typica curve of Digita Input Logic Threshod vs Suppy Votage). With the LTC96 operating on a 9V suppy, the output of may go between V and 9V. The 9V output may damage the MPU running off a 5V suppy. The way to get around this possibiity is to have a resistor divider on 968fc

21 APPLICATIONS INFORMATION (Figure 6) and connect the center point to the MPU input. It shoud be noted that to get fu shutdown, the input of the LTC96/LTC98 must be driven to the V CC votage. This woud require adding a eve shift circuit to the signa in Figure 6. OPTIONAL LEVEL SHIFT DIFFERENTIAL INPUTS COMMON MODE RANGE V TO 6V +IN IN GND V CC V REF Figure 6. Interfacing a 9V Powered LTC96 to a 5V System BOARD LAYOUT CONSIDERATIONS 9V LTC96 Grounding and Bypassing The LTC96(L)/LTC98(L) shoud be used with an anaog ground pane and singe point grounding techniques. The GND pin shoud be tied directy to the ground pane. 9V 5k 6V 4.7μF 5k MPU (e.g. 85) P.4 P.3 P.2 5V 968 F6 The V CC pin shoud be bypassed to the ground pane with a μf tantaum with eads as short as possibe. If power suppy is cean, the LTC96(L)/LTC98(L) can aso operate with smaer.μf surface mount or ceramic bypass capacitors. A anaog inputs shoud be referenced directy to the singe point ground. Digita inputs and outputs shoud be shieded from and/or routed away from the reference and anaog circuitry. SAMPLE-AND-HOLD Both the LTC96(L) and the LTC98(L) provide a buit-in sampe-and-hod (S&H) function to acquire signas. The S&H of the LTC96(L) acquires input signas from + input reative to input during the t WAKEUP time (see Figure ). However, the S&H of the LTC98(L) can sampe input signas in the singe-ended mode or in the differentia inputs during the t SMPL time (see Figure 7). Singe-Ended Inputs The sampe-and-hod of the LTC98(L) aows conversion of rapidy varying signas. The input votage is samped during the t SMPL time as shown in Figure 7. The samping interva begins as the bit preceding the MSBF bit is shifted SAMPLE HOLD "+" INPUT MUST SETTLE DURING THIS TIME t SMPL t CONV D IN START SGL/DIFF MSBF DON'T CARE B7 ST BIT TEST " " INPUT MUST SETTLE DURING THIS TIME "+" INPUT " " INPUT Figure 7. LTC98(L) + and Input Setting Windows 968 F7 968fc 2

22 APPLICATIONS INFORMATION in and continues unti the faing edge after the MSBF bit is received. On this faing edge, the S&H goes into hod mode and the conversion begins. Differentia Inputs With differentia inputs, the ADC no onger converts just a singe votage but rather the difference between two votages. In this case, the votage on the seected + input is sti samped and hed and therefore may be rapidy time varying just as in singe-ended mode. However, the votage on the seected input must remain constant and be free of noise and rippe throughout the conversion time. Otherwise, the differencing operation may not be performed accuratey. The conversion time is 8 cyces. Therefore, a change in the input votage during this interva can cause conversion errors. For a sinusoida votage on the input this error woud be: V ERROR (MAX) = V PEAK 2 π f( ) 8/f Where f( ) is the frequency of the input votage, V PEAK is its peak ampitude and f is the frequency of the. In most cases V ERROR wi not be signifi cant. For a 6Hz signa on the input to generate a /4LSB error (5mV) with the converter running at = 5kHz, its peak vaue woud have to be 75mV. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the anaog inputs of the LTC96(L)/ LTC98(L )have capacitive switching input current spikes. These current spikes sette quicky and do not cause a probem. However, if arge source resistances are used or if sow setting op amps drive the inputs, care must be taken to ensure that the transients caused by the current spikes sette competey before the conversion begins. + Input Setting The input capacitor of the LTC96(L) is switched onto + input during the wake-up time (see Figure ) and sampes the input signa within that time. However, the input capacitor of the LTC98(L) is switched onto + input during the sampe phase (t SMPL, see Figure 7). The sampe phase is.5 cyces before conversion starts. The votage on the + input must sette competey within 22 t WAKEUP or t SMPL for the LTC96(L) or the LTC98(L) respectivey. Minimizing R SOURCE + and C wi improve the input setting time. If a arge + input source resistance must be used, the sampe time can be increased by using a sower frequency. Input Setting At the end of the t WAKEUP or t SMPL, the input capacitor switches to the input and conversion starts (see Figures and 7). During the conversion the + input votage is effectivey hed by the sampe-and-hod and wi not affect the conversion resut. However, it is critica that the input votage settes competey during the first cyce of the conversion time and be free of noise. Minimizing R SOURCE and C2 wi improve setting time. If a arge input source resistance must be used, the time aowed for setting can be extended by using a sower frequency. Input Op Amps When driving the anaog inputs with an op amp it is important that the op amp sette within the aowed time (see Figure 7). Again, the + and input samping times can be extended as described above to accommodate sower op amps. Most op amps, incuding the LT6 and LT43 singe suppy op amps, can be made to sette we even with the minimum setting windows of 3μs ( + input) which occur at the maximum cock rate of 5kHz. Source Resistance The anaog inputs of the LTC96/LTC98 ook ike a 25pF capacitor (C IN ) in series with a 5Ω resistor (R ON ) as shown in Figure 8. C IN gets switched between the seected + and inputs once during each conversion cyce. V IN + V IN R SOURCE + R SOURCE + INPUT C INPUT C2 R ON = 5Ω Figure 8. Anaog Input Equivaent Circuit LTC96 LTC98 C IN = 25pF 968 F8 968fc

23 APPLICATIONS INFORMATION Large externa source resistors and capacitances wi sow the setting of the inputs. It is important that the overa RC time constants be short enough to aow the anaog inputs to competey sette within the aowed time. RC Input Fitering It is possibe to fi ter the inputs with an RC network as shown in Figure 9. For arge vaues of C F (e.g., μf), the capacitive input switching currents are averaged into a net DC current. Therefore, a fiter shoud be chosen with a sma resistor and arge capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximatey I DC = 25pF(V IN /t CYC ) and is roughy proportiona to V IN. When running at the minimum cyce time of 29μs, the input current equas 4.3 at V IN = 5V. In this case, a fiter resistor of 39Ω wi cause.lsb of fuscae error. If a arger fiter resistor must be used, errors can be eiminated by increasing the cyce time. V IN R FILTER I DC C FILTER Figure 9. RC Input Fitering Input Leakage Current Input eakage currents can aso create errors if the source resistance gets too arge. For instance, the maximum input eakage specification of (at 25 C) f owing through a source resistance of 3.9k wi cause a votage drop of 3.9mV or.2lsb. This error wi be much reduced at ower temperatures because eakage drops rapidy (see typica curve of Input Channe Leakage Current vs Temperature). REFERENCE INPUTS The votage on the reference input of the LTC96 defines the votage span of the A/D converter. The reference input transient capacitive switching currents due to the switched-capacitor conversion technique (see Figure ). During each bit test of the conversion (every cyce), a + LTC F9 capacitive current spike wi be generated on the reference pin by the ADC. These current spikes sette quicky and do not cause a probem. Using a sower wi aow more time for the reference to sette. Even at the maximum rate of 5kHz most references and op amps can be made to sette within the R OUT V REF 2μs bit time. REF + 5 GND 4 LTC96 EVERY CYCLE R ON 5pF TO 3pF 968 F Figure. Reference Input Equivaent Circuit Reduced Reference Operation The minimum reference votage of the LTC98 is imited to 3V because the V CC suppy and reference are internay tied together. However, the LTC96 can operate with reference votages beow V. The effective resoution of the LTC96 can be increased by reducing the input span of the converter. The LTC96 exhibits good inearity and gain over a wide range of reference votages (see typica curves of Linearity and Fu Scae Error vs Reference Votage). However, care must be taken when operating at ow vaues of V REF because of the reduced LSB step size and the resuting higher accuracy requirement paced on the converter. The foowing factors must be considered when operating at ow V REF vaues.. Offset 2. Noise 3. Conversion speed ( frequency) Offset with Reduced V REF The offset of the LTC96 has a arger effect on the output code when the ADC is operated with reduced reference votage. The offset (which is typicay a fi xed votage) becomes a arger fraction of an LSB as the size of the LSB is reduced. The typica curve of Unadjusted Offset Error vs Reference Votage shows how offset in LSBs is 968fc 23

24 APPLICATIONS INFORMATION reated to reference votage for a typica vaue of V OS. For exampe, a V OS of 2mV which is.lsb with a 5V reference becomes.5lsb with a V reference and 2.5LSBs with a.2v reference. If this offset is unacceptabe, it can be corrected digitay by the receiving system or by offsetting the input of the LTC96. Noise with Reduced V REF The tota input referred noise of the LTC96 can be reduced to approximatey mv peak-to-peak using a ground pane, good bypassing, good ayout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but wi become a arger fraction of an LSB as the size of the LSB is reduced. For operation with a 5V reference, the mv noise is ony.5lsb peak-to-peak. In this case, the LTC96 noise wi contribute virtuay no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirabe jitter in the output code. For exampe, with a V reference, this same mv noise is.25lsb peak-to-peak. This wi reduce the range of input votages over which a stabe output code can be achieved by LSB. If the reference is further reduced to 2mV, the mv noise becomes equa to.25lsbs and a stabe code may be difficut to achieve. In this case averaging readings may be necessary. This noise data was taken in a very cean setup. Any setupinduced noise (noise or rippe on V CC, V REF or V IN ) wi add to the interna noise. The ower the reference votage to be used, the more critica it becomes to have a cean, noise free setup. Conversion Speed with Reduced V REF With reduced reference votages the LSB step size is reduced and the LTC96 interna comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum frequency when ow vaues of V REF are used. Input Divider It is OK to use an input divider on the reference input of the LTC96 as ong as the reference input can be made 24 to sette within the bit time at which the cock is running. When using a arger vaue resistor divider on the reference input the input shoud be matched with an equivaent resistance. Bypassing Reference Input with Divider Bypassing the reference input with a divider is aso possibe. However, care must be taken to make sure that the DC votage on the reference input wi not drop too much beow the intended reference votage. AC PERFORMANCE Two commony used fi gures of merit for specifying the dynamic performance of the ADCs in digita signa processing appications are the signa-to-noise ratio (SNR) and the effective number of bits (ENOBs). Signa-to-Noise Ratio The signa-to-noise ratio (SNR) is the ratio between the RMS ampitude of the fundamenta input frequency to the RMS ampitude of a other frequency components at the A/D output. This incudes distortion as we as noise products and for this reason it is sometimes referred to as signa-to-noise + distortion [S/(N + D)]. The output is band imited to frequencies from DC to one haf the samping frequency. Figure shows spectra content from DC to 5.625kHz which is /2 the 3.25kHz samping rate. AMPLITUDE (db) f SAMPLE = 3.25kHz f IN =.8kHz FREQUENCY (khz) Figure. This Cean FFT of an.8khz Input Shows Remarkabe Performance for an ADC That Draws Ony When Samping at the 3.25kHz Rate F 968fc

25 APPLICATIONS INFORMATION Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resoution of an A/D and is directy reated to the S/(N + D) by the equation: ENOB = [S/(N + D).76]/6.2 where S/(N + D) is expressed in db. At the maximum samping rate of 33kHz the LTC96 maintains 7.5 ENOBs or better to 4kHz. Above 4kHz the ENOBs graduay decine, as shown in Figure 2, due to increasing second harmonic distortion. The noise f oor remains approximatey 7dB. EFFECTIVE NUMBER OF BITS (ENOBs) f SAMPLE = 3.25kHz 2 4 INPUT FREQUENCY (khz) 968 F2 Figure 2. Dynamic Accuracy Is Maintained Up to an Input Frequency of 4kHz TYPICAL APPLICATIONS MICROPROCESSOR INTERFACES The LTC96(L)/LTC98(L) can interface directy (without externa hardware to most popuar microprocessor (MPU) synchronous seria formats (see Tabe ). If an MPU without a dedicated seria port is used, then three or four of the MPU s parae port ines can be programmed to form the seria ink to the LTC96(L)/LTC98(L). Incuded here is one seria interface exampe and one exampe showing a parae port programmed to form the seria interface. Motoroa SPI (MC68HC5C4,CM68HC) The MC68HC5C4 has been chosen as an exampe of an MPU with a dedicated seria port. This MPU transfer data MSB-first and in 8-bit increments. With two 8-bit transfers, the A/D resut is read into the MPU. The first 8-bit transfer sends the D IN word to the LTC98(L) and cocks into the processor. The second 8-bit transfer cocks the A/D conversion resut, B7 through B, into the MPU. ANDing the first MUP received byte with Hex cears the first byte. Notice how the position of the start bit in the first MPU transmit word is used to position the A/D resut right-justifi ed in two memory ocations. Tabe. Microprocessor with Hardware Seria Interfaces Compatibe with the LTC96(L)/LTC98(L) PART NUMBER TYPE OF INTERFACE Motoroa MC685S2,S3 MC68HC MC68HC5 RCA CDP68HC5 Hitachi HD635 HD6375 HD63 HD637 HD633 HD648 Nationa Semiconductor COP4 Famiy COP8 Famiy NS85U HPC6 Famiy Texas Instruments TMS72 TMS742 TMS7C2 TMS7C42 TMS32* TMS322 * Requires externa hardware SPI SPI SPI SPI SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous I/O MICROWIRE MICROWIRE/PLUS MICROWIRE/PLUS MICROWIRE/PLUS Seria Port Seria Port Seria Port Seria Port Seria Port Seria Port MICROWIRE and MICROWIRE/PLUS are trademarks of Nationa Semiconductor Corp. 968fc 25

26 TYPICAL APPLICATIONS Data Exchange Between LTC98(L) and MC68HC5C4 START BIT MPU TRANSMIT WORD SGL/ DIFF BYTE ODD/ SIGN MSBF X BYTE 2 (DUMMY) X X X X X X X X X = DON'T CARE D IN START SGL/ DIFF ODD/ SIGN MSBF DON'T CARE B7 B6 B5 B4 B3 B2 B B MPU RECEIVED WORD??????? B7 B6 B5 B4 B3 B2 B B ST TRANSFER 2ND TRANSFER 968 TA3 Hardware and Software Interface to Motoroa MC68HC5C4 ANALOG INPUTS LOCATION A LOCATION A + LTC98 D IN C SCK MC68HC5C4 MISO MOSI from LTC98(L) Stored in MC68HC5C4 B7 B6 B5 B4 B3 B2 B B LSB 968 TA5 968 TA4 BYTE BYTE 2 LABEL MNEMONIC COMMENTS START BCLRn LDA STA TST BPL LDA STA AND STA TST BPL BSETn LDA STA Bit Port C goes ow ( goes ow) Load LTC98(L) D IN word into Acc. Load LTC98(L) D IN word into SPI from Acc. Transfer begins. Test status of SPIF Loop to previous instruction if not done with transfer Load contents of SPI data register into Acc. ( MSBs) Start next SPI cyce Cear the fi rst word Store in memory ocation A (MSBs) Test status of SPIF Loop to previous instruction if not done with transfer Set B of Port C ( goes high) Load contents of SPI data register into Acc. ( LSBs) Store in memory ocation A + (LSBs) fc

27 TYPICAL APPLICATIONS Interfacing to the Parae Port of the Inte 85 Famiy The Inte 85 has been chosen to demonstrate the interface between the LTC98(L) and parae port microprocessors. Normay the, and D IN signas woud be generated on three port ines and the signa read on a fourth port ine. This works very we. However, we wi demonstrate here an interface with the D IN and of the LTC98(L) tied together as described in the SERIAL INTERFACE section. This saves one wire. The 85 first sends the start bit and MUX address to the LTC98(L) over the data ine connected to P.2. Then P.2 is reconfi gured as an input (by writing to it a one) and the 85 reads back the 8-bit A/D resut over the same data ine. LABEL MNEMONIC OPERAND COMMENTS LOOP LOOP MOV SETB CLR MOV RLC CLR MOV SETB DJNZ MOV CLR MOV MOV RLC SETB CLR DJNZ MOV SETB A, #FFH P.4 P.4 R4, #4 A P.3 P.2, C P.3 R4, LOOP P, #4 P.3 R4, #9 C, P.2 A P.3 P.3 R4, LOOP R2, A P.4 D IN word for LTC98(L) Make sure is high goes ow Load counter Rotate D IN bit into Carry goes ow Output D IN bit to LTC98(L) goes high Next bit Bit 2 becomes an input goes ow Load counter Read data bit into Carry Rotate data bit into Acc. goes high goes ow Next bit Store MSBs in R2 goes high ANALOG INPUTS LTC98(L) D IN MUX ADDRESS P.4 P.3 P.2 85 from LTC98(L) Stored in 85 RAM MSB LSB R2 B7 B6 B5 B4 B3 B2 B B A/D RESULT 968 TA6 968 TA7 MSBF BIT LATCHED BY LTC98(L) SGL/ DATA (D IN / ) START ODD/ DIFF SIGN MSBF B7 B6 B5 B4 B3 B2 B B 85 P.2 OUTPUTS DATA TO LTC98(L) 85 P.2 RECONFIGURED AS AN INPUT AFTER THE 4TH RISING AND BEFORE THE 4TH FALLING LTC98(L) TAKES CONTROL OF DATA LINE ON 4TH FALLING LTC98(L) SENDS A/D RESULT BACK TO 85 P TA8 968fc 27

28 A Quick Look Circuit for the LTC96 Users can get a quick ook at the function and timing of the LT96 by using the foowing simpe circuit (Figure 3). V REF is tied to V CC. V IN is appied to the +IN input and the IN input is tied to the ground. is driven at /6 the cock rate by the 74C6 and outputs the data. The output data from the pin can be viewed on an oscioscope that is set up to trigger on the faing edge of (Figure 4). Note the LSB data is partiay cocked out before goes high. V IN V CC CH LTC96 CH GND 4.7μF + V REF 5V TO OSCILLOSCOPE CLR A B C D P GND 74C6 V CC RC QA QB QC QD T LOAD CLOCK IN 5kHz MAX Figure 3. Quick Look Circuit for the LTC F3 Figure 5 shows a temperature measurement system. The LTC96 is connected directy to the ow cost siicon temperature sensor. The votage appied to the V REF pin adjusts the fu scae of the A/D to the output range of the sensor. The zero point of the converter is matched to the zero output votage of the sensor by the votage on the LTC96 s negative input. 5V Figure 4. Scope Trace the LTC96 Quick Look Circuit Showing A/D Output (AA HEX ) 678Ω LM34 3.5k.μF NULL BIT 75k 82k MSB (B7) LT4-.2.μF LSB (B) VERTICAL: 5V/DIV HORIZONTAL: μs/div IN LTC96 Figure 5. The LTC96 s High Impedance Input Connects Directy to This Temperature Sensor, Eiminating Signa Conditioning Circuitry in This C to 7 C Thermometer +IN V REF 63.4k LSB DATA (B) 3V V CC GND 968 F4.μF TO μp 968 F fc