LTC6993-1/LTC LTC6993-3/LTC TimerBlox: Monostable Pulse Generator (One Shot) Applications. Typical Application

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1 Features n Puse Width Range: 1µs to 33.6 Seconds n Configured with 1 to 3 Resistors n Puse Width Max Error: <.3% for Puse Width > 51µs <3.4% for Puse Width of 8µs to 51µs <4.9% for Puse Width of 1µs to 8µs n Four LTC6993 Options Avaiabe: Rising-Edge or Faing-Edge Trigger Retriggerabe or Non-Retriggerabe n Configurabe for Positive or Negative Output Puse n Fast Recovery Time n. to 5. Singe Suppy Operation n 7µA Suppy Current at 1µs Puse Width n 5µs Start-Up Time n CMOS Output Driver Sources/Sinks ma n 4 C to 15 C Operating Temperature Range n Avaiabe in Low Profie (1mm) SOT-3 (ThinSOT ) and mm 3mm DFN Appications n Watchdog Timer n Frequency Discriminators n Missing Puse Detection n Enveope Detection n High Vibration, High Acceeration Environments n Portabe and Battery-Powered Equipment L, LT, LTC, LTM, Linear Technoogy, TimerBox and the Linear ogo are registered trademarks and ThinSOT is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. LTC6993-1/LTC6993- TimerBox: Monostabe Puse Generator (One Shot) Description The LTC 6993 is a monostabe mutivibrator (aso known as a one-shot puse generator) with a programmabe puse width of 1µs to 33.6 seconds. The LTC6993 is part of the TimerBox famiy of versatie siicon timing devices. A singe resistor, R, programs an interna master osciator frequency, setting the LTC6993 s time base. The output puse width is determined by this master osciator and an interna cock divider, N, programmabe to eight settings from 1 to 1. t = N R 5kΩ 1µs, N = 1, 8, 64,...,1 The output puse is initiated by a transition on the trigger input (). Each part can be configured to generate positive or negative output puses. The LTC6993 is avaiabe in four versions to provide different trigger signa poarity and retrigger capabiity. DEVICE INPUT POLARITY REGER LTC Rising-Edge No LTC6993- Rising-Edge Yes LTC Faing-Edge No LTC Faing-Edge Yes The LTC6993 aso offers the abiity to dynamicay adjust the width of the output puse via a separate contro votage. For easy configuration of the LTC6993, downoad the TimerBox Designer too at Typica Appication Enveope Detector 8kHz CARRIER MODULATED CARRIER LTC6993- SIGNAL ENVELOPE 3.3V V/ R 8k V TA1a.1µF V/ 16µs 5µs/ TA1b 1

2 Absoute Maximum Ratings (Note 1) Suppy Votage (V+) to...6v Maximum Votage on Any Pin... (.3V) V PIN ( +.3V) Operating Temperature Range (Note ) LTC6993C... 4 C to 85 C LTC6993I... 4 C to 85 C LTC6993H... 4 C to 15 C Specified Temperature Range (Note 3) LTC6993C... C to 7 C LTC6993I... 4 C to 85 C LTC6993H... 4 C to 15 C Junction Temperature C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec) S6 Package...3 C Pin Configuration TOP VIEW 1 6 TOP VIEW DCB PACKAGE 6-LEAD (mm 3mm) PLASTIC DFN T JMAX = 15 C, θ JA = 64 C/W, θ JC = 1.6 C/W EXPOSED PAD (PIN 7) CONNECTED TO, PCB CONNECTION OPTIONAL S6 PACKAGE 6-LEAD PLASTIC TSOT-3 T JMAX = 15 C, θ JA = 19 C/W, θ JC = 51 C/W Order Information Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6993CDCB-1#TRMPBF LTC6993CDCB-1#TRPBF LDXH 6-Lead (mm 3mm) Pastic DFN C to 7 C LTC6993IDCB-1#TRMPBF LTC6993IDCB-1#TRPBF LDXH 6-Lead (mm 3mm) Pastic DFN 4 C to 85 C LTC6993HDCB-1#TRMPBF LTC6993HDCB-1#TRPBF LDXH 6-Lead (mm 3mm) Pastic DFN 4 C to 15 C LTC6993CDCB-#TRMPBF LTC6993CDCB-#TRPBF LDXK 6-Lead (mm 3mm) Pastic DFN C to 7 C LTC6993IDCB-#TRMPBF LTC6993IDCB-#TRPBF LDXK 6-Lead (mm 3mm) Pastic DFN 4 C to 85 C LTC6993HDCB-#TRMPBF LTC6993HDCB-#TRPBF LDXK 6-Lead (mm 3mm) Pastic DFN 4 C to 15 C LTC6993CDCB-3#TRMPBF LTC6993CDCB-3#TRPBF LFMJ 6-Lead (mm 3mm) Pastic DFN C to 7 C LTC6993IDCB-3#TRMPBF LTC6993IDCB-3#TRPBF LFMJ 6-Lead (mm 3mm) Pastic DFN 4 C to 85 C LTC6993HDCB-3#TRMPBF LTC6993HDCB-3#TRPBF LFMJ 6-Lead (mm 3mm) Pastic DFN 4 C to 15 C LTC6993CDCB-4#TRMPBF LTC6993CDCB-4#TRPBF LFMM 6-Lead (mm 3mm) Pastic DFN C to 7 C LTC6993IDCB-4#TRMPBF LTC6993IDCB-4#TRPBF LFMM 6-Lead (mm 3mm) Pastic DFN 4 C to 85 C LTC6993HDCB-4#TRMPBF LTC6993HDCB-4#TRPBF LFMM 6-Lead (mm 3mm) Pastic DFN 4 C to 15 C LTC6993CS6-1#TRMPBF LTC6993CS6-1#TRPBF LTDXG 6-Lead Pastic TSOT-3 C to 7 C LTC6993IS6-1#TRMPBF LTC6993IS6-1#TRPBF LTDXG 6-Lead Pastic TSOT-3 4 C to 85 C LTC6993HS6-1#TRMPBF LTC6993HS6-1#TRPBF LTDXG 6-Lead Pastic TSOT-3 4 C to 15 C

3 Order Information Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6993CS6-#TRMPBF LTC6993CS6-#TRPBF LTDXJ 6-Lead Pastic TSOT-3 C to 7 C LTC6993IS6-#TRMPBF LTC6993IS6-#TRPBF LTDXJ 6-Lead Pastic TSOT-3 4 C to 85 C LTC6993HS6-#TRMPBF LTC6993HS6-#TRPBF LTDXJ 6-Lead Pastic TSOT-3 4 C to 15 C LTC6993CS6-3#TRMPBF LTC6993CS6-3#TRPBF LTFMH 6-Lead Pastic TSOT-3 C to 7 C LTC6993IS6-3#TRMPBF LTC6993IS6-3#TRPBF LTFMH 6-Lead Pastic TSOT-3 4 C to 85 C LTC6993HS6-3#TRMPBF LTC6993HS6-3#TRPBF LTFMH 6-Lead Pastic TSOT-3 4 C to 15 C LTC6993CS6-4#TRMPBF LTC6993CS6-4#TRPBF LTFMK 6-Lead Pastic TSOT-3 C to 7 C LTC6993IS6-4#TRMPBF LTC6993IS6-4#TRPBF LTFMK 6-Lead Pastic TSOT-3 4 C to 85 C LTC6993HS6-4#TRMPBF LTC6993HS6-4#TRPBF LTFMK 6-Lead Pastic TSOT-3 4 C to 15 C TRM = 5 pieces. *Temperature grades are identified by a abe on the shipping container. Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 5 C. Test conditions are =. to 5., = V, CODE = to 15 (N = 1 to 1 ), R = 5k to 8k, R LOAD = 5k, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Output Puse Width 1µ sec t Puse Width Accuracy (Note 4) N 51 ±1.7 ±.3 ±3. % % 8 N 64 ±.4 ±3.4 ±4.4 % % N = 1 (LTC or LTC6993-) ±3.6 ±4.9 ±6. % % N = 1 (LTC or LTC6993-4) ±4. ±5.3 ±6.4 % % t / T Puse Width Drift Over Temperature N 51 N 64 ±.6 ±.8 %/ C %/ C Puse Width Change With Suppy N 51 = 4. to 5. =. to % % 8 N 64 = 4. to 5. =.7V to 4. =. to.7v % % % Puse Width Jitter (Note 1) N = 1 = 5. = % P-P % P-P N = 8. % P-P N = 64.5 % P-P N = 51. % P-P N = % P-P t S Puse Width Change Setting Time (Note 9) t MASTER = t /N 6 t MASTER µs 3

4 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 5 C. Test conditions are =. to 5., = V, CODE = to 15 (N = 1 to 1 ), R = 5k to 8k, R LOAD = 5k, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Suppy Operating Suppy Votage Range V Power-On Reset Votage 1.95 V I S(IDLE) Suppy Current (Ide) R L =, R = 5k, N 64 = 5. =. R L =, R = 5k, N 51 = 5. =. R L =, R = 8k, N 64 = 5. =. R L =, R = 8k, N 51 = 5. =. Anaog Inputs V Votage at Pin V V / T V Drift Over Temperature ±75 µv/ C R Frequency-Setting Resistor 5 8 kω V Pin Votage V V / Pin Vaid Code Range (Note 5) Deviation from Idea ±1.5 % V / = (CODE +.5)/16 Pin Input Current ±1 na Digita I/O Pin Input Capacitance.5 pf Pin Input Current = V to ±1 na V IH High Leve Pin Input Votage (Note 6).7 V V IL Low Leve Pin Input Votage (Note 6).3 V I (MAX) Output Current =.7V to 5. ± ma V OH High Leve Output Votage (Note 7) = 5. I = 1mA I = 16mA = 5. I = 1mA I = 16mA =. I = 1mA I = 8mA V OL Low Leve Output Votage (Note 7) = 5. I = 1mA I = 16mA = 3.3V I = 1mA I = 1mA =. I = 1mA I = 8mA µa µa µa µa µa µa µa µa V V V V V V V V V V V V 4

5 Eectrica Characteristics LTC6993-1/LTC6993- The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 5 C. Test conditions are =. to 5., = V, CODE = to 15 (N = 1 to 1 ), R = 5k to 8k, R LOAD =, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t PD Trigger Propagation Deay = 5. = 3.3V =. t WIDTH Minimum Recognized Puse Width = 3.3V 5 ns t ARM Recovery Time (LTC6993-1/LTC6993-3) 4 ns t RE Time Between Trigger Signas N = 1 = 3.3V 1 ns (LTC6993-/LTC6993-4) N > 1 = 3.3V 5 ns t r Output Rise Time (Note 8) = 5. = 3.3V =. t f Output Fa Time (Note 8) = 5. = 3.3V = ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note : The LTC6993C is guaranteed functiona over the operating temperature range of 4 C to 85 C. Note 3: The LTC6993C is guaranteed to meet specified performance from C to 7 C. The LTC6993C is designed, characterized and expected to meet specified performance from 4 C to 85 C but it is not tested or QA samped at these temperatures. The LTC6993I is guaranteed to meet specified performance from 4 C to 85 C. The LTC6993H is guaranteed to meet specified performance from 4 C to 15 C. Note 4: Puse width accuracy is defined as the deviation from the t equation, assuming R is used to program the puse width. Note 5: See Operation section, Tabe 1 and Figure for a fu expanation of how the pin votage seects the vaue of CODE. Note 6: The pin has hysteresis to accommodate sow rising or faing signas. The threshod votages are proportiona to. Typica vaues can be estimated at any suppy votage using: V (RISING) mV and V (FALLING) mV Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrariy given a negative vaue. Note 8: Output rise and fa times are measured between the 1% and the 9% power suppy eves with 5pF output oad. These specifications are based on characterization. Note 9: Setting time is the amount of time required for the output to sette within ±1% of the fina puse width after a.5 or change in I. Note 1: Jitter is the ratio of the deviation of the output puse width to the mean of the puse width. This specification is based on characterization and is not 1% tested. 5

6 Typica Performance Characteristics = 3.3V, R = k and T A = 5 C uness otherwise noted t Drift vs Temperature (N 64) R = 5k 3 PARTS t Drift vs Temperature (N 64) R = k 3 PARTS t Drift vs Temperature (N 64) R = 8k 3 PARTS DRIFT (%) DRIFT (%) DRIFT (%) TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) G G G t Drift vs Temperature (N 51) R = 5k 3 PARTS t Drift vs Temperature (N 51) R = k 3 PARTS t Drift vs Temperature (N 51) R = 8k 3 PARTS DRIFT (%) DRIFT (%) DRIFT (%) TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) G G G6 DRIFT (%) t Drift vs Suppy Votage (N = 1, Rising Edge) LTC6993-1/LTC6993- CODE = REFERENCED TO = 4V 3 4 SUPPLY (V) R = 5k R = k R = 8k G7 DRIFT (%) t Drift vs Suppy Votage (N = 1, Faing Edge) CODE = REFERENCED TO = 4V 3 4 SUPPLY (V) R = 5k R = k R = 8k G8 DRIFT (%) t Drift vs Suppy Votage (N > 1) REFERENCED TO = 4V R = 5k, N = 8 R = 5k TO 8k, N 51 R = 8k, N = SUPPLY (V) G9 6

7 Typica Performance Characteristics = 3.3V, R = k and T A = 5 C uness otherwise noted. ERROR (%) t Error vs R (N = 1, Rising Edge) LTC6993-1/LTC6993- CODE = 3 PARTS R (kω) ERROR (%) t Error vs R (8 N 64) 3 PARTS R (kω) ERROR (%) t Error vs R (N 51) 3 PARTS R (kω) G G G t Error vs R (N = 1, Faing Edge) CODE = 3 PARTS t Error vs CODE (Rising Edge) LTC6993-1/LTC6993- R = 5k 3 PARTS t Error vs CODE (Faing Edge) R = 5k 3 PARTS ERROR (%) 1 1 ERROR (%) 1 1 ERROR (%) R (kω) CODE CODE G G G15 V (mv) 1. V Drift vs I REFERENCED TO I = 1µA I (µa) G16 DRIFT (mv) V Drift vs Suppy Votage REFERENCED TO = 4V SUPPLY (V) G17 V (V) V vs Temperature 3 PARTS TEMPERATURE ( C) G18 7

8 Typica Performance Characteristics = 3.3V, R = k and T A = 5 C uness otherwise noted. NUMBER OF UNITS Typica V Distribution Suppy Current vs Suppy Votage Suppy Current vs Temperature LOTS DFN AND SOT UNITS V (V) G19 POWER SUPPLY CURRENT (µa) ACTIVE = 5% TIMING DUTY CYCLE C LOAD = 5pF R LOAD = R = 5k 1, ACTIVE R = 5k 1, IDLE R = 1k, 8, ACTIVE R = 1k, 8, IDLE R = 8k, SUPPLY VOLTAGE (V) G POWER SUPPLY CURRENT (µa) ACTIVE = 5% TIMING DUTY CYCLE 5 5 R = 5k, 1, ACTIVE R = 5k, 1, IDLE R = 1k, 8, ACTIVE R = 1k, 8, IDLE R = 8k, 51 C LOAD = 5pF R LOAD = TEMPERATURE ( C) G1 POWER SUPPLY CURRENT (µa) Suppy Current vs Pin Votage FALLING 3.3V FALLING V / (V/V) RISING 3.3V RISING 5 C LOAD = 5pF R LOAD = G POWER SUPPLY CURRENT (µa) Suppy Current vs t () 1 ACTIVE CURRENT MEASURED WITH GER PERIOD = t (5% DUTY CYCLE) = C LOAD = 5pF ACTIVE R LOAD = IDLE t (ms) G3 POWER SUPPLY CURRENT (µa) Suppy Current vs t (.) 1 ACTIVE CURRENT MEASURED WITH GER PERIOD = t (5% DUTY CYCLE) =. C LOAD = 5pF ACTIVE R LOAD = IDLE t (ms) G4 RST PIN VOLTAGE (V) Threshod Votage vs Suppy Votage POSITIVE GOING NEGATIVE GOING SUPPLY VOLTAGE (V) G5 JITTER (% P-P ) Peak-to-Peak Jitter vs t.1 1, 5. 1,. 8,. 8, PEAK-TO-PEAK t VARIATION MEASURED OVER 3s INTERVALS t (ms) G6 I (µa) Typica I Current Limit vs 1 PIN SHORTED TO SUPPLY VOLTAGE (V) G7 8

9 Typica Performance Characteristics = 3.3V, R = k and T A = 5 C uness otherwise noted. PROPAGATION DELAY (ns) Trigger Propagation Deay (t PD ) vs Suppy Votage C LOAD = 5pF RISE/FALL TIME (ns) Rise and Fa Time vs Suppy Votage t RISE t FALL C LOAD = 5pF PUT RESISTANCE (Ω) Output Resistance vs Suppy Votage PUT SOURCING CURRENT PUT SINKING CURRENT SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 699 G SUPPLY VOLTAGE (V) G G8 9

10 Pin Functions (DCB/S6) (Pin 1/Pin 5): Suppy Votage (. to 5.). This suppy shoud be kept free from noise and rippe. It shoud be bypassed directy to the pin with a.1µf capacitor. (Pin /Pin 4): Programmabe Divider and Poarity Input. The pin votage (V ) is internay converted into a 4-bit resut (CODE). V may be generated by a resistor divider between and. Use 1% resistors to ensure an accurate resut. The pin and resistors shoud be shieded from the pin or any other traces that have fast edges. Limit the capacitance on the pin to ess than 1pF so that V settes quicky. The MSB of CODE (POL) determines the poarity of the pins. When POL = the output produces a positive puse. When POL = 1 the output produces a negative puse. (Pin 3/Pin 3): Puse Width Setting Input. The votage on the pin (V ) is reguated to 1V above. The amount of current sourced from the pin (I ) programs the master osciator frequency. The I current range is 1.5µA to µa. The output puse wi continue indefinitey if I drops beow approximatey 5nA, and wi terminate when I increases again. A resistor connected between and is the most accurate way to set the puse width. For best performance, use a precision meta or thin fim resistor of.5% or better toerance and 5ppm/ C or better temperature coefficient. For ower accuracy appications an inexpensive 1% thick fim resistor may be used. Limit the capacitance on the pin to ess than 1pF to minimize jitter and ensure stabiity. Capacitance ess than 1pF maintains the stabiity of the feedback circuit reguating the V votage. (Pin 4/Pin 1): Trigger Input. Depending on the version, a rising or faing edge on wi initiate the output puse. LTC and LTC6993- are rising-edge sensitive. LTC and LTC are faing-edge sensitive. The LTC6993- and LTC are retriggerabe, aowing the puse width to be extended by additiona trigger signas that occur whie the output is active. The LTC6993 1/ LTC wi ignore additiona trigger inputs unti the output puse has terminated. (Pin 5/Pin ): Ground. Tie to a ow inductance ground pane for best performance. (Pin 6/Pin 6): Output. The pin swings from to with an output resistance of approximatey 3Ω. When driving an LED or other ow impedance oad a series output resistor shoud be used to imit source/ sink current to ma. R LTC PF C1.1µF 1

11 + + LTC6993-1/LTC6993- Bock Diagram (S6 package pin numbers shown) BIT A/D CONVERTER DIGITAL FILTER POL 1 GER/ REGER LOGIC S MASTER OSCILLATOR t MASTER = 1µs 5kΩ V I MCLK PROGRAMMABLE IDER 1, 8, 64, 51, 496, 15, 18, 1 R Q PUT POLARITY 6 t HALT OSCILLATOR IF I < 5nA POR I V = 1V 1V I 3 R BD 11

12 Operation The LTC6993 is buit around a master osciator with a 1µs minimum period. The osciator is controed by the pin current (I ) and votage (V ), with a 1µs/5kΩ conversion factor that is accurate to ±1.7% under typica conditions. t MASTER = 1µs 5kΩ V I A feedback oop maintains V at 1V ±3mV, eaving I as the primary means of controing the puse width. The simpest way to generate I is to connect a resistor (R ) between and, such that I = V /R. The master osciator equation reduces to: t MASTER = 1µs R 5kΩ From this equation, it is cear that V drift wi not affect the puse width when using a singe program resistor (R ). Error sources are imited to R toerance and the inherent puse width accuracy t of the LTC6993. R may range from 5k to 8k (equivaent to I between 1.5µA and µa). A trigger signa (rising or faing edge on pin) atches the output to the active state, beginning the output puse. At the same time, the master osciator is enabed to time the duration of the output puse. When the desired puse width is reached, the master osciator resets the output atch. The LTC6993 aso incudes a programmabe frequency divider which can further divide the frequency by 1, 8, 64, 51, 496, 15, 18 or 1. This extends the puse width duration by those same factors. The divider ratio N is set by a resistor divider attached to the pin. t = N 5kΩ V I 1µs With R in pace of V /I the equation reduces to: t = N R 5kΩ 1µs CODE The pin connects to an interna, referenced 4-bit A/D converter that determines the CODE vaue. CODE programs two settings on the LTC6993: 1. CODE determines the frequency divider setting, N.. CODE determines the poarity of pin, via the POL bit. V may be generated by a resistor divider between and as shown in Figure 1. LTC F1. TO 5. Figure 1. Simpe Technique for Setting CODE Tabe 1 offers recommended 1% resistor vaues that accuratey produce the correct votage division as we as the corresponding N and POL vaues for the recommended resistor pairs. Other vaues may be used as ong as: 1. The V / ratio is accurate to ±1.5% (incuding resistor toerances and temperature effects).. The driving impedance ( ) does not exceed 5kΩ. If the votage is generated by other means (i.e., the output of a DAC) it must track the suppy votage. The ast coumn in Tabe 1 shows the idea ratio of V to the suppy votage, which can aso be cacuated as: V CODE+.5 = ±1.5% + V 16 For exampe, if the suppy is 3.3V and the desired CODE is 4, V = V = 98mV ± 5mV. Figure iustrates the information in Tabe 1, showing that N is symmetric around the CODE midpoint. 1

13 Operation Tabe 1. CODE Programming CODE POL N Recommended t (k) (k) V / 1 1µs to 16µs Open Short.315 ± µs to 18µs ± µs to 1.4ms ± µs to 8.19ms ± , ms to 65.54ms ± , ms to 54.3ms ± , ms to 4.194sec ±.15 7,97,15.97sec to 33.55sec ± ,97,15.97sec to 33.55sec ± , ms to 4.194sec ± , ms to 54.3ms ± , ms to 65.54ms ± µs to 8.19ms ± µs to 1.4ms ± µs to 18µs ± µs to 16µs Short Open ±.15 POL BIT = POL BIT = t (ms) V V + INCREASING V F Figure. Puse Width Range and POL Bit vs CODE 13

14 Operation Monostabe Mutivibrator (One Shot) The LTC6993 is a monostabe mutivibrator. A trigger signa on the input wi force the output to the active (unstabe) state for a programmabe duration. This type of circuit is commony referred to as a one-shot puse generator. Figures 3 detais the basic operation. A rising edge on the pin initiates the output puse. The puse width (t ) is determined by the N setting and by the resistor (R ) connected to the pin. Subsequent rising edges on have no affect unti the competion of the one shot and for a short rearming time (t ARM ) thereafter. To ensure proper operation, positive and negative puses shoud be at east t WIDTH wide. The LTC6993- and LTC aow the output puse to be retriggered. As shown in Figure 4, the output puse wi stay high unti t after the ast rising-edge on. Successive trigger signas can extend the puse width indefinitey. Consecutive trigger signas must be separated by t RE to be recognized. Negative Trigger Versions In addition to the retrigger option, the LTC6993 famiy aso incudes negative input (faing-edge) versions. These four combinations are detaied in Tabe. Tabe. Retrigger and Input Poarity Options DEVICE INPUT POLARITY REGER LTC Rising-Edge No LTC6993- Rising-Edge Yes LTC Faing-Edge No LTC Faing-Edge Yes Output Poarity (POL Bit) Each variety of LTC6993 aso offers the abiity to invert the output, producing negative puses. This option is programmed, aong with N, by the choice of CODE. (The previous section describes how to program CODE using the pin). t WIDTH t PD t PD t ARM t t t F3 Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = ) t WIDTH t RE t PD t PD t PD t PD t t t F4 Figure 4. Retriggering Timing Diagram (LTC6993-, POL = ) 14

15 Operation Changing CODE After Start-Up Foowing start-up, the A/D converter wi continue monitoring V for changes. Changes to CODE wi be recognized sowy, as the LTC6993 paces a priority on eiminating any wandering in the CODE. The typica deay depends on the difference between the od and new CODE settings and is proportiona to the master osciator period. t CODE = 16 ( CODE + 6) t MASTER A change in CODE wi not be recognized unti it is stabe, and wi not pass through intermediate codes. A digita fiter is used to guarantee the CODE has setted to a new vaue before making changes to the output. However, if the output puse is active during the transition, the puse width can take on a vaue between the two settings. 5mV/ V/ 51µs Start-Up Time When power is first appied, the power-on reset (POR) circuit wi initiate the start-up time, t START. The pin is hed ow during this time. The typica vaue for t START ranges from.5ms to 8ms depending on the master osciator frequency (independent of N ): t START(TYP) = 5 t MASTER During start-up, the pin A/D converter must determine the correct CODE before an output puse can be generated. The start-up time may increase if the suppy or pin votages are not stabe. For this reason, it is recommended to minimize the capacitance on the pin so it wi propery track. Less than 1pF wi not extend the start-up time. The CODE setting is recognized at the end of the startup up. If POL = 1, the output wi transition high. Otherwise (if POL = ) simpy remains ow. At this point, the LTC6993 is ready to respond to rising/faing edges on the input. V/ 4µs 56µs V+ LTC = 3.3V R = k µs/ F5a Figure 5a. CODE Change from to t START ( IGNORED) POL = POL = 1 5mV/ V/ 51µs t Figure 6. Start-Up Timing Diagram F6 V/ 4µs 56µs LTC = 3.3V R = k µs/ F5b Figure 5b. CODE Change from to 15

16 Appications Information Basic Operation The simpest and most accurate method to program the LTC6993 is to use a singe resistor, R, between the and pins. The design procedure is a four step process. Aternativey, Linear Technoogy offers the easy-to-use TimerBox Designer too to quicky design any LTC6993 based circuit. Downoad the free TimerBox Designer software at Step 1: Seect the POL Bit Setting. The LTC6993 can generate positive or negative output puses, depending on the setting of the POL bit. The POL bit is the CODE MSB, so any CODE 8 has POL = 1 and produces active-ow puses. Step : Seect LTC6993 Version. Two input-reated choices dictate the proper LTC6993 for a given appication: Is a rising or faing-edge input? Shoud retriggering be aowed? Use Tabe to seect a particuar variety of LTC6993. Step 3: Seect the N Frequency Divider Vaue. As expained earier, the votage on the pin sets the CODE which determines both the POL bit and the N vaue. For a given output puse width (t ), N shoud be seected to be within the foowing range: t 16µs N t (1) 1µs To minimize suppy current, choose the owest N vaue. However, in some cases a higher vaue for N wi provide better accuracy (see Eectrica Characteristics). Tabe 1 can aso be used to seect the appropriate N vaues for the desired t. With POL aready chosen, this competes the seection of CODE. Use Tabe 1 to seect the proper resistor divider or V / ratio to appy to the pin. Step 4: Cacuate and Seect R. The fina step is to cacuate the correct vaue for R using the foowing equation: R = 5k 1µs t N () Seect the standard resistor vaue cosest to the cacuated vaue. Exampe: Design a one-shot circuit that satisfies the foowing requirements: t = 1µs Negative Output Puse Rising-Edge Trigger Input Retriggerabe Input Minimum power consumption Step 1: Seect the POL Bit Setting. For inverted (negative) output puse, choose POL = 1. Step : Seect the LTC6993 Version. A rising-edge retriggerabe input requires the LTC6993. Step 3: Seect the N Frequency Divider Vaue. Choose an N vaue that meets the requirements of Equation (1), using t = 1µs: 6.5 N 1 Potentia settings for N incude 8 and 64. N = 8 is the best choice, as it minimizes suppy current by using a arge R resistor. POL = 1 and N = 8 requires CODE = 14. Using Tabe 1, choose = 1k and = 976k vaues to program CODE = 14. Step 4: Seect R. Cacuate the correct vaue for R using Equation (): R = 5k 1µs 1µs = 65k 8 16

17 Appications Information Since 65k is not avaiabe as a standard 1% resistor, substitute 619k if a.97% shift in t is acceptabe. Otherwise, seect a parae or series pair of resistors such as 39k and 316k to attain a more precise resistance. The competed design is shown in Figure 7. V CTRL R MOD LTC6993 C1.1µF R R 65k LTC TO 5..1µF 1k CODE = k F7 Figure 7. 1µs Negative Puse Generator Votage-Controed Puse Width With one additiona resistor, the LTC6993 output puse width can be manipuated by an externa votage. As shown in Figure 8, votage V CTRL sources/sinks a current through R MOD to vary the I current, which in turn moduates the puse width as described in Equation (3). t = N R MOD 5kΩ 1µs 1+ R MOD R V CTRL V (3) Figure 8. Votage-Controed Puse Width F8 Digita Puse Width Contro The contro votage can be generated by a DAC (digita-toanaog converter), resuting in a digitay-controed puse width. Many DACs aow for the use of an externa reference. If such a DAC is used to provide the V CTRL votage, the V dependency can be eiminated by buffering V and using it as the DAC s reference votage, as shown in Figure 9. The DAC s output votage now tracks any V variation and eiminates it as an error source. The pin cannot be tied directy to the reference input of the DAC because the current drawn by the DAC s REF input woud affect the puse width. LTC6993.1µF C1.1µF 1/ LTC µF F9 µp D IN CLK V CC REF LTC1659 V R MOD N R t MOD = 5kΩ D IN = TO R MOD R 1µs D IN 496 CS/LD R Figure 9. Digitay Controed Puse Width 17

18 Appications Information I Extremes (Master Osciator Frequency Extremes) When operating with I outside of the recommended 1.5µA to µa range, the master osciator operates outside of the 6.5kHz to 1MHz range in which it is most accurate. The osciator wi sti function with reduced accuracy for I < 1.5µA. At approximatey 5nA, the osciator wi stop. Under this condition, the output puse can sti be initiated, but wi not terminate unti I increases and the master osciator starts again. At the other extreme, it is not recommended to operate the master osciator beyond MHz because the accuracy of the pin ADC wi suffer. Setting Time Foowing a or.5 step change in I, the output puse width takes approximatey six master cock cyces (6 t MASTER ) to sette to within 1% of the fina vaue. An exampe is shown in Figure 1, using the circuit in Figure 8. Couping Error The current sourced by the pin is used to bias the interna master osciator. The LTC6993 responds to changes in I amost immediatey, which provides exceent setting time. However, this fast response aso makes the pin sensitive to couping from digita signas, such as the input. Even an exceent ayout wi aow some couping between and. Additiona error is incuded in the specified accuracy for N = 1 to account for this. Figure 11 shows that 1 suppy variation is dependent on couping from rising or faing trigger inputs and, to a esser extent, output poarity. A very poor ayout can actuay degrade performance further. The PCB ayout shoud avoid routing next to (or any other fast-edge, wide-swing signa) V CTRL V/ / / PULSE WIDTH µs/ LTC = 3.3V CODE = R = k R MOD = 464k t = 3µs AND 6µs µs/ F1 DRIFT (%) R = 5k N = 1 LTC POL = 1 LTC POL = 3 4 SUPPLY (V) LTC POL = 1 LTC POL = F11 Figure 11. t Drift vs Suppy Votage Figure 1. Typica Setting Time 18

19 Appications Information Power Suppy Current The Eectrica Characteristics tabe specifies the suppy current whie the part is ide (waiting to be triggered). I S(IDLE) varies with the programmed t and the suppy votage. Once triggered, the instantaneous suppy current increases to I S(ACTIVE) whie the timing circuit is active. I S(ACTIVE) = I S(IDLE) + I S(ACTIVE) The average increase in suppy current I S(ACTIVE) depends on the output duty cyce (or negative duty cyce, if POL = 1), since that represents the percentage of time that the circuit is active. I S(IDLE) and I S(ACTIVE) can be estimated using the equations in Tabe. Figure 1 shows how the suppy current increases from I S(IDLE) as the input frequency increases. The increase is smaer at higher N settings. POWER SUPPLY CURRENT (µa) IDLE = 3.3V DUTY CYCLE = f IN t 1, R = 5k C LOAD = 5pF R LOAD = 8, R = 5k 1, R = 1k 1, R = 8k DUTY CYCLE (%) F1 Figure 1. I S(ACTIVE) vs Output Duty Cyce Tabe. Typica Suppy Current CONDITION TYPICAL I S(IDLE) TYPICAL I S(ACTIVE) * N 64 ( N 7pF + 4pF) + V+ t 5kΩ +. I + 5µA Duty Cyce ( N t 5pF +18pF +C LOAD ) N 51 *Ignoring resistive oads (assumes R LOAD = ) N 7pF t + V+ 5kΩ +1.8 I + 5µA Duty Cyce C t LOAD 19

20 Appications Information Suppy Bypassing and PCB Layout Guideines The LTC6993 is an accurate monostabe mutivibrator when used in the appropriate manner. The part is simpe to use and by foowing a few rues, the expected performance is easiy achieved. Adequate suppy bypassing and proper PCB ayout are important to ensure this. Figure 13 shows exampe PCB ayouts for both the SOT-3 and DCB packages using 63 sized passive components. The ayouts assume a two ayer board with a ground pane ayer beneath and around the LTC6993. These ayouts are a guide and need not be foowed exacty. 1. Connect the bypass capacitor, C1, directy to the and pins using a ow inductance path. The connection from C1 to the pin is easiy done directy on the top ayer. For the DCB package, C1 s connection to is aso simpy done on the top ayer. For the SOT-3, can be routed through the C1 pads to aow a good C1 connection. If the PCB design rues do not aow that, C1 s connection can be accompished through mutipe vias to the ground pane. Mutipe vias for both the pin connection to the ground pane and the C1 connection to the ground pane are recommended to minimize the inductance. Capacitor C1 shoud be a.1µf ceramic capacitor.. Pace a passive components on the top side of the board. This minimizes trace inductance. 3. Pace R as cose as possibe to the pin and make a direct, short connection. The pin is a current summing node and currents injected into this pin directy moduate the output puse width. Having a short connection minimizes the exposure to signa pickup. 4. Connect R directy to the pin. Using a ong path or vias to the ground pane wi not have a significant affect on accuracy, but a direct, short connection is recommended and easy to appy. 5. Use a ground trace to shied the pin. This provides another ayer of protection from radiated signas. 6. Pace and cose to the pin. A direct, short connection to the pin minimizes the externa signa couping. LTC6993 C1.1µF R C1 C1 R R F13 DCB PACKAGE TSOT-3 PACKAGE Figure 13. Suppy Bypassing and PCB Layout

21 Typica Appications Missing Puse Detector LTC V.1µF V/ 5kHz INPUT 1k V/ 64µs R 4k CODE = 14 (N = 8, POL = 1) 976k TAa 5µs/ TAb Use retriggerabe one shot with output inverted. Output remains ow as ong as retrigger occurs within t = 64µs. 1.5ms Radio Contro Servo Reference Puse Generator R7 1k ms FRAME RATE GENERATOR ms PERIOD 1.5ms REFERENCE PULSE RE = OPEN RUN = (CLOSED) RST R3 11k LTC6991 R4 976k R5 1k C1.1µF R6 1k R8 143k LTC ms CAL TRIM 1M 8k 1.5ms PULSE TA3 C.1µF Puse Deay Generator 1µs DELAY GENERATOR 1µs PUT PULSE GENERATOR PULSE IN R6 78.7k LTC R4 18k R5 976k C1.1µF R3 61.9k LTC k 1k C.1µF 1µs PULSE IN 1µs DELAY 1µs PULSE 1

22 Typica Appications RC Servo Puse Generator Controed Retrigger Lockout Time Interva GER R9 1k 1.5ms PULSE GENERATOR PULSE R5 1k M1 N7.1µF R6 1M R7 39k LTC R3 147k ms REGER LOCK INTERVAL LTC M 8k R4 43k C.1µF GER PULSE IN 1.5ms PULSE ms REGER LOCK REGER LOCK TIME TA5 Staircase Generator with Reset PULSE FREQUENCY-TO-VOLTAGE CONVERTER R8 4.99k R7 1k.1µF PULSES IN 1k R6 k U LT µF D1 1N k R9 1k REGERABLE STAIRCASE RE PULSE GENERATOR C1 1µF + U4 N7 U3 LT149 RE STAIRCASE RE STAIRCASE V RAMP RE LTC6993-8k C.1µF STAIRCASE PULSES IN RES AFTER 1.5ms IF NO PULSES APPLIED TA6 R3 147k 1M

23 Typica Appications Puse Stretcher Q1 N97 U LT19. R6 1k C1 pf R4 4.99k Q4 N19A Q N97 RAMP Q3 N19A 1k + R7 1k U4 LT1638.1µF 6 14k 3 113k VOLTAGE VARIABLE PUT PULSE WIDTH LTC k 5 1k PULSE STRETCHED PULSE C4.1µF PULSE IN 1µs TO 1µs INPUT PULSE WIDTH R3 39k LTC RAMP VOLTAGE PROPORTIONAL TO INPUT PULSE WIDTH 5µs RAMP RE TIMER 18k R5 976k TA7 C.1µF On-Time Programmabe Pused Soenoid Driver Safety Time-Out Reay Driver GER 5 SECONDS ON D1 1N44 GER IN OFF R4 k R3 118k LTC M 887k 4V TA8 1mA SOLENOID DANFOSS 4 N4D TYPE AK4D Q1 N19A C.1µF TIMED (5s) TURN-OFF AFTER LOSS OF INPUT PULSES RUN ENABLE PULSES R3 118k RE LTC6993- D1 1N4148 R4 15k 1M 887k 1V L TA9 NO Q1 N19A C.1µF C 1 COTO 1 RELAY

24 Package Description DCB Package 6-Lead Pastic DFN (mm 3mm) (Reference LTC DWG # Rev A).7 ±.5. ±.1 ( SIDES) R =.115 TYP R =.5 TYP ± ± ±.5 ( SIDES).15 ±.5 PACKAGE LINE PIN 1 BAR TOP MARK (SEE NOTE 6).5 ±.5.5 BSC. REF 1.35 ±.5 ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE LINE M-9 VARIATION OF (TBD). DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE S6 Package 6-Lead Pastic TSOT-3 (Reference LTC DWG # ) 3. ±.1 ( SIDES).75 ± ±.1 ( SIDES) PIN 1 NOTCH R. OR.5 45 CHAMFER (DCB6) DFN ±.5.5 BSC 1.35 ±.1 ( SIDES) BOTTOM VIEW EXPOSED PAD.6 MAX.95 REF.9 BSC (NOTE 4) 1. REF 3.85 MAX.6 REF 1.4 MIN.8 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAY PER IPC CALCULATOR.95 BSC PLCS (NOTE 3).8.9. BSC DATUM A 1. MAX REF.9. (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.54mm 6. JEDEC PACKAGE REFERENCE IS MO BSC S6 TSOT-3 3 REV B

25 Revision History REV DATE DESCRIPTION PAGE NUMBER A 7/11 Revised Description section 1 to 3 Added text to Basic Operation paragraph in Appications Information section 15 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 5

26 Typica Appication Consecutive Test Sequencer START TEST SEQUENCE s TO 3s DELAY DELAY TEST 1 TEST TEST 3 5k DELAY ADJUST 3s s R9 74k LTC k.1µF 1k R3 887k LTC R6 191k.1µF LTC R7 191k.1µF LTC R8 191k.1µF R5 1k R4 681k SHARED PIN BIASING FOR EQUAL ONE-SHOT TIMERS TA1 START TEST 1 DELAY TEST TEST 3 ONE SECOND DURATION SEQUENTIAL TEST PULSES AFTER AN ADJUSTABLE DELAY TIME Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Siicon Osciator Wide Frequency Range LTC69 1MHz to MHz ThinSOT Siicon Osciator Low Power, Wide Frequency Range LTC696/LTC697 1kHz to 1MHz or 4kHz ThinSOT Siicon Osciator Micropower, I SUPPLY = 35µA at 4kHz LTC693 Fixed Frequency Osciator, 3.768kHz to 8.19MHz.9% Accuracy, 11µs Start-Up Time, 15µA at 3kHz LTC699 TimerBox: Votage-Controed Siicon Osciator Fixed-Frequency or Votage-Controed Operation LTC6991 TimerBox: Resettabe Low Frequency Osciator Cock Periods up to 9.5 hours LTC699 TimerBox: Votage-Controed Puse Width Moduator (PWM) Simpe PWM with Wide Frequency Range LTC6994 TimerBox: Deay Bock/Debouncer Deay Rising Edge, Faing Edge or Both Edges 6 LT 711 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 1