LTC2656 Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/ C Max Reference DESCRIPTION FEATURES APPLICATIONS BLOCK DIAGRAM

Transcription

1 FEATURES n Precision 1ppm/ C Max Reference n Maximum INL Error: ±4LSB at 16 Bits n Guaranteed Monotonic over Temperature n Seectabe Interna or Externa Reference n 2.7V to 5.5V Suppy Range (LTC2656-L) n Integrated Reference Buffers n Utraow Crosstak Between DACs(<1nV s) n Power-On-Reset to Zero-Scae/Mid-scae n Asynchronous LDAC Update Pin n Tiny 2-Lead 4mm 5mm QFN and 2-Lead Thermay Enhanced TSSOP Packages APPLICATIONS n Mobie Communications n Process Contro and Industria Automation n Instrumentation n Automatic Test Equipment n Automotive DESCRIPTION LTC2656 Octa 16-/12-Bit Rai-to-Rai DACs with 1ppm/ C Max Reference The LTC 2656 is a famiy of octa 16-/12-bit rai-to-rai DACs with a precision integrated reference. The DACs have buit-in high performance, rai-to-rai, output buffers and are guaranteed monotonic. The LTC2656-L has a fu-scae output of 2.5V with the integrated 1ppm/ C reference and operates from a singe 2.7V to 5.5V suppy. The LTC2656-H has a fu-scae output of 4.96V with the integrated reference and operates from a 4.5V to 5.5V suppy. Each DAC can aso operate with an externa reference, which sets the DAC fu-scae output to two times the externa reference votage. These DACs communicate via a SPI/MICROWIRE compatibe 4-wire seria interface which operates at cock rates up to 5MHz. The LTC2656 incorporates a power-on reset circuit that is controed by the PORSEL pin. If PORSEL is tied to GND the DACs reset to zero-scae. If PORSEL is tied to V CC, the DACs reset to mid-scae. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents, incuding , BLOCK DIAGRAM COMP GND LO A B C D DAC A DAC B DAC C DAC D REGISTER REGISTER REGISTER REGISTER INTERNAL ERENCE REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER DAC H DAC G DAC F DAC E IN/OUT V CC H G F E INL (LSB) INL vs Code DAC A DAC B DAC C DAC D CODE DAC E DAC F DAC G DAC H TA1b CS/LD SCK CONTROL LOGIC DECODE POWER-ON RESET PORSEL SDO SDI LDAC 32-BIT SHIFT REGISTER CLR 2656 TA1a 1

2 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Suppy Votage (V CC )....3V to 6V CS/LD, SCK, SDI, LDAC, CLR, LO....3V to 6V A to H....3V to Min(V CC +.3V, 6V) IN/OUT, COMP....3V to Min(V CC +.3V, 6V) PORSEL, SDO....3V to Min(V CC +.3V, 6V) Operating Temperature Range LTC2656C... C to 7 C LTC2656I... 4 C to 85 C Maximum Junction Temperature C Storage Temperature Range to 15 C Lead Temperature (Sodering, 1 sec) FE Package... 3 C PIN CONFIGURATION LO 1 A 2 B 3 COMP 4 C 5 D 6 IN/OUT 7 LDAC 8 CS/LD 9 SCK 1 TOP VIEW 21 2 GND 19 V CC 18 H 17 G 16 F 15 E 14 PORSEL 13 CLR 12 SDO 11 SDI FE PACKAGE 2-LEAD PLASTIC TSSOP T JMAX = 15 C, θ JA = 38 C/W, θ JC = 1 C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB B 1 COMP 2 C 3 D 4 IN/OUT 5 LDAC 6 TOP VIEW A LO GND VCC CS/LD SCK SDI SDO UFD PACKAGE 2-LEAD (4mm 5mm) PLASTIC QFN T JMAX = 15 C, θ JA = 43 C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB H G F E PORSEL CLR 2

3 PRODUCT SELECTOR GUIDE LTC2656 B C UFD -L 16 #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = Tape and Ree RESOLUTION 16 = 16-Bit 12 = 12-Bit FULL-SCALE VOLTAGE, INTERNAL ERENCE MODE L = 2.5V H = 4.96V PACKAGE TYPE UFD = 2-Lead (4mm 5mm) Pastic QFN FE = 2-Lead Thermay Enhanced TSSOP TEMPERATURE GRADE C = Commercia Temperature Range ( C to 7 C) I = Industria Temperature Range ( 4 C to 85 C) ELECTRICAL GRADE (OPTIONAL) B = ±4LSB Maximum INL (16-Bit) C = ±12LSB Maximum INL (16-Bit) PRODUCT PART NUMBER Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 3

4 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION LTC2656BCFE-L16#PBF LTC2656BIFE-L16#PBF LTC2656BCUFD-L16#PBF LTC2656BIUFD-L16#PBF LTC2656BCFE-H16#PBF LTC2656BIFE-H16#PBF LTC2656BCUFD-H16#PBF LTC2656BIUFD-H16#PBF LTC2656CCFE-L16#PBF LTC2656CIFE-L16#PBF LTC2656CCUFD-L16#PBF LTC2656CIUFD-L16#PBF LTC2656CFE-L12#PBF LTC2656IFE-L12#PBF LTC2656CUFD-L12#PBF LTC2656IUFD-L12#PBF LTC2656CFE-H12#PBF LTC2656IFE-H12#PBF LTC2656CUFD-H12#PBF LTC2656IUFD-H12#PBF LTC2656BCFE-L16#TRPBF LTC2656BIFE-L16#TRPBF LTC2656BCUFD-L16#TRPBF LTC2656BIUFD-L16#TRPBF LTC2656BCFE-H16#TRPBF LTC2656BIFE-H16#TRPBF LTC2656BCUFD-H16#TRPBF LTC2656BIUFD-H16#TRPBF LTC2656CCFE-L16#TRPBF LTC2656CIFE-L16#TRPBF LTC2656CCUFD-L16#TRPBF LTC2656CIUFD-L16#TRPBF LTC2656CFE-L12#TRPBF LTC2656IFE-L12#TRPBF LTC2656CUFD-L12#TRPBF LTC2656IUFD-L12#TRPBF LTC2656CFE-H12#TRPBF LTC2656IFE-H12#TRPBF LTC2656CUFD-H12#TRPBF LTC2656IUFD-H12#TRPBF LTC2656FE-L16 LTC2656FE-L16 56L16 56L16 LTC2656FE-H16 LTC2656FE-H16 56H16 56H16 LTC2656CFE-L16 LTC2656CFE-L16 6CL16 6CL16 LTC2656FE-L12 LTC2656FE-L12 56L12 56L12 LTC2656FE-H12 LTC2656FE-H12 56H12 56H12 2-Lead Thermay Enhanced TSSOP 2-Lead Thermay Enhanced TSSOP 2-Lead (4mm 5mm) Pastic QFN 2-Lead (4mm 5mm) Pastic QFN 2-Lead Thermay Enhanced TSSOP 2-Lead Thermay Enhanced TSSOP 2-Lead (4mm 5mm) Pastic QFN 2-Lead (4mm 5mm) Pastic QFN 2-Lead Thermay Enhanced TSSOP 2-Lead Thermay Enhanced TSSOP 2-Lead (4mm 5mm) Pastic QFN 2-Lead (4mm 5mm) Pastic QFN 2-Lead Thermay Enhanced TSSOP 2-Lead Thermay Enhanced TSSOP 2-Lead (4mm 5mm) Pastic QFN 2-Lead (4mm 5mm) Pastic QFN 2-Lead Thermay Enhanced TSSOP 2-Lead Thermay Enhanced TSSOP 2-Lead (4mm 5mm) Pastic QFN 2-Lead (4mm 5mm) Pastic QFN TEMPERATURE RANGE C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C C to 7 C 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: MAXIMUM INL ±4 ±4 ±4 ±4 ±4 ±4 ±4 ±4 ±12 ±12 ±12 ±12 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 4

5 ELECTRICAL CHARACTERISTICS LTC2656 The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 2.7V to 5.5V, unoaded uness otherwise specified. LTC2656B-L16/LTC2656C-L16/LTC2656-L12 (interna reference = 1.25V) SYMBOL PARAMETER DC Performance SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Output Span Interna Reference to 2.5 V Externa Reference = V EXT to 2 V EXT V PSR Power Suppy Rejection V CC ±1% 8 db R OUT DC Output Impedance V CC = 5V ±1%, Interna Reference, Mid-Scae, 15mA I OUT 15mA I SC Reference DC Crosstak (Note 5) Short-Circuit Output Current (Note 6) V CC = 3V ±1%, Interna Reference, Mid-Scae, 7.5mA I OUT 7.5mA Due to Fu-Scae Output Change Due to Load Current Change Due to Powering Down (per Channe) V CC = 5.5V, V EXT = 2.75V Code: Zero-Scae, Forcing Output to V CC Code: Fu-Scae, Forcing Output to GND V CC = 2.7V, V EXT = 1.35V Code: Zero-Scae, Forcing Output to V CC Code: Fu-Scae, Forcing Output to GND.4.15 Ω.4.15 Ω ±1.5 ±2 ± µv µv/ma µv Reference Output Votage V Reference Temperature Coefficient C-Grade (Note 7) I-Grade (Note 7) ±2 ±2 ma ma ma ma ±1 ppm/ C ppm/ C Reference Line Reguation V CC ±1% 8 db Reference Short-Circuit Current V CC = 5.5V, Forcing Output to GND 3 5 ma COMP Pin Short-Circuit Current V CC = 5.5V, Forcing Output to GND 6 2 µa Reference Load Reguation V CC = 3V ±1% or 5V ±1%, I OUT = 1µA Sourcing Reference Output Votage Noise Density CONDITIONS LTC2656B-L16/ LTC2656-L12 LTC2656C-L16 MIN TYP MAX MIN TYP MAX Resoution Bits Monotonicity (Note 3) Bits DNL Differentia Noninearity (Note 3) ±.1 ±.5 ±.3 ±1 LSB INL Integra Noninearity (Note 3) LTC2656B-L16: V CC = 5.5V, V = 2.5V LTC2656C-L16: V CC = 5.5V, V = 2.5V Load Reguation V CC = 5V ±1%, Interna Reference, Mid-Scae, 15mA I OUT 15mA V CC = 3V ±1%, Interna Reference, Mid-Scae, 7.5mA I OUT 7.5mA ±.5 ±1 ±2 ±6 UNITS 4 mv/ma C COMP = C IN/OUT =.1µF at f = 1kHz 3 nv/ Hz ±4 ±12 LSB LSB LSB/mA LSB/mA ZSE Zero-Scae Error mv V OS Offset Error V = 1.25V (Note 4) ±1 ±2 ±1 ±2 mv V OS Temperature Coefficient 2 2 µv/ C GE Gain Error ±.2 ±.1 ±.2 ±.1 %FSR Gain Temperature Coefficient 1 1 ppm/ C 5

6 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 2.7V to 5.5V, unoaded uness otherwise specified. LTC2656B-L16/LTC2656C-L16/LTC2656-L12 (interna reference = 1.25V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Suppy Reference Input Range Externa Reference Mode (Note 13).5 V CC /2 V Reference Input Current.1 1 µa Reference Input Capacitance (Note 9) 4 pf V CC Positive Suppy Votage For Specified Performance V I CC Suppy Current (Note 8) V CC = 5V, Interna Reference On V CC = 5V, Interna Reference Off V CC = 3V, Interna Reference On V CC = 3V, Interna Reference Off I SHDN Digita I/O Suppy Current in Shutdown Mode (Note 8) V IH Digita Input High Votage V CC = 3.6V to 5.5V V CC = 2.7V to 3.6V V IL Digita Input Low Votage V CC = 4.5V to 5.5V V CC = 2.7V to 4.5V V CC = 5V 3 µa V OH Digita Output High Votage Load Current = 1µA V CC.4 V V OL Digita Output Low Votage Load Current = 1µA.4 V I LK Digita Input Leakage V IN = GND to V CC ±1 µa C IN Digita Input Capacitance (Note 9) 8 pf AC Performance t S Setting Time (Note 1) ±.24% (±1LSB at 12 Bits) ±.15% (±1LSB at 16 Bits) Setting Time for 1LSB Step ±.24% (±1LSB at 12 Bits) ±.15% (±1LSB at 16 Bits) Votage Output Sew Rate 1.8 V/µs Capacitive Load Driving 1 pf Gitch Impuse (Note 11) At Mid-Scae Transition, V CC = 3V 3 nv s DAC-to-DAC Crosstak (Note 12) Due to Fu-Scae Output Change, C COMP = C OUT = No Load ma ma ma ma V V V V µs µs µs µs 2 nv s Mutipying Bandwidth 15 khz e n Output Votage Noise Density At f = 1kHz At f = 1kHz Output Votage Noise.1Hz to 1Hz, Interna Reference.1Hz to 2kHz, Interna Reference nv/ Hz nv/ Hz µv P-P µv P-P 6

7 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 4.5V to 5.5V, unoaded uness otherwise specified. LTC2656B-H16/LTC2656-H12 (interna reference = 2.48V) SYMBOL PARAMETER DC Performance CONDITIONS LTC2656-H12 LTC2656B-H16 MIN TYP MAX MIN TYP MAX Resoution Bits Monotonicity (Note 3) Bits DNL Differentia Noninearity (Note 3) ±.1 ±.5 ±.3 ±1 LSB INL Integra Noninearity (Note 3) V CC = 5.5V, V = 2.5V ±.5 ±1 ±2 ±4 LSB Load Reguation V CC = 5V ±1%, Interna Reference, Mid-Scae, 15mA I OUT 15mA UNITS LSB/mA ZSE Zero-Scae Error mv V OS Offset Error V = 2.48V (Note 4) ±1 ±2 ±1 ±2 mv V OS Temperature Coefficient 2 2 µv/ C GE Gain Error ±.2 ±.1 ±.2 ±.1 %FSR Gain Temperature Coefficient 1 1 ppm/ C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Output Span Interna Reference to 4.96 V Externa Reference = V EXT to 2 V EXT V PSR Power Suppy Rejection V CC ±1% 8 db R OUT DC Output Impedance V CC = 5V ±1%, Interna Reference, Mid-Scae, 15mA I OUT 15mA I SC Reference DC Crosstak (Note 5) Short-Circuit Output Current (Note 6) Due to Fu-Scae Output Change Due to Load Current Change Due to Powering Down (per Channe) V CC = 5.5V, V EXT = 2.75V Code: Zero-Scae, Forcing Output to V CC Code: Fu-Scae, Forcing Output to GND.4.15 Ω 2 2 ±1.5 ±2 ± µv µv/ma µv Reference Output Votage V Reference Temperature Coefficient C-Grade (Note 7) I-Grade (Note 7) ±2 ±2 ma ma ±1 ppm/ C ppm/ C Reference Line Reguation V CC ±1% 8 db Reference Short-Circuit Current V CC = 5.5V, Forcing Output to GND 3 5 ma COMP Pin Short-Circuit Current V CC = 5.5V, Forcing Output to GND 6 2 µa Reference Load Reguation V CC = 5V ±1%, I OUT = 1µA Sourcing 4 mv/ma Reference Output Votage Noise Density C COMP = C IN/OUT =.1µF at f = 1kHz 35 nv/ Hz Reference Input Range Externa Reference Mode (Note 13).5 V CC /2 V Reference Input Current.1 1 µa Reference Input Capacitance (Note 9) 4 pf 7

8 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 4.5V to 5.5V, unoaded uness otherwise specified. LTC2656B-H16/LTC2656-H12 (interna reference = 2.48V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Suppy V CC Positive Suppy Votage For Specified Performance V I CC Suppy Current (Note 8) V CC = 5V, Interna Reference On V CC = 5V, Interna Reference Off I SHDN Digita I/O Suppy Current in Shutdown Mode (Note 8) V CC = 5V 3 µa V IH Digita Input High Votage V CC = 4.5V to 5.5V 2.4 V V IL Digita Input Low Votage V CC = 4.5V to 5.5V.8 V V OH Digita Output High Votage Load Current = 1µA V CC.4 V V OL Digita Output Low Votage Load Current = 1µA.4 V I LK Digita Input Leakage V IN = GND to V CC ±1 µa C IN Digita Input Capacitance (Note 9) 8 pf AC Performance t S Setting Time (Note 1) ±.24% (±1LSB at 12 Bits) ±.15% (±1LSB at 16 Bits) Setting Time for 1LSB Step ±.24% (±1LSB at 12 Bits) ±.15% (±1LSB at 16 Bits) Votage Output Sew Rate 1.8 V/µs Capacitive Load Driving 1 pf Gitch Impuse (Note 11) At Mid-Scae Transition, V CC = 5V 6 nv s DAC-to-DAC Crosstak (Note 12) Due to Fu-Scae Output Change, C COMP = C OUT = No Load ma ma µs µs µs µs 3 nv s Mutipying Bandwidth 15 khz e n Output Votage Noise Density At f = 1kHz At f = 1kHz Output Votage Noise.1Hz to 1Hz, Interna Reference.1Hz to 2kHz, Interna Reference nv/ Hz nv/ Hz µv P-P µv P-P 8

9 ELECTRICAL CHARACTERISTICS LTC2656 The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. LTC2656B-L16/LTC2656C-L16/LTC2656-L12/LTC2656B-H16/LTC2656-H12 (see Figure 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC = 2.7V to 5.5V t 1 SDI Vaid to SCK Setup 4 ns t 2 SDI Vaid to SCK Hod 4 ns t 3 SCK High Time 9 ns t 4 SCK Low Time 9 ns t 5 CS/LD Puse Width 1 ns t 6 LSB SCK High to CS/LD High 7 ns t 7 CS/LD Low to SCK High 7 ns t 8 SDO Propagation Deay from SCK Faing Edge C LOAD = 1pF V CC = 4.5V to 5.5V V CC = 2.7V to 4.5V t 9 CLR Puse Width 2 ns t 1 CS/LD High to SCK Positive Edge 7 ns t 12 LDAC Puse Width 15 ns t 13 CS/LD High to LDAC High or Low Transition 2 ns SCK Frequency 5% Duty Cyce 5 MHz 2 45 ns ns Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A votages are with respect to GND. Note 3: Linearity and monotonicity are defined from code kl to code 2 N 1, where N is the resoution and kl is the ower end code for which no output imiting occurs. For V = 2.5V and N = 16, kl = 128 and inearity is defined from code 128 to code For V = 2.5V and N = 12, kl = 8 and inearity is defined from code 8 to code 4,95. Note 4: Inferred from measurement at code 128 (LTC ) or code 8 (LTC ). Note 5: DC crosstak is measured with V CC = 5V and using interna reference with the measured DAC at mid-scae. Note 6: This IC incudes current imiting that is intended to protect the device during momentary overoad conditions. Junction temperature can exceed the rated maximum during current imiting. Continuous operation above the specified maximum operating junction temperature may impair device reiabiity. Note 7: Temperature coefficient is cacuated by dividing the maximum change in output votage by the specified temperature range. Note 8: Digita inputs at V or V CC. Note 9: Guaranteed by design and not production tested. Note 1: Interna reference mode. DAC is stepped 1/4 scae to 3/4 scae and 3/4 scae to 1/4 scae. Load is 2kΩ in parae with 2pF to GND. Note 11: V CC = 5V, interna reference mode. DAC is stepped ±1LSB between haf scae and haf scae 1LSB. Load is 2k in parae with 2pF to GND. Note 12: DAC-to-DAC crosstak is the gitch that appears at the output of one DAC due to a fu-scae change at the output of another DAC. It is measured with V CC = 5V and using interna reference, with the measured DAC at mid-scae. Note 13: Gain error specification may be degraded for reference input votages ess than 1V. See Gain Error vs Reference Input Votage curve in the Typica Performance Characteristics section. 9

10 TYPICAL PERFORMANCE CHARACTERISTICS LTC2656-L16 T A = 25 C uness otherwise noted. Integra Noninearity (INL) Differentia Noninearity (DNL) INL vs Temperature 4 V CC = 3V 1. V CC = 3V 4 V CC = 3V 3 3 INL (LSB) DNL (LSB).5 INL (LSB) INL (POS) INL (NEG) CODE CODE TEMPERATURE ( C) 2656 G G G3 1. DNL vs Temperature V CC = 3V OUT Votage vs Temperature V CC = 3V DNL (LSB).5.5 DNL (POS) DNL (NEG) V (V) TEMPERATURE ( C) 2656 G TEMPERATURE ( C) 2656 G5 Setting to ±1LSB Rising Setting to ±1LSB Faing CS/LD 3V/DIV 1µV/DIV 3/4 SCALE TO 1/4 SCALE STEP V CC = 3V, V FS = 2.5V R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 1µV/DIV 8.9µs 1/4 SCALE TO 3/4 SCALE STEP V CC = 3V, V FS = 2.5V R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS CS/LD 3V/DIV 8.7µs 2µs/DIV 2µs/DIV 2656 G G7 1

11 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C uness otherwise noted. LTC2656-H Integra Noninearity (INL) Differentia Noninearity (DNL) INL vs Temperature V CC = 5V 1. V CC = 5V 4 V CC = 5V 3 INL (LSB) DNL (LSB).5 INL (LSB) INL (POS) INL (NEG) CODE CODE TEMPERATURE ( C) 2656 G G G1 1. DNL vs Temperature V CC = 5V 2.54 OUT Votage vs Temperature V CC = 5V DNL (LSB).5.5 DNL (POS) DNL (NEG) V (V) TEMPERATURE ( C) 2656 G TEMPERATURE ( C) 2656 G12 Setting to ±1LSB Rising Setting to ±1LSB Faing CS/LD 5V/DIV 25µV/DIV 1/4 SCALE TO 3/4 SCALE STEP V CC = 5V, V FS = 4.96V 7.9µs R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 25µV/DIV CS/LD 5V/DIV 6.1µs 3/4 SCALE TO 1/4 SCALE STEP V CC = 5V, V FS = 4.96V R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 2µs/DIV 2µs/DIV 2656 G G14 11

12 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C uness otherwise noted. LTC INL (LSB) Integra Noninearity (INL) Differentia Noninearity (DNL) Setting to ±1LSB (12 Bit) Rising V CC = 5V V = 2.48V CODE 495 DNL (LSB) V CC = 5V V = 2.48V CODE 495 CS/LD 5V/DIV 1mV/DIV 1/4 SCALE TO 3/4 SCALE STEP V CC = 5V, V FS = 4.95V 4.6µs R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 2µs/DIV 2656 G17 LTC G G16 (mv) Load Reguation V CC = 5V (LTC2656-H) V CC = 3V (LTC2656-L) INTERNAL. CODE = MID-SCALE I OUT (ma) (V) Current Limiting V CC = 5V (LTC2656-H) V CC = 3V (LTC2656-L) INTERNAL. CODE = MID-SCALE I OUT (ma) (V) Headroom at Rais vs Output Current 3V SOURCING (LTC2656-L) 3V SINKING (LTC2656-L) 5V SOURCING 5V SINKING I OUT (ma) 2656 G G G2 1. Offset Error vs Temperature Zero-Scae Error vs Temperature Gain Error vs Temperature OFFSET ERROR (mv) ZERO-SCALE ERROR (mv) GAIN ERROR (LSB) TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) 3656 G G G23 12

13 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C uness otherwise noted. LTC OFFSET ERROR (mv) Offset Error vs Reference Input Gain Error vs Reference Input I CC Shutdown vs V CC V CC = 5.5V OFFSET ERROR OF 8 CHANNELS ERENCE VOLTAGE (V) 2.5 GAIN ERROR (LSBs) V CC = 5.5V GAIN ERROR OF 8 CHANNELS ERENCE VOLTAGE (V) 2.5 I CC (na) V CC (V) 2656 G G G Suppy Current vs Logic Votage Hardware CLR to Mid-Scae Hardware CLR to Zero-Scae SWEEP SCK, SDI, CS/LD BETWEEN V AND V CC 1V/DIV 1V/DIV V CC = 5V V = 2.48V CODE = FULL-SCALE I CC (ma) V CC = 5V (LTC2656-H) V CC = 5V V = 2.48V CODE = FULL-SCALE 2.4 V CC = 3V (LTC2656-L) CLR 5V/DIV CLR 5V/DIV LOGIC VOLTAGE (V) 1µs/DIV 2656 G28 1µs/DIV 2656 G G27 MAGNITUDE (db) k Mutipying Bandwidth Large-Signa Response Mid-Scae Gitch Impuse V CC = 5V V (DC) = 2V V (AC) =.2V P-P CODE = FULL-SCALE 1k 1k 1M FREQUENCY (Hz) 2656 G3 1V/DIV V CC = 5V V = 2.48V ZERO-SCALE TO FULL-SCALE 2.5µs/DIV 2656 G31 CS/LD 5V/DIV 5mV/DIV 5mV/DIV 2µs/DIV V CC = 5V, 6nV s TYP (LTC2656-H16) V CC = 3V, 3nV s TYP (LTC2656-L16) 2656 G32 13

14 TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C uness otherwise noted. LTC2656 DAC-to-DAC Crosstak (Dynamic) Power-On Reset Gitch Power-On Reset to Mid-Scae ONE DAC SWITCH -FS 2V/DIV LTC2656-H16, V CC = 5V, 3nV s TYP C COMP = C OUT = NO LOAD V CC 2V/DIV V CC 2V/DIV LTC2656-H 2mV/DIV 2mV/DIV LTC2656-H16, V CC = 5V, <1nV s TYP C COMP = C OUT =.1µF 1mV/DIV ZERO-SCALE 1V/DIV 2µs/DIV 2µs/DIV 25µs/DIV 2656 G G G35 NOISE VOLTAGE (nv/ Hz) Noise Votage vs Frequency LTC2656-H V CC = 5V CODE = MID-SCALE INTERNAL C COMP = C OUT =.1µF 5µV/DIV.1Hz to 1Hz Votage Noise V CC = 5V, V FS = 2.5V CODE = MID-SCALE INTERNAL C COMP = C OUT =.1µF 2µV/DIV Reference.1Hz to 1Hz Votage Noise = 1.25V C COMP = C OUT =.1µF LTC2656-L k 1k 1k 1M FREQUENCY (Hz) 1 SEC/DIV 2656 G37 1 SEC/DIV 2656 G G36 14

15 PIN FUNCTIONS (TSSOP/QFN) LO (Pin 1/Pin 19): Reference Low Pin. The votage at this pin sets the zero-scae votage of a DACs. LO shoud be tied to GND. A to H (Pins 2, 3, 5, 6, 15, 16, 17, 18/Pins 2, 1, 3, 4, 13, 14, 15, 16): DAC Anaog Votage Outputs. The output range is V to 2 times the votage at the IN/OUT pin. COMP (Pin 4/Pin 2): Interna Reference Compensation Pin. For ow noise and reference stabiity, tie a.1µf capacitor to GND. Connect COMP to GND to aow the use of externa reference at start-up. IN/OUT (Pin 7/Pin 5): This pin acts as the interna reference output in interna reference mode and acts as the reference input pin in externa reference mode. When acting as an output, the nomina votage at this pin is 1.25V for L options and 2.48V for H options. For ow noise and reference stabiity tie a capacitor from this pin to GND. This capacitor vaue must be C COMP, where C COMP is the capacitance tied to the COMP pin. In externa reference mode, the aowabe reference input votage range is.5v to V CC /2. LDAC (Pin 8/Pin 6): Asynchronous DAC Update Pin. If CS/LD is high, a faing edge on LDAC immediatey updates the DAC register with the contents of the input register (simiar to a software update). If CS/LD is ow when LDAC goes ow, the DAC register is updated after CS/LD returns high. A ow on the LDAC pin powers up the DAC outputs. A the software power-down commands are ignored if LDAC is ow when CS/LD goes high. CS/LD (Pin 9/Pin 7): Seria Interface Chip Seect/Load Input. When CS/LD is ow, SCK is enabed for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabed and the specified command (see Tabe 1) is executed. LTC2656 SCK (Pin 1/Pin 8): Seria Interface Cock Input. CMOS and TTL compatibe. SDI (Pin 11/Pin 9): Seria Interface Data Input. Data is appied to SDI for transfer to the device at the rising edge of SCK (Pin 1). The LTC2656 accepts input word engths of either 24 or 32 bits. SDO (Pin 12/Pin 1): Seria Interface Data Output. This pin is used for daisy-chain operation. The seria output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is deayed 32 SCK rising edges before being output at the next faing edge. This pin is continuousy driven and does not go high impedance when CS/LD is taken active high. CLR (Pin 13/Pin 11): Asynchronous Cear Input. A ogic ow at this eve-triggered input cears a registers and causes the DAC votage outputs to drop to V if the PORSEL pin is tied to GND. If the PORSEL pin is tied to V CC, a ogic ow at CLR sets a registers to mid-scae code and causes the DAC votage outputs to go to mid-scae. PORSEL (Pin 14/Pin 12): Power-On Reset Seect Pin. If tied to GND, the DAC resets to zero-scae at power-up. If tied to V CC, the DAC resets to mid-scae at power-up. V CC (Pin 19/Pin 17): Suppy Votage Input. For -L options, 2.7V V CC 5.5V and for -H options, 4.5V V CC 5.5V. GND (Pin 2/Pin 18): Ground. Exposed Pad (Pin 21/Pin 21): Ground. Must be sodered to PCB Ground. 15

16 BLOCK DIAGRAM COMP GND LO A B C D DAC A DAC B DAC C DAC D REGISTER REGISTER REGISTER REGISTER INTERNAL ERENCE REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER DAC H DAC G DAC F DAC E IN/OUT V CC H G F E CS/LD SCK CONTROL LOGIC DECODE POWER-ON RESET PORSEL SDO SDI LDAC 32-BIT SHIFT REGISTER CLR 2656 BD 16

17 TIMING DIAGRAMS LTC2656 t 1 t 2 t 3 t 4 t 6 SCK t 1 SDI t 5 t 7 CS/LD t 8 SDO LDAC t 13 t F1a Figure 1a CS/LD t 13 LDAC 2656 F1 Figure 1b 17

18 OPERATION The LTC2656 is a famiy of octa votage output DACs in 2-ead 4mm 5mm QFN and in 2-ead thermay enhanced TSSOP packages. Each DAC can operate rai-to-rai in externa reference mode, or with its fu-scae votage set by an integrated reference. Four combinations of accuracy (16-bit and 12-bit), and fu-scae votage (2.5V or 4.96V) are avaiabe. The LTC2656 is controed using a 4-wire SPI/MICROWIRE compatibe interface. Power-On Reset The LTC2656-L/ LTC2656-H cear the output to zero-scae if the PORSEL pin is tied to GND, when power is first appied, making system initiaization consistent and repeatabe. For some appications, downstream circuits are active during DAC power-up and may be sensitive to nonzero outputs from the DAC during this time. The LTC2656 contains circuitry to reduce the power-on gitch. The anaog outputs typicay rise ess than 1mV above zero-scae during power on if the power suppy is ramped to 5V in 1ms or more. In genera, the gitch ampitude decreases as the power suppy ramp time is increased. See Power-On Reset Gitch in the Typica Performance Characteristics. Aternativey, if the PORSEL pin is tied to V CC, the LTC2656 L/ LTC2656-H sets the output to mid-scae when power is first appied. Power Suppy Sequencing and Start-Up For the LTC2656 famiy of parts, the interna reference is powered up at start-up by defaut. If an externa reference is to be used, the COMP pin must be hardwired to GND. Having COMP hardwired to GND at power up wi cause the IN/OUT pin to become high impedance and wi aow for the use of an externa reference at startup. However in this configuration, the interna reference wi sti be on even though it is disconnected from the IN/OUT pin and wi draw suppy current. In order to use externa reference after power-up, the command Seect Externa Reference (111b) shoud be used to turn the interna reference off (see Tabe 1.) The votage at IN/OUT shoud be kept within the range.3v IN/OUT V CC +.3V if the externa reference is to be used (see Absoute Maximum Ratings). Particuar care shoud be taken to observe these imits during power 18 suppy turn-on and turn-off sequences, when the votage at V CC is in transition. Transfer Function The digita-to-anaog transfer function is: (IDEAL) = k 2 N 2 V V LO ( ) + V LO where k is the decima equivaent of the binary DAC input code, N is the resoution of the DAC, and V is the votage at the IN/OUT pin. The resuting DAC output span is V to 2 V, as it is necessary to tie LO to GND. V is nominay 1.25V for LTC2656-L and 2.48V for LTC2656-H, in interna reference mode. Tabe 1. Command and Address Codes COMMAND* C3 C2 C1 C Write to Input Register n 1 Update (Power Up) DAC Register n 1 Write to Input Register n, Update (Power Up) A 1 1 Write to and Update (Power Up) n 1 Power Down n 1 1 Power Down Chip (A DACs and Reference) 1 1 Seect Interna Reference (Power-Up Reference) Seect Externa Reference (Power-Down Reference) No Operation ADDRESS (n)* A3 A2 A1 A DAC A 1 DAC B 1 DAC C 1 1 DAC D 1 DAC E 1 1 DAC F 1 1 DAC G DAC H A DACs *Command and address codes not shown are reserved and shoud not be used. Seria Interface The CS/LD input is eve triggered. When this input is taken ow, it acts as a chip-seect signa, powering on the SDI and SCK buffers and enabing the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges.

19 OPERATION The 4-bit command, C3-C, is oaded first; foowed by the 4-bit DAC address, A3-A; and finay the 16-bit data word. For the LTC the data word comprises the 16-bit input code, ordered MSB-to-LSB. For the LTC the data word comprises the 12-bit input code, ordered MSBto-LSB, foowed by four don t care bits. Data can ony be transferred to the LTC2656 when the CS/LD signa is ow. The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The compete sequence is shown in Figure 2a. The command (C3-C) and address (A3-A) assignments are shown in Tabe 1. The first four commands in the tabe consist of write and update operations. A write operation oads a 16-bit data word from the 32-bit shift register into the input register of the seected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16- or 12-bit input code, and is converted to an anaog votage at the DAC output. The update operation aso powers up the seected DAC if it had been in power-down mode. The data path and registers are shown in the Bock Diagram. Whie the minimum input word is 24 bits, it may optionay be extended to 32 bits. To use the 32-bit word width, 8 don t-care bits must be transferred to the device first, foowed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. The 32-bit word is required for daisy-chain operation, and is aso avaiabe to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). The 16-bit data word is ignored for a commands that do not incude a write operation. Daisy-Chain Operation The seria output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is deayed 32 SCK rising edges before being output at the next SCK faing edge. The SDO pin is continuousy driven and does not go high impedance when CS/LD is taken active high. The SDO output can be used to faciitate contro of mutipe seria devices from a singe 3-wire seria port (i.e., SCK, SDI and CS/LD). Such a daisy-chain series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices LTC2656 are thus connected in series, effectivey forming a singe input shift register which extends through the entire chain. Because of this, the devices can be addressed and controed individuay by simpy concatenating their input words; the first instruction addresses the ast device in the chain and so forth. The SCK and CS/LD signas are common to a devices in the series. In use, CS/LD is first taken ow. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is compete, CS/LD is taken high, competing the instruction sequence for a devices simutaneousy. A singe device can be controed by using the no-operation command (1111) for the other devices in the chain. Power-Down Mode For power-constrained appications, power-down mode can be used to reduce the suppy current whenever ess than eight DAC outputs are needed. When in power down, the buffer ampifiers, bias circuits and integrated reference circuits are disabed and draw essentiay zero current. The DAC outputs are put into a high impedance state, and the output pins are passivey pued to ground through individua 8k resistors. Input- and DAC-register contents are not disturbed during power down. Any channe or combination of DAC channes can be put into power-down mode by using command 1b in combination with the appropriate DAC address, (n). The integrated reference is automaticay powered down when externa reference is seected using command 111b. In addition, a the DAC channes and the integrated reference together can be put into power-down mode using power-down chip command 11b. For a power-down commands the 16-bit data word is ignored. Norma operation resumes by executing any command which incudes a DAC update, in software as shown in Tabe 1 or by taking the asynchronous LDAC pin ow. The seected DAC is powered up as its votage output is updated. When a DAC which is in a powered-down state is powered up and updated, norma setting is deayed. If ess than eight DACs are in a powered-down state prior to the update command, the power-up deay time is 12µs. If, on the other hand, a eight DACs and the integrated reference 19

20 OPERATION C3 C2 C1 C A3 A2 A1 A D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D CS/LD SCK SDI 2656 F2a COMMAND WORD ADDRESS WORD DATA WORD X X X X X X X C3 C2 C1 C A3 A2 A1 A D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D CS/LD 24-BIT INPUT WORD SCK Figure 2a. LTC Bit Load Sequence (Minimum Input Word) LTC SDI Data Word: 12-Bit Input Code + 4 Don t-care Bits SDI COMMAND WORD ADDRESS WORD DATA WORD X DON T CARE X X X X X X X C3 C2 C1 C A3 A2 A1 A D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D CURRENT 32-BIT INPUT WORD PREVIOUS 32-BIT INPUT WORD SDO X t 1 t F2b SCK t 3 t4 D14 D15 SDI t8 SDO PREVIOUS D15 PREVIOUS D14 Figure 2b. LTC Bit Load Sequence LTC SDI/SDO Data Word: 12-Bit Input Code + 4 Don t-care Bits 2

21 OPERATION are powered down, then the main bias generation circuit bock has been automaticay shut down in addition to the individua DAC ampifiers and integrated reference. In this case, the power-up deay time is 14µs. The power up of the integrated reference depends on the command that powered it down. If the reference is powered down using the seect externa reference command (111b), then it can ony be powered back up using seect interna reference command (11b). However if the reference was powered down using power-down chip command (11b), then in addition to seect interna reference command (11b), any command that powers up the DACs wi aso power up the integrated reference. Asynchronous DAC Update Using LDAC In addition to the update commands shown in Tabe 1, the LDAC pin asynchronousy updates a the DAC registers with the contents of the input registers. If CS/LD is high, a ow on the LDAC pin causes a the DAC registers to be updated with the contents of the input registers. If CS/LD is ow, a ow going puse on the LDAC pin before the rising edge of CS/LD powers up a the DAC outputs but does not cause the output to be updated. If LDAC remains ow after the rising edge of CS/LD, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC outputs are updated. The DAC outputs are powered up when LDAC is taken ow, independent of the state of CS/LD. The integrated reference is aso powered up if it was powered down using power-down chip (11b) command. The integrated reference wi not power up when LDAC is taken ow, if it was powered down using seect externa reference (111b) command. If LDAC is ow at the time CS/LD goes high, it inhibits any software power-down command (power down n, powerdown chip, seect externa reference) that was specified in the input word. Reference Modes For appications where an accurate externa reference is not avaiabe, the LTC2656 has a user-seectabe, integrated LTC2656 reference. The LTC2656-L has a 1.25V reference that provides a fu-scae DAC output of 2.5V. The LTC2656-H has a 2.48V reference that provides a fu-scae DAC output of 4.96V. Both references exhibit a typica temperature drift of 2ppm/ C. Interna reference mode can be seected by using command 11b, and is the power-on defaut. A buffer is needed if the interna reference is required to drive externa circuitry. For reference stabiity and ow noise, it is recommended that a.1µf capacitor be tied between COMP and GND. In this configuration, the interna reference can drive up to.1µf capacitive oad without any stabiity probems. In order to ensure stabe operation, the capacitive oad on the IN/OUT pin shoud not exceed the capacitive oad on the COMP pin. The DAC can aso operate in externa reference mode using command 111b. In this mode, the IN/OUT pin acts as an input that sets the DAC s reference votage. The input is high impedance and does not oad the externa reference source. The acceptabe votage range at this pin is.5v IN/OUT V CC /2. The resuting fu-scae output votage is 2 V IN/OUT. For using externa reference at start-up, see the Power Suppy Sequencing and Start-Up section. Integrated Reference Buffers Each of the eight DACs in LTC2656 has its own integrated high performance reference buffer. The buffers have very high input impedance and do not oad the reference votage source. These buffers shied the reference votage from gitches caused by DAC switching and thus minimize DACto-DAC dynamic crosstak. Typicay DAC-to-DAC crosstak is ess than 3nV s. By tying.1µf capacitors between COMP and GND, and aso between IN/OUT and GND, this number can be reduced to ess than 1nV s. See the curve DAC-to-DAC Dynamic Crosstak in the Typica Performance Characteristics section. Votage Outputs Each of the LTC2656 s eight rai-to-rai output ampifiers contained in these parts has a guaranteed oad reguation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load reguation is a measure of the ampifier s abiity to maintain the rated votage accuracy over a wide range of 21

22 OPERATION oad conditions. The measured change in output votage per miiampere of forced oad current change is expressed in LSB/mA. DC output impedance is equivaent to oad reguation, and may be derived from it by simpy cacuating a change in units from LSB/mA to Ohms. The ampifiers DC output impedance is.4ω when driving a oad we away from the rais. When drawing a oad current from either rai, the output votage headroom with respect to that rai is imited by the 3Ω typica channe resistance of the output devices; e.g., when sinking 1mA, the minimum output votage = 3Ω 1mA = 3mV. See the graph Headroom at Rais vs Output Current in the Typica Performance Characteristics section. The ampifiers are stabe driving capacitive oads of up to 1pF. Board Layout The exceent oad reguation and DC crosstak performance of these devices is achieved in part by keeping signa and power grounds separate. The PC board shoud have separate areas for the anaog and digita sections of the circuit. This keeps digita signas away from sensitive anaog signas and faciitates the use of separate digita and anaog ground panes which have minima capacitive and resistive interaction with each other. Digita and anaog ground panes shoud be joined at ony one point, estabishing a system star ground as cose to the device s ground pin as possibe. Ideay, the anaog ground pane shoud be ocated on the component side of the board, and shoud be aowed to run under the part to shied it from noise. Anaog ground shoud be a continuous and uninterrupted pane, except for necessary ead pads and vias, with signa traces on another ayer. The GND pin functions as a return path for power suppy currents in the device and shoud be connected to anaog ground. The LO pin shoud be connected to the system star ground. Resistance from the LO pin to the system star ground shoud be as ow as possibe. Rai-to-Rai Output Considerations In any rai-to-rai votage output device, the output is imited to votages within the suppy range. Since the anaog outputs of the device cannot go beow ground, they may imit the owest codes as shown in Figure 3b. Simiary, imiting can occur in externa reference mode near fu-scae when the IN/OUT pin is at V CC /2. If V IN/OUT = V CC /2 and the DAC fu-scae error (FSE) is positive, the output for the highest codes imits at V CC are shown in Figure 3c. No fu-scae imiting can occur if V IN/OUT (V CC FSE)/2. Offset and inearity are defined and tested over the region of the DAC transfer function where no output imiting can occur. V = V CC POSITIVE FSE V = V CC OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (3c) 2656 F3 NEGATIVE OFFSET V INPUT CODE (3b) 32,768 65,535 INPUT CODE (3a) 22 Figure 3. Effects of Rai-to-Rai Operation on a DAC Transfer Curve. (3a) Overa Transfer Function (3b) Effect of Negative Offset for Codes Near Zero-Scae (3c) Effect of Positive Fu-Scae Error for Codes Near Fu-Scae

23 PACKAGE DESCRIPTION FE Package 2-Lead Pastic TSSOP (4.4mm) (Reference LTC DWG # ) Exposed Pad Variation CB LTC (.152) * ( ) 3.86 (.152) ± ±.1 SEE NOTE (.18).45 ± (.18) 6.4 (.252) BSC 1.5 ±.1 RECOMMENDED SOLDER PAD LAYOUT * ( ).65 BSC (.47) MAX.9.2 (.35.79).5.75 (.2.3) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE.65 (.256) BSC ( ) TYP 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.15mm (.6") PER SIDE.5.15 (.2.6) FE2 (CB) TSSOP 24 23

24 PACKAGE DESCRIPTION UFD Package 2-Lead Pastic QFN (4mm 5mm) (Reference LTC DWG # Rev B).7 ± ± ± ± ±.5 PACKAGE OUTLINE.25 ±.5.5 BSC ± ±.5 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4. ±.1 (2 SIDES).75 ±.5 R =.5 TYP PIN 1 NOTCH R =.2 OR C =.35 PIN 1 TOP MARK (NOTE 6).4 ± ±.1 (2 SIDES) ± ±.1 (UFD2) QFN 56 REV B.2..5 R = ±.5 TYP.5 BSC BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-22 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A ERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 24

25 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 11/1 Added C-grade to data sheet 3 to 6, 9 Updated Eectrica Characteristics tabe for H-grade 7 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 25

26 TYPICAL APPLICATION Digitay Controed Output Votage 1.1A Suppy MID-SCALE ZERO-SCALE V CC 4 2 JP2 3 1 V CC C1.1µF TO MICROCONTROLLER C1.1µF CS SCK SDO SDI C1.1µF COMP IN/OUT LDAC PORSEL V CC CLR LTC2656* GND LO GND R4 7.5k A B C D E F G H V IN 1.2V TO 36V IN V CONTROL 1µF SET LT38 + OUT 2.2µF *PIN NUMBERS INDICATED ARE FOR THE QFN PACKAGE NOTE: LT38 MINIMUM LOAD CURRENT IS.5mA 2656 TA2 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC166/LTC1665 Octa 1-/8-Bit DACs in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, Micropower, Rai-to-Rai Output LTC1664 Quad 1-Bit DAC in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, Micropower, Rai-to-Rai Output LTC1821 Singe 16-Bit DAC with ±1LSB INL, DNL Parae Interface, Precision 16-Bit Setting in 2μs for 1V Step LTC26/LTC261/ LTC262 LTC261/LTC2611/ LTC2621 LTC262/LTC2612/ LTC2622 LTC264/LTC2614/ LTC2624 LTC265/LTC2615/ LTC2625 LTC266/LTC2616/ LTC2626 LTC269/LTC2619/ LTC2629 Octa 16-/14-/12-Bit DACs in 16-Lead Narrow SSOP Singe 16-/14-/12-Bit DACs in 1-Lead DFN Dua 16-/14-/12-Bit DACs in 8-Lead MSOP Quad 16-/14-/12-Bit DACs in 16-Lead SSOP Octa 16-/14-/12-Bit DACs with I 2 C Interface Singe 16-/14-/12-Bit DACs with I 2 C Interface Quad 16-/14-/12-Bit DACs with I 2 C Interface 25μA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 3μA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 3μA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 25μA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 25μA per DAC, 2.7V to 5.5V Suppy Range, Rai-to-Rai Output 27μA per DAC, 2.7V to 5.5V Suppy Range, Rai-to-Rai Output 25μA per DAC, 2.7V to 5.5V Suppy Range, Rai-to-Rai Output with Separate V Pins for Each DAC LTC2636 Octa 12-/1-/8-Bit DACs with 1ppm/ C Reference 125μA per DAC, 2.7V to 5.5V Suppy Range, Interna 1.25V or 2.48V Reference, Rai-to-Rai Output, SPI Interface LTC2641/LTC2642 Singe 16-/14-/12-Bit DACs with ±1LSB INL, DNL ±1LSB (Max) INL, DNL, 3mm 3mm DFN and MSOP Packages, 12μA Suppy Current, SPI Interface LTC274 LTC2755 Quad 16-/14-/12-Bit DACs with ±2LSB INL, ±1LSB DNL Quad 16-/14-/12-Bit I OUT DACs with ±1LSB INL, ±1LSB DNL Software Programmabe Output Ranges Up to ±1V, SPI Interface Software Programmabe Output Ranges Up to ±1V, Parae Interface 26 LT 111 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 29