LTC2607/LTC2617/LTC /14-/12-Bit Dual Rail-to-Rail DACs with I 2 C Interface. Applications. Block Diagram

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1 Features n Smaest Pin-Compatibe Dua DACs: LTC267: 16 Bits LTC2617: 14 Bits LTC2627: 12 Bits n Guaranteed Monotonic Over Temperature n 27 Seectabe Addresses n 4kHz I 2 C Interface n Wide 2.7V to 5.5V Suppy Range n Low Power Operation: 26µA per DAC at 3V n Power Down to 1µA, Max n High Rai-to-Rai Output Drive (±15mA, Min) n Utraow Crosstak (3µV) n Doube-Buffered Data Latches n Asynchronous DAC Update Pin n LTC267/LTC2617/LTC2627: Power-On Reset to Zero Scae n LTC267-1/LTC2617-1/LTC2627-1: Power-On Reset to Mid-Scae n Tiny (3mm 4mm) 12-Lead DFN Package Appications n Mobie Communications n Process Contro and Industria Automation n Instrumentation n Automatic Test Equipment LTC267/LTC2617/LTC /14-/12-Bit Dua Rai-to-Rai DACs with I 2 C Interface Description The LTC 267/LTC2617/LTC2627 are dua 16-, 14- and 12-bit, 2.7V to 5.5V rai-to-rai votage output DACs in a 12-ead DFN package. They have buit-in high performance output buffers and are guaranteed monotonic. These parts estabish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive and oad reguation in singe-suppy, votage-output DACs. The parts use a 2-wire, I 2 C compatibe seria interface. The LTC267/LTC2617/LTC2627 operate in both the standard mode (cock rate of 1kHz) and the fast mode (cock rate of 4kHz). An asynchronous DAC update pin (LDAC) is aso incuded. The LTC267/LTC2617/LTC2627 incorporate a power-on reset circuit. During power-up, the votage outputs rise ess than 1mV above zero scae; and after power-up, they stay at zero scae unti a vaid write and update take pace. The power-on reset circuit resets the LTC267-1/LTC2617-1/ LTC to mid-scae. The votage outputs stay at midscae unti a vaid write and update takes pace. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents incuding and Patent Pending. Bock Diagram REFLO GND REF V CC /14-/16-BIT DAC V OUTA DAC REGISTER INPUT REGISTER 32-BIT SHIFT REGISTER 2-WIRE INTERFACE DAC REGISTER INPUT REGISTER 12-/14-/16-BIT DAC CA CA1 LDAC SCL SDA CA V OUTB 267 BD1a DNL (LSB) Differentia Noninearity (LTC267) 1..8 V REF = 4.96V CODE 267 BD1b fa

2 LTC267/LTC2617/LTC2627 Absoute Maximum Ratings (Note 1) Any Pin to GND....3V to 6V Any Pin to V CC... 6V to.3v Maximum Junction Temperature C Storage Temperature Range C to 125 C Lead Temperature (Sodering, 1 sec)...3 C Operating Temperature Range: LTC267C/LTC2617C/LTC2627C LTC267C-1/LTC2617C-1/LTC2627C-1... C to 7 C LTC267I/LTC2617I/LTC2627I LTC267I-1/LTC2617I-1/LTC2627I C to 85 C Pin Configuration TOP VIEW CA 1 12 V OUTA CA REFLO LDAC GND SCL 4 9 REF SDA 5 8 V CC CA2 6 7 V OUTB DE12 PACKAGE 12-LEAD (4mm 3mm) PLASTIC DFN T JMAX = 125 C, θ JA = 43 C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC267CDE#PBF LTC267CDE#TRPBF Lead (4mm 3mm) Pastic DFN C to 7 C LTC267IDE#PBF LTC267IDE#TRPBF Lead (4mm 3mm) Pastic DFN 4 C to 85 C LTC267CDE-1#PBF LTC267CDE-1#TRPBF Lead (4mm 3mm) Pastic DFN C to 7 C LTC267IDE-1#PBF LTC267IDE-1#TRPBF Lead (4mm 3mm) Pastic DFN 4 C to 85 C LTC2617CDE#PBF LTC2617CDE#TRPBF Lead (4mm 3mm) Pastic DFN C to 7 C LTC2617IDE#PBF LTC2617IDE#TRPBF Lead (4mm 3mm) Pastic DFN 4 C to 85 C LTC2617CDE-1#PBF LTC2617CDE-1#TRPBF Lead (4mm 3mm) Pastic DFN C to 7 C LTC2617IDE-1#PBF LTC2617IDE-1#TRPBF Lead (4mm 3mm) Pastic DFN 4 C to 85 C LTC2627CDE#PBF LTC2627CDE#TRPBF Lead (4mm 3mm) Pastic DFN C to 7 C LTC2627IDE#PBF LTC2627IDE#TRPBF Lead (4mm 3mm) Pastic DFN 4 C to 85 C LTC2627CDE-1#PBF LTC2627CDE-1#TRPBF Lead (4mm 3mm) Pastic DFN C to 7 C LTC2627IDE-1#PBF LTC2627IDE-1#TRPBF Lead (4mm 3mm) Pastic DFN 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: fa

3 LTC267/LTC2617/LTC2627 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. REF = 4.96V (), REF = 2.48V (V CC = 2.7V), REFLO = V, V OUT unoaded, uness otherwise noted. SYMBOL PARAMETER DC Performance CONDITIONS LTC2627/LTC LTC2617/LTC LTC267/LTC267-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX Resoution Bits Monotonicity (Note 2) Bits DNL Differentia Noninearity (Note 2) ±.5 ±1 ±1 LSB INL Integra Noninearity (Note 2) ±1.5 ±4 ±5 ±16 ±19 ±64 LSB Load Reguation V REF =, Mid-Scae I OUT = ma to 15mA Sourcing I OUT = ma to 15mA Sinking V REF = V CC = 2.7V, Mid-Scae I OUT = ma to 7.5mA Sourcing I OUT = ma to 7.5mA Sinking UNITS LSB/mA LSB/mA LSB/mA LSB/mA ZSE Zero-Scae Error Code = mv V OS Offset Error (Note 6) ±1 ±9 ±1 ±9 ±1 ±9 mv V OS Temperature ±7 ±7 ±7 µv/ C Coefficient GE Gain Error ±.15 ±.7 ±.15 ±.7 ±.15 ±.7 %FSR Gain Temperature Coefficient ±4 ±4 ±4 ppm/ C The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. REF = 4.96V (), REF = 2.48V (V CC = 2.7V), REFLO = V, V OUT unoaded, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSR Power Suppy Rejection V CC ±1% 8 db R OUT DC Output Impedance V REF =, Mid-Scae; 15mA I OUT 15mA V REF = V CC = 2.7V, Mid-Scae; 7.5mA I OUT 7.5mA Ω Ω DC Crosstak (Note 4) Due to Fu Scae Output Change (Note 5) Due to Load Current Change Due to Powering Down (Per Channe) I SC Short-Circuit Output Current V CC = 5.5V, V REF = 5.5V Code: Zero Scae; Forcing Output to V CC Code: Fu Scae; Forcing Output to GND V CC = 2.7V, V REF = 2.7V Code: Zero Scae; Forcing Output to V CC Code: Fu Scae; Forcing Output to GND Reference Input ±4 ±3 ± µv µv/ma µv Input Votage Range V CC V Resistance Norma Mode kω Capacitance 3 pf I REF Reference Current, Power Down Mode DAC Powered Down.1 1 µa ma ma ma ma fa

4 LTC267/LTC2617/LTC2627 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. REF = 4.96V (), REF = 2.48V (V CC = 2.7V), REFLO = V, V OUT unoaded, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Suppy V CC Positive Suppy Votage For Specified Performance V I CC Suppy Current (Note 3) V CC = 3V (Note 3) DAC Powered Down (Note 3) DAC Powered Down (Note 3) V CC = 3V Digita I/O (Note 11) V IL Low Leve Input Votage (SDA and SCL).3V CC V V IH High Leve Input Votage (SDA and SCL).7V CC V V IL(LDAC) Low Leve Input Votage (LDAC) V CC = 4.5V to 5.5V V CC = 2.7V to 5.5V V IH(LDAC) High Leve Input Votage (LDAC) V CC = 2.7V to 5.5V V CC = 2.7V to 3.6V V IL(CAn) Low Leve Input Votage on CAn (n =, 1, 2) See Test Circuit 1.15V CC V 1 V IH(CAn) High Leve Input Votage on CAn (n =, 1, 2) See Test Circuit 1.85V CC V R INH Resistance from CAn (n =, 1, 2) See Test Circuit 2 kω to V CC to Set CAn = V CC R INL Resistance from CAn (n =, 1, 2) to GND to Set CAn = GND See Test Circuit 2 1 kω R INF Resistance from CAn (n =, 1, 2) See Test Circuit 2 2 MΩ to V CC or GND to Set CAn = Foat V OL Low Leve Output Votage Sink Current = 3mA.4 V t OF Output Fa Time V O = V IH(MIN) to V O = V IL(MAX), 2 +.1C B 25 ns C B = 1pF to 4pF (Note 9) t SP Puse Width of Spikes Suppressed by Input Fiter 5 ns I IN Input Leakage.1V CC V IN.9V CC 1 µa C IN I/O Pin Capacitance Note 12 1 pf C B Capacitive Load for Each Bus Line 4 pf C CAX Externa Capacitive Load on Address Pins CAn (n =, 1, 2) 1 pf ma ma µa µa V V V V fa

5 Eectrica Characteristics Timing Characteristics Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: Linearity and monotonicity are defined from code k L to code 2N 1, where N is the resoution and k L is given by k L =.16(2 N /V REF ), rounded to the nearest whoe code. For V REF = 4.96V and N = 16, k L = 256 and inearity is defined from code 256 to code 65,535. Note 3: SDA, SCL and LDAC at V or V CC, CA, CA1 and CA2 Foating. Note 4: DC crosstak is measured with and V REF = 4.96V, with the measured DAC at mid-scae, uness otherwise noted. LTC267/LTC2617/LTC2627 The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. REF = 4.96V (), REF = 2.48V (V CC = 2.7V), REFLO = V, V OUT unoaded, uness otherwise noted. LTC2627/LTC LTC2617/LTC LTC267/LTC267-1 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS AC Performance t S Setting Time (Note 7) ±.24% (±1LSB at 12 Bits) ±.6% (±1LSB at 14 Bits) ±.15% (±1LSB at 16 Bits) Setting Time for 1LSB Step (Note 8) ±.24% (±1LSB at 12 Bits) ±.6% (±1LSB at 14 Bits) ±.15% (±1LSB at 16 Bits) Votage Output Sew Rate V/µs Capacitive Load Driving pf Gitch Impuse At Mid-Scae Transition nv s Mutipying Bandwidth khz e n Output Votage Noise Density At f = 1kHz At f = 1kHz The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. (See Figure 1) (Notes 1, 11) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC = 2.7V to 5.5V f SCL SCL Cock Frequency 4 khz t HD(STA) Hod Time (Repeated) Start Condition.6 µs t LOW Low Period of the SCL Cock Pin 1.3 µs t HIGH High Period of the SCL Cock Pin.6 µs t SU(STA) Set-Up Time for a Repeated Start Condition.6 µs t HD(DAT) Data Hod Time.9 µs t SU(DAT) Data Set-Up Time 1 ns t r Rise Time of Both SDA and SCL Signas (Note 9) 2 +.1C B 3 ns t f Fa Time of Both SDA and SCL Signas (Note 9) 2 +.1C B 3 ns t SU(STO) Set-Up Time for Stop Condition.6 µs t BUF Bus Free Time Between a Stop and Start Condition 1.3 µs t 1 Faing Edge of 9th Cock of the 3rd Input Byte to 4 ns LDAC High or Low Transition t 2 LDAC Low Puse Width 2 ns µs µs µs µs µs µs nv/ Hz nv/ Hz Output Votage Noise.1Hz to 1Hz µv P-P Note 5: R L = 2kΩ to GND or V CC. Note 6: Inferred from measurement at code k L (Note 2) and at fu scae. Note 7:, V REF = 4.96V. DAC is stepped 1/4 scae to 3/4 scae and 3/4 scae to 1/4 scae. Load is 2k in parae with 2pF to GND. Note 8:, V REF = 4.96V. DAC is stepped ±1LSB between haf scae and haf scae 1. Load is 2k in parae with 2pF to GND. Note 9: C B = capacitance of one bus ine in pf. Note 1: A vaues refer to V IH(MIN) and V IL(MAX) eves. Note 11: These specifications appy to LTC267/LTC267-1, LTC2617/LTC2617-1, LTC2627/LTC Note 12: Guaranteed by design and not production tested fa

6 LTC267/LTC2617/LTC2627 Typica Performance Characteristics LTC267 INL (LSB) Integra Noninearity (INL) Differentia Noninearity (DNL) INL vs Temperature V REF = 4.96V CODE 267 G1 DNL (LSB) V REF = 4.96V CODE 267 G2 INL (LSB) V REF = 4.96V INL (POS) INL (NEG) TEMPERATURE ( C) 267 G3 DNL (LSB) DNL vs Temperature INL vs V REF DNL vs V REF V REF = 4.96V DNL (POS) DNL (NEG) TEMPERATURE ( C) 267 G4 INL (LSB) V CC = 5.5V INL (POS) INL (NEG) V REF (V) 267 G5 DNL (LSB) V CC = 5.5V DNL (POS) DNL (NEG) V REF (V) 267 G6 Setting to ±1LSB Setting of Fu-Scae Step V OUT 1µV/DIV SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE 9.7µs V OUT 1µV/DIV SCL 2V/DIV 12.3µs 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV, V REF = 4.96V 1/4-SCALE TO 3/4-SCALE STEP R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 267 G7 5µs/DIV SETTLING TO ±1LSB, V REF = 4.96V CODE 512 TO STEP AVERAGE OF 248 EVENTS 267 G fa

7 Typica Performance Characteristics LTC2617 LTC267/LTC2617/LTC2627 INL (LSB) LTC2627 Integra Noninearity (INL) Differentia Noninearity (DNL) Setting to ±1LSB V REF = 4.96V CODE 267 G9 DNL (LSB) V REF = 4.96V CODE 267 G1 V OUT 1µV/DIV SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV, V REF = 4.96V 1/4-SCALE TO 3/4-SCALE STEP R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 8.9µs 267 G11 INL (LSB) Integra Noninearity (INL) Differentia Noninearity (DNL) Setting to ±1LSB V REF = 4.96V CODE 267 G12 DNL (LSB) V REF = 4.96V CODE 267 G13 V OUT 1mV/DIV SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV 6.8µs, V REF = 4.96V 1/4-SCALE TO 3/4-SCALE STEP R L = 2k, C L = 2pF AVERAGE OF 248 EVENTS 267 G fa

8 LTC267/LTC2617/LTC2627 Typica Performance Characteristics LTC267/LTC2617/LTC2627 V OUT (V) Current Limiting Load Reguation Offset Error vs Temperature CODE = MID-SCALE V REF = V REF = V CC = 3V V REF = V CC = 3V V REF = V OUT (mv) 1. CODE = MID-SCALE V REF =.2.4 V REF = V CC = 3V I OUT (ma) I OUT (ma) TEMPERATURE ( C) 267 G G G17 OFFSET ERROR (mv) 3 Zero-Scae Error vs Temperature Gain Error vs Temperature Offset Error vs V CC.4 3 ZERO-SCALE ERROR (mv) GAIN ERROR (%FSR) OFFSET ERROR (mv) TEMPERATURE ( C) 267 G TEMPERATURE ( C) 267 G V CC (V) 267 G2.4.3 Gain Error vs V CC 45 4 I CC Shutdown vs V CC GAIN ERROR (%FSR) V CC (V) 267 G21 I CC (na) V CC (V) 267 G fa

9 Typica Performance Characteristics LTC267/LTC2617/LTC2627 LTC267/LTC2617/LTC2627 Large-Signa Response Mid-Scae Gitch Impuse Power-On Reset to Zeroscae TRANSITION FROM MS-1 TO MS V OUT.5V/DIV V REF = 1/4-SCALE TO 3/4-SCALE V OUT 1mV/DIV SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE TRANSITION FROM MS TO MS-1 V CC 1V/DIV V OUT 1mV/DIV 4mV PEAK 2.5µs/DIV 267 G23 2.5µs/DIV 267 G24 25µs/DIV 267 G25 V OUT (V) Headroom at Rais vs Output Current 5V SOURCING 3V SOURCING 3V SINKING 5V SINKING Power-On Reset to Midscae V REF = V CC 1V/DIV V CC V OUT I CC (µa) Suppy Current vs Logic Votage SWEEP LDAC OV TO V CC I OUT (ma) 267 G26 5µs/DIV 267 G LOGIC VOLTAGE (V) 267 G28 I CC (µa) Suppy Current vs Logic Votage HYSTERSIS 37mV SWEEP SCL AND SDA OV TO V CC AND V CC TO OV LOGIC VOLTAGE (V) 267 G29 db k Mutipying Bandwidth V REF (DC) = 2V V REF (AC) =.2V P-P CODE = FULL SCALE 1k 1k FREQUENCY (Hz) 1M 267 G3 V OUT 1µV/DIV Output Votage Noise,.1Hz to 1Hz SECONDS 267 G fa

10 LTC267/LTC2617/LTC2627 Typica Performance Characteristics LTC267/LTC2617/LTC Short-Circuit Output Current vs V OUT (Sinking) V CC = 5.5V V REF = 5.6V CODE = V OUT SWEPT V TO V CC 1 Short-Circuit Output Current vs V OUT (Sourcing) V CC = 5.5V V REF = 5.6V CODE = FULL SCALE V OUT SWEPT V CC TO V 1mA/DIV 3 2 1mA/DIV V/DIV G V/DIV G33 Pin Functions CA (Pin 1): Chip Address Bit. Tie this pin to V CC, GND or eave it foating to seect an I 2 C save address for the part (Tabe 1). CA1 (Pin 2): Chip Address Bit 1. Tie this pin to V CC, GND or eave it foating to seect an I 2 C save address for the part (Tabe 1). LDAC (Pin 3): Asynchronous DAC Update. A faing edge of this input after four bytes have been written into the part immediatey updates the DAC register with the contents of the input register. A ow on this input without a compete 32-bit (four bytes incuding the save address) data write transfer to the part wakes up seeping DACs without updating the DAC output. Software power-down is disabed when LDAC is ow. LDAC is disabed when tied high. SCL (Pin 4): Seria Cock Input Pin. Data is shifted into the SDA pin at the rising edges of the cock. This high impedance pin requires a pu-up resistor or current source to V CC. SDA (Pin 5): Seria Data Bidirectiona Pin. Data is shifted into the SDA pin and acknowedged by the SDA pin. This pin is high impedance whie data is shifted in and an opendrain N-channe output during acknowedgment. Requires a pu-up resistor or current source to V CC. 1 CA2 (Pin 6): Chip Address Bit 2. Tie this pin to V CC, GND or eave it foating to seect an I 2 C save address for the part (Tabe 1). V OUTB (Pin 7): DAC Anaog Votage Output. The output range is V REFLO to V REF. V CC (Pin 8): Suppy Votage Input. 2.7V V CC 5.5V. REF (Pin 9): Reference Votage Input. The input range is V REFLO V REF V CC. GND (Pin 1): Anaog Ground. REFLO (Pin 11): Reference Low. The votage at this pin sets the zero scae (ZS) votage of a DACs. The V REFLO pin can be used at votages up to 1V for, or 1mV for V CC = 3V. V OUTA (Pin 12): DAC Anaog Votage Output. The output range is V REFLO to V REF. Exposed Pad (Pin 13): Ground. Must be sodered to PCB ground fa

11 Bock Diagram LTC267/LTC2617/LTC REFLO GND REF V CC /14-/16-BIT DAC V OUTA 12-/14-/16-BIT DAC 7 V OUTB DAC REGISTER DAC REGISTER INPUT REGISTER INPUT REGISTER 32-BIT SHIFT REGISTER 2-WIRE INTERFACE CA CA1 LDAC SCL SDA CA BD Test Circuits Test Circuit 1 Test Circuit 2 V DD 1Ω CAn R INH /R INL /R INF CAn V IH(CAn) /V IL(CAn) GND 267 TC fa 11

12 LTC267/LTC2617/LTC2627 Timing Diagrams SDA t f tlow tr tsu(dat) t f thd(sta) tsp tr tbuf SCL t HD(STA) tsu(sta) tsu(sto) S t HD(DAT) thigh S P S 267 F1 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS Figure 1 START SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE SDA SA6 SA5 SA4 SA3 SA2 SA1 SA ACK C3 C2 C1 C A3 A2 A1 A ACK ACK ACK Figure 2a Figure 2b 267 F2A SCL LDAC 9TH CLOCK OF 3RD DATA BYTE SCL t 1 LDAC 267 F2b t1 t fa

13 Operation Power-On Reset The LTC267/LTC2617/LTC2627 cear the outputs to zero scae when power is first appied, making system initiaization consistent and repeatabe. The LTC267-1/ LTC2617 1/LTC set the votage outputs to midscae when power is first appied. For some appications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC267/ LTC2617/LTC2627 contain circuitry to reduce the poweron gitch; furthermore, the gitch ampitude can be made arbitrariy sma by reducing the ramp rate of the power suppy. For exampe, if the power suppy is ramped to 5V in 1ms, the anaog outputs rise ess than 1mV above ground (typ) during power-on. See Power-On Reset Gitch in the Typica Performance Characteristics section. Power Suppy Sequencing The votage at REF (Pin 9) shoud be kept within the range.3v V REF V CC +.3V (see Absoute Maximum Ratings). Particuar care shoud be taken to observe these imits during power suppy turn-on and turn-off sequences, when the votage at V CC (Pin 8) is in transition. Transfer Function The digita-to-anaog transfer function is: V k ( ) = 2 ( ) + V V V OUT IDEAL N REF REFLO REFLO where k is the decima equivaent of the binary DAC input code, N is the resoution and V REF is the votage at REF (Pin 6). Seria Digita Interface The LTC267/LTC2617/LTC2627 communicate with a host using the standard 2-wire I 2 C interface. The Timing Diagrams (Figures 1 and 2) show the timing reationship of the signas on the bus. The two bus ines, SDA and SCL, must be high when the bus is not in use. Externa pu-up resistors or current sources are required on these ines. The vaue of these pu-up resistors is dependent on the power suppy and can be obtained from the I 2 C LTC267/LTC2617/LTC2627 specifications. For an I 2 C bus operating in the fast mode, an active pu-up wi be necessary if the bus capacitance is greater than 2pF. The V CC power shoud not be removed from the LTC267/LTC2617/LTC2627 when the I 2 C bus is active to avoid oading the I 2 C bus ines through the interna ESD protection diodes. The LTC267/LTC2617/LTC2627 are receive-ony (save) devices. The master can write to the LTC267/LTC2617/ LTC2627. The LTC267/LTC2617/LTC2627 do not respond to a read from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signas the beginning of a communication to a save device by transmitting a START condition. A START condition is generated by transitioning SDA from high to ow whie SCL is high. When the master has finished communicating with the save, it issues a STOP condition. A STOP condition is generated by transitioning SDA from ow to high whie SCL is high. The bus is then free for communication with another I 2 C device. Acknowedge The Acknowedge signa is used for handshaking between the master and the save. An Acknowedge (active LOW) generated by the save ets the master know that the atest byte of information was received. The Acknowedge reated cock puse is generated by the master. The master reeases the SDA ine (HIGH) during the Acknowedge cock puse. The save-receiver must pu down the SDA bus ine during the Acknowedge cock puse so that it remains a stabe LOW during the HIGH period of this cock puse. The LTC267/LTC2617/LTC2627 respond to a write by a master in this manner. The LTC267/LTC2617/LTC2627 do not acknowedge a read (retains SDA HIGH during the period of the Acknowedge cock puse). Chip Address The state of CA, CA1 and CA2 decides the save address of the part. The pins CA, CA1 and CA2 can be each set to any one of three states: V CC, GND or foat. This resuts fa 13

14 LTC267/LTC2617/LTC2627 Operation in 27 seectabe addresses for the part. The save address assignments are shown in Tabe 1. Tabe 1. Save Address Map CA2 CA1 CA SA6 SA5 SA4 SA3 SA2 SA1 SA GND GND GND 1 GND GND FLOAT 1 1 GND GND V CC 1 1 GND FLOAT GND GND FLOAT FLOAT 1 GND FLOAT V CC 1 1 GND V CC GND 1 1 GND V CC FLOAT GND V CC V CC 1 1 FLOAT GND GND FLOAT GND FLOAT FLOAT GND V CC FLOAT FLOAT GND 1 FLOAT FLOAT FLOAT 1 1 FLOAT FLOAT V CC 1 1 FLOAT V CC GND FLOAT V CC FLOAT 1 1 FLOAT V CC V CC V CC GND GND V CC GND FLOAT V CC GND V CC 1 1 V CC FLOAT GND V CC FLOAT FLOAT V CC FLOAT V CC V CC V CC GND V CC V CC FLOAT V CC V CC V CC GLOBAL ADDRESS In addition to the address seected by the address pins, the parts aso respond to a goba address. This address aows a common write to a LTC267, LTC2617 and LTC2627 parts to be accompished with one 3-byte write transaction on the I 2 C bus. The goba address is a 7-bit on-chip hardwired address and is not seectabe by CA, CA1 and CA2. 14 The addresses corresponding to the states of CA, CA1 and CA2 and the goba address are shown in Tabe 1. The maximum capacitive oad aowed on the address pins (CA, CA1 and CA2) is 1pF, as these pins are driven during address detection to determine if they are foating. Write Word Protoco The master initiates communication with the LTC267/ LTC2617/LTC2627 with a START condition and a 7-bit save address foowed by the Write bit (W) =. The LTC267/ LTC2617/LTC2627 acknowedges by puing the SDA pin ow at the 9th cock if the 7-bit save address matches the address of the parts (set by CA, CA1 and CA2) or the goba address. The master then transmits three bytes of data. The LTC267/LTC2617/LTC2627 acknowedges each byte of data by puing the SDA ine ow at the 9th cock of each data byte transmission. After receiving three compete bytes of data, the LTC267/LTC2617/LTC2627 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a vaid 7-bit save address, the LTC267/LTC2617/LTC2627 do not acknowedge the extra bytes of data (SDA is high during the 9th cock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command word C3-C, and 4-bit DAC address A3-A. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16-, 14- or 12-bit input code, MSB to LSB, foowed by, 2 or 4 don t care bits (LTC267, LTC2617 and LTC2627 respectivey). A typica LTC267 write transaction is shown in Figure 4. The command (C3-C) and address (A3-A) assignments are shown in Tabe 2. The first four commands in the tabe consist of write and update operations. A write operation oads a 16-bit data word from the 32-bit shift register into the input register of the seected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an anaog votage at the DAC output. The update operation aso powers up the seected DAC if it had been in power-down mode. The data path and registers are shown in the Bock Diagram fa

15 LTC267/LTC2617/LTC2627 Operation Write Word Protoco for LTC267/LTC2617/LTC1627 S SLAVE ADDRESS W A Input Word (LTC267) 1ST DATA BYTE A 2ND DATA BYTE A 3RD DATA BYTE A P INPUT WORD C3 C2 C1 C A3 A2 A1 A D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D 1ST DATA BYTE Input Word (LTC2617) C3 2ND DATA BYTE 3RD DATA BYTE C2 C1 C A3 A2 A1 A D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X 1ST DATA BYTE Input Word (LTC2627) C3 2ND DATA BYTE 3RD DATA BYTE C2 C1 C A3 A2 A1 A D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE 267 F3 Figure 3 Tabe 2 COMMAND* C3 C2 C1 C Write to Input Register 1 Update (Power Up) DAC Register 1 1 Write to and Update (Power Up) 1 Power Down No Operation ADDRESS* A3 A2 A1 A DAC A 1 DAC B A DACs *Command and address codes not shown are reserved and shoud not be used. Power-Down Mode For power-constrained appications, the power-down mode can be used to reduce the suppy current whenever one or both of the DAC outputs are not needed. When in powerdown, the buffer ampifiers, bias circuits and reference input are disabed and draw essentiay zero current. The DAC outputs are put into a high impedance state, and the output pins are passivey pued to V REFLO through 9k resistors. Input-register and DAC-register contents are not disturbed during power-down. Either or both DAC channes can be put into power-down mode by using command 1b in combination with the appropriate DAC address. The 16-bit data word is ignored. The suppy and reference currents are reduced by approximatey 5% for each DAC powered down; the effective resistance at REF (Pin 9) rises accordingy, becoming a high-impedance input (typicay > 1GΩ) when both DACs are powered down. Norma operation can be resumed by executing any command which incudes a DAC update, as shown in Tabe 2 or performing an asychronous update (LDAC) as described in the next section. The seected DAC is powered up as its votage output is updated. When a DAC in powereddown state is powered up and updated, norma setting is deayed. If one of the two DACs is in a powered- down state prior to the update command, the power up deay is 5µs. If on the other hand, both DACs are powered down, the main bias generation circuit has been automaticay shut down in addition to the DAC ampifiers and reference input and so the power up deay time is 12µs (for ) or 3µs (for V CC = 3V) Asynchronous DAC Update Using LDAC In addition to the update commands shown in Tabe 2, the LDAC pin asynchronousy updates the DAC registers with the contents of the input registers. Asynchronous update is disabed when the input word is being cocked into the part fa 15

16 LTC267/LTC2617/LTC2627 Operation If a compete input word has been written to the part, a ow on the LDAC pin causes the DAC registers to be updated with the contents of the input registers. If the input word is being written to the part, a ow going puse on the LDAC pin before the competion of three bytes of data powers up the DACs but does not cause the outputs to be updated. If LDAC remains ow after a compete input word has been written to the part, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC outputs updated. The DACs are powered up when LDAC is taken ow, independent of any activity on the I 2 C bus. If LDAC is ow at the faing edge of the 9th cock of the 3rd byte of data, it inhibits any software power-down command that was specified in the input word. LDAC is disabed when tied high. Votage Output Both of the two rai-to-rai ampifiers have guaranteed oad reguation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load reguation is a measure of the ampifiers abiity to maintain the rated votage accuracy over a wide range of oad conditions. The measured change in output votage per miiampere of forced oad current change is expressed in LSB/mA. DC output impedance is equivaent to oad reguation, and may be derived from it by simpy cacuating a change in units from LSB/mA to Ohms. The ampifiers DC output impedance is.35ω when driving a oad we away from the rais. When drawing a oad current from either rai, the output votage headroom with respect to that rai is imited by the 3Ω typica channe resistance of the output devices; e.g., when sinking 1mA, the minimum output votage = 3Ω 1mA = 3mV. See the graph Headroom at Rais vs Output Current in the Typica Performance Characteristics section. The ampifiers are stabe driving capacitive oads of up to 1pF. 16 Board Layout The exceent oad reguation performance is achieved in part by separating the signa and power grounds as REFLO and GND pins, respectivey. The PC Board shoud have separate areas for the anaog and digita sections of the circuit. This keeps the digita signas away from the sensitive anaog signas and faciitates the use of separate digita and anaog ground panes that have minima interaction with each other. Digita and anaog ground panes shoud be joined at ony one point, estabishing a system star ground. Ideay, the anaog ground pane shoud be ocated on the component side of the board, and shoud be aowed to run under the part to shied it from noise. Anaog ground shoud be a continuous and uninterrupted pane, except for necessary ead pads and vias, with signa traces on another ayer. The GND pin functions as a return path for power suppy currents in the device and shoud be connected to anaog ground. Resistance from the GND pin to the anaog power suppy return shoud be as ow as possibe. Resistance here wi add directy to the channe resistance of the output device when sinking oad current. When a zero scae DAC output votage of zero is required, the REFLO pin shoud be connected to system star ground. Any shared trace resistance between REFLO and GND pins is undesirabe since it adds to the effective DC output impedance (typicay.35ω) of the part. Rai-to-Rai Output Considerations In any rai-to-rai votage output device, the output is imited to votages within the suppy range. Since the anaog output of the device cannot go beow ground, it may imit for the owest codes as shown in Figure 5b. Simiary, imiting can occur near fu scae when the REF pin is tied to V CC. If V REF = V CC and the DAC fu-scae error (FSE) is positive, the output for the highest codes imits at V CC as shown in Figure 5c. No fu-scae imiting wi occur if V REF is ess than V CC FSE. Offset and inearity are defined and tested over the region of the DAC transfer function where no output imiting can occur fa

17 Operation LTC267/LTC2617/LTC2627 SLAVE ADDRESS COMMAND MS DATA LS DATA SA6 SA5 SA4 SA3 SA2 SA1 SA WR C3 C2 C1 C A3 A2 A1 A D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D START SDA SA6 SA5 SA4 SA3 SA2 SA1 SA ACK C3 C2 C1 C A3 A2 A1 A ACK ACK ACK SCL V OUT X = DON T CARE Figure 4. Typica LTC267 Input Waveform Programming DAC Output for Fu Scae V REF = V CC POSITIVE FSE VREF = V CC OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) 267 F5 NEGATIVE OFFSET V INPUT CODE (b) 32, , 535 INPUT CODE (a) Figure 5. Effects of Rai-to-Rai Operation on a DAC Transfer Curve. (a) Overa Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scae (c) Effect of Positive Fu-Scae Error for Codes Near Fu Scae STOP FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 267 F fa 17

18 LTC267/LTC2617/LTC2627 Package Description DE/UE Package 12-Lead Pastic DFN (4mm 3mm) (Reference LTC DWG # Rev D) PACKAGE OUTLINE BSC 2.5 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4..1 (2 SIDES) R =.5 TYP 7 R =.115 TYP PIN 1 TOP MARK (NOTE 6).2 REF 3..1 (2 SIDES) BSC 2.5 REF BOTTOM VIEW EXPOSED PAD PIN 1 NOTCH R =.2 OR CHAMFER (UE12/DE12) DFN 86 REV D NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE fa

19 LTC267/LTC2617/LTC2627 Revision History REV DATE DESCRIPTION PAGE NUMBER A 1/1 Revised Features Added Pin Configuration and Updated Order Information Added Text to Seria Digita Interface Section Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights fa 19

20 LTC267/LTC2617/LTC2627 Typica Appication Demo Circuit Schematic. Onboard 2-Bit ADC Measures Key Performance Parameters 5V 5V V REF 1V TO 5V.1µF I 2 C BUS LDAC CA CA1 CA2 SCL SDA V CC REF FS SET V CC V OUTB 7 1Ω 7.5k 3 CH 1 LTC267 GND REFLO 1, 13 V OUTA DAC OUTPUT B 12 1Ω 7.5k 4 DAC OUTPUT A CH LTC2422 ZS SET GND 5 6 SCK SDO CS F O SPI BUS 267 TA1 Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC1458/LTC1458L Quad 12-Bit Rai-to-Rai Output DACs with Added Functionaity LTC1458: V CC = 4.5V to 5.5V, V OUT = V to 4.96V LTC1458L: V CC = 2.7V to 5.5V, V OUT = V to 2.5V LTC1654 Dua 14-Bit Rai-to-Rai V OUT DAC Programmabe Speed/Power, 3.5µs/75µA, 8µs/45µA LTC1655/LTC1655L Singe 16-Bit V OUT DACs with Seria Interface in SO-8 (3V), Low Power, Degitched LTC1657/LTC1657L Parae 5V/3V 16-Bit V OUT DACs Low Power, Degitched, Rai-to-Rai V OUT LTC166/LTC1665 Octa 1/8-Bit V OUT DACs in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, Micropower, Rai-to-Rai Output LTC1664 Quad 1-Bit V OUT DAC in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, Micropower, Rai-to-Rai Output LTC1821 Parae 16-Bit Votage Output DAC Precision 16-Bit Setting in 2µs for 1V Step LTC26/LTC261/ Octa 16-/14-/12-Bit V OUT DACs in 16-Lead SSOP 25µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai LTC262 Output, SPI Seria Interface LTC261/LTC2611/ LTC2621 LTC262/LTC2612/ LTC2622 LTC264/LTC2614/ LTC2624 LTC265/LTC2615/ LTC2625 LTC266/LTC2616/ LTC2626 LTC269/LTC2619/ LTC2629 Singe 16-/14-/12-Bit V OUT DACs in 1-Lead DFN Dua 16-/14-/12-Bit V OUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit V OUT DACs in 16-Lead SSOP Octa 16-/14-/12-Bit V OUT DACs with I 2 C Interface 16-/14-/12-Bit V OUT DACs with I 2 C Interface Quad 16-/14-/12-Bit V OUT DACs with I 2 C Interface 3µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 3µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 25µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface 25µA per DAC, 2.7V to 5.5V Suppy Range, Rai-to-Rai Output, I 2 C Interface 27µA per DAC, 2.7V to 5.5V Suppy Range, Rai-to-Rai Output, I 2 C Interface 25µA Range per DAC, 2.7V to 5.5V Suppy Range, Rai-to-Rai Output with Separate V REF Pins for Each DAC fa LT 11 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 25