LTC V Micropower Dual Voltage Monitor TYPICAL APPLICATION

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1 LTC966 1V Micropower Dua Votage Monitor FEATURES n Wide Operating Range: 3.5V to 1V n Wide Monitoring Range: 1.75V to 98V n Quiescent Current: 7µA n Adjustabe Threshod Range n Interna High Vaue Resistive Dividers n ±1.4% (Max) Threshod Accuracy Over Temperature n Poarity Seection n 1V Rated Outputs n Seectabe Buit-In Hysteresis n -Lead SW and 16-Lead 3mm 3mm QFN Packages APPLICATIONS n Portabe Equipment n Battery-Powered Equipment n Teecom Systems n Automotive/Industria Eectronics DESCRIPTION The LTC 966 is a ow current, high votage dua channe votage monitor. Interna high vaue resistors sense the input monitor pins providing a compact and ow power soution for votage monitoring. Each channe incudes two comparator reference inputs (INH/INL) to aow configuration of a high and ow threshod using an externa resistive divider biased from the on-chip reference. Range seection pins are provided for each channe to set the interna resistive dividers for 5x, 1x, x and 4x scaing. The threshods are scaed according to the range seection settings. Additionay, either INH or INL can be grounded to enabe buit-in hysteresis. Poarity seection pins aow each output to be inverted. The outputs are 1V capabe and incude a 5k pu-up resistor to an interna suppy. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION THRESHOLD CONFIGURATION k 91k 99k 48V 4V INHA INHB Dua Undervotage Monitor LTC966 V INB OUTA OUTB 1k 48V UNDERVOLTAGE 4V UNDERVOLTAGE 1k 5V 5V SYS RANGE V IN MONITOR RANGE SELECTION 1.75V* to 1.5V 5x 3.5V to 4.5V 1x 7V to 49V x 14V to 98V 4x *Requires either or V INB > 3.5V INLB PSA RS1A RSA PSB RS1B RSB 1 1 Suppy Current vs (B) 8 POLARITY AND RANGE SELECTION RISING THRESHOLD FALLING THRESHOLD HYSTERESIS RANGE CHANNEL A 4.3V 36.4V 3.6V x B.V 18.V 1.8V 1x 966 TA1a I VA(B) (µa) 6 4 RANGE = 4x OUTA(B) = LOW V INB(A) = I = µa (V) 45 C 5 C 9 C 15 C TA1b For more information 1

2 LTC966 ABSOLUTE MAXIMUM RATINGS Input Votages, V INB....3V to 14V PSA, PSB, RS1A, RS1B, RSA, RSB....3V to 6V INHA, INHB,, INLB....3V to 6V Output Votages OUTA, OUTB....3V to 14V Average Currents, V INB... ma OUTA, OUTB...±5mA...±5mA INHA, INHB,, INLB... 1mA PIN CONFIGURATION (Notes 1, ) Operating Ambient Temperature Range LTC966C... C to 7 C LTC966I... 4 C to 85 C LTC966H... 4 C to 15 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec)...3 C INHA RS1A TOP VIEW OUTA VINA V INB OUTB RSA PSA PSB RSB 1 11 INHB 1 INLB 9 RS1B UD PACKAGE 16-LEAD (3mm 3mm) PLASTIC QFN T JMAX = 15 C, θ JA = 68 C/W EXPOSED PAD (PIN 17) PCB CONNECTION OPTIONAL NC OUTA NC INHA RS1A RSA PSA TOP VIEW SW PACKAGE -LEAD PLASTIC SO T JMAX = 15 C, θ JA = 35 C/W V INB NC OUTB NC INHB INLB RS1B RSB PSB ORDER INFORMATION ( LEAD FREE FINISH TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC966CUD#PBF LTC966CUD#TRPBF LGMG 16-Lead (3mm 3mm) Pastic QFN C to 7 C LTC966IUD#PBF LTC966IUD#TRPBF LGMG 16-Lead (3mm 3mm) Pastic QFN 4 C to 85 C LTC966HUD#PBF LTC966HUD#TRPBF LGMG 16-Lead (3mm 3mm) Pastic QFN 4 C to 15 C LTC966CSW#PBF LTC966CSW#TRPBF LTC966SW -Lead Pastic Sma Outine (Wide.3 Inch) C to 7 C LTC966ISW#PBF LTC966ISW#TRPBF LTC966SW -Lead Pastic Sma Outine (Wide.3 Inch) 4 C to 85 C LTC966HSW#PBF LTC966HSW#TRPBF LTC966SW -Lead Pastic Sma Outine (Wide.3 Inch) 4 C to 15 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on nonstandard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: For more information

3 LTC966 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 5 C. = V INB = 1V, RS1/RS =, PS =, INH = 1.V, INL = (Notes 1, ). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Input Suppy Operating Range or V INB V V MON V IN Monitor Range (Note 3) V I VA Input Suppy Current = 1V, V INB =, 4x =, V INB = 1V, 4x I VB V INB Input Suppy Current V INB = 1V, =, 4x V INB =, = 1V, 4x V INB = 1V, = 5V, 4x ± ±5 4 V UVLO Undervotage Lockout or V INB Rising 3 V Undervotage Lockout Hysteresis and V INB Faing 7 Comparator Reference Input: INHA, INHB,, INLB V CM Comparator Common Mode Votage V V ERR V IN Error Votage at 96V INH = V, 4x.35V INH.4V, 4x V IN Error Votage at 48V INH = V, x.35v INH.4V, x V IN Error Votage at 4V INH = V, 1x.35V INH.4V, 1x V IN Error Votage at 1V INH = V, 5x.35V INH.4V, 5x V OS Comparator Offset Votage INH =.35V, 1x ±1.9 ±3 AV ERR Interna Resistive Divider Range Error INH =.4V, Range = 5x, 1x, x, 4x ±.4 % V HYS Comparator Buit-in Hysteresis INH =, INL Rising INL =, INH Faing V HYTH Buit-in Hysteresis Enabe Threshod t PD V IN to OUT Comparator Propagation Deay Overdrive = 1%, OUT Faing, 1x INH =, INL = 1.V 4 8 µs I IN(LKG) Input Leakage Current (INH, INL) V = 1.V, I-Grade V = 1.V, H-Grade Reference: V Reference Output Votage I 1µA, V IN 3.5V V Noise Reference Output Noise 1Hz to 1kHz 14 µv RMS Contro Inputs: RS1A, RSA, RS1B, RSB, PSA, PSB V TH Seect Input Threshod V I LKG Input Leakage Current V =.4V ±1 na Status Outputs: OUTA, OUTB V OL Votage Output Low V IN = 1.5V, I = 1µA V IN = 3.5V, I = 5µA V OH Votage Output High V IN = 3.5V, I = 1µA V IN 4.5V, I = 1µA I OH Output Current High V =, V IN = 3.5V µa I O(LKG) Leakage Current, Output High V = 1V, V IN = 6V ±5 na ±5 ±5 ±1 ±1 ±35 ±35 ±15 ±15 ±.1 ± ±136 ±4 ±63 ±15 ±315 ±75 ±155 ± ±1 ± µa na µa na µa na na V V Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note : A currents into pins are positive; a votages are referenced to uness otherwise noted. Note 3: Requires either or V INB >3.5V. For more information 3

4 LTC966 TYPICAL PERFORMANCE CHARACTERISTICS 1 1 Suppy Current vs (B).5. V INB Pin Current vs V INB RANGE = 4x OUTA(B) = LOW = 5V I = µa V vs Temperature I = 1µA I VA(B) (µa) I VB (µa) V (V) RANGE = 4x OUTA(B) = LOW V INB(A) = I = µa (V) 45 C 5 C 9 C 15 C C 5 C 9 C 15 C V INB (V) TEMPERATURE ( C) 966 G1 966 G 966 G3.45 V vs Load Current V vs (B) % Range Error vs Temperature.45.4 V IN = 3.5V 5 C V (V) C 5 C 9 C 15 C LOAD CURRENT (ma) V (V) µA 1µA 1mA (V) RANGE ERROR, AV ERR (%) x 1x x 4x TEMPERATURE ( C) 966 G4 966 G5 966 G6 V OS (µv) Comparator V OS vs Temperature V INH(L) = 1.V TEMPERATURE ( C) 966 G7 PROPAGATION DELAY, tpd (µs) V IN Faing Propagation Deay vs % Overdrive 45 C 5 C 9 C 15 C V INL = 1.V V INH = V IN = 1V % OVERDRIVE (%) 966 G8 BUILT-IN HYSTERESIS V HYS () Buit-In Hysteresis vs Temperature 16 5 V INH(L) = 1.V TEMPERATURE ( C) 966 G9 4 For more information

5 TYPICAL PERFORMANCE CHARACTERISTICS LTC966 4 Votage Output High vs Pu-Down Current (OUTA/OUTB) V IN = 1V Votage Output Low vs Pu-Up Current (OUTA/OUTB) 1.5 V IN = 1V 3.5 Votage Output High vs Input Votage I = 1µA V OH (V) V OL (V).75 V OH (V) C 5 C 9 C 15 C PULL-DOWN CURRENT (µa) PULL-UP CURRENT (ma) 45 C 5 C 9 C 15 C V IN (V) G1 966 G G1 PIN FUNCTIONS Exposed Pad (UD16 Ony): Exposed pad may be eft foating or connected to device ground. : Device Ground. INHA: Channe A High Comparator Reference Input. Votage on this pin is mutipied by the configured range setting to set the high or rising threshod. Keep within vaid votage range, V CM, or tie to to configure buit-in hysteresis where high threshod for becomes + V HYS scaed according to the RS pin configuration. INHB: Channe B High Comparator Reference Input. Votage on this pin is mutipied by the configured range setting to set the V INB high or rising threshod. Keep within vaid votage range, V CM, or tie to to configure buit-in hysteresis where high threshod for V INB becomes INLB + V HYS scaed according to the RS pin configuration. : Channe A Low Comparator Reference Input. Votage on this pin is mutipied by the configured range setting to set the ow or faing threshod. Keep within vaid votage range, V CM, or tie to to configure buit-in hysteresis where ow threshod becomes INHA V HYS scaed according to the RS pin configuration. Otherwise, INHA- sets the hysteresis of the Channe A comparator. Osciation wi occur if > INHA uness buit-in hysteresis is enabed. INLB: Channe B Low Comparator Reference Input. Votage on this pin is mutipied by the configured range setting to set the V INB ow or faing threshod. Keep within vaid votage range, V CM, or tie to to configure buit-in hysteresis where ow threshod becomes INHB V HYS scaed according to the RS pin configuration. Otherwise, INHB-INLB sets the hysteresis of the Channe B comparator. Osciation wi occur if INLB > INHB uness buit-in hysteresis is enabed. OUTA: Channe A Comparator Output. OUTA consists of a high votage active pu-down and a gated, resistive (5kΩ) pu-up to an internay generated suppy between 3.5V and 5V depending on input suppy votage. Bocking circuitry at the pin aows the pin to be resistivey pued up to votages as high as 1V without back conducting onto the interna suppy of the part. Poarity with respect to the pin is configured using the poarity seect pin, PSA. OUTA pus ow when the part is in UVLO. For more information 5

6 LTC966 PIN FUNCTIONS OUTB: Channe B Comparator Output. OUTB consists of a high votage active pu-down and a gated, resistive (5kΩ) pu-up to an internay generated suppy between 3.5V and 5V depending on input suppy votage. Bocking circuitry at the pin aows the pin to be resistivey pued up to votages as high as 1V without back conducting onto the interna suppy of the part. Poarity with respect to the V INB pin is configured using the poarity seect pin, PSB. OUTB pus ow when the part is in UVLO. PSA: Channe A Poarity Seection. Connect to or a votage >V TH to configure comparator output to be inverting with respect to. Otherwise connect pin to to configure comparator output to be noninverting with respect to. PSB: Channe B Poarity Seection. Connect to or a votage >V TH to configure comparator output to be inverting with respect to V INB. Otherwise connect pin to to configure comparator output to be noninverting with respect to V INB. : Reference Output. V with respect to. Use a maximum of 1nF to bypass uness damping resistor is used. RS1A-RSA: Channe A Range Seect Input. RS1A-RSA seect 5x, 1x, x or 4x range for Channe A. Connect to or to configure the pin. (See Tabe 1) RS1B-RSB: Channe B Range Seect Input. RS1B-RSB seect 5x, 1x, x or 4x range for Channe B. Connect to or to configure the pin. (See Tabe 1), V INB : Votage Monitor and Suppy Inputs. An interna high vaue resistive divider is connected to the pin. The greater of and V INB is used to generate an interna votage rai with priority given to. If both and V INB fa beow the UVLO threshod minus hysteresis, the outputs are pued ow. If V INB < < 1.V, the ogic state of the outputs cannot be guaranteed. 6 For more information

7 BLOCK DIAGRAM LTC966 1X V V INB V IN PRIORITIZER 7M 7M V INT INHA V HYTH + INHB + V HYS V HYS + + V INT 5k OUTA OUTB INLB V HYTH + PSA RS1A 5x/1x/x/4x RSA PSB RS1B CHANNEL A CHANNEL B RSB 966 BD For more information 7

8 LTC966 OPERATION The LTC966 is a micropower dua channe votage monitor with a 1V maximum operating votage. Each channe is comprised of an interna high vaue resistive divider and a comparator with a high votage output. A reference votage is provided to aow the threshods of each channe to be set independenty. This configuration has the advantage of being abe to monitor very high votages with very itte current draw whie threshod configuration is done using ow vaue resistors at ow votages. The two channes of the LTC966 provide independent monitoring capabiities for mutipe votages or work in conjunction to set up an undervotage/overvotage monitor. Integration of a resistive divider for high votage sensing makes the LTC966 a compact and ow power soution for generating votage status signas to a monitoring system. A buit-in buffered reference gives the monitor fexibiity to operate independenty from a high votage suppy without the requirement of additiona ow votage biasing. The reference provides an accurate votage from which a resistive divider to ground configures the threshod votage for the interna comparators. In addition, the pin can be used as a ogic high votage for the range and poarity seect pins. The input votage threshod at V IN is determined by the votage on the INH and INL pins which are scaed by the attenuation interna resistive divider. In the LTC966 the attenuation of the interna divider is configured using two range seect pins, RS1 and RS to seect 5x, 1x, x or 4x for each channe. Use Tabe 1 to determine the correct configuration for a desired range setting. The poarity seect pins, (PSA/PSB), configure the corresponding OUT pin to be inverting or noninverting with respect to V IN aowing the part to be configured for monitoring overvotage and undervotage conditions with either poarity output. Tabe 1. V IN MONITOR RANGE RANGE SELECTION RS1 RS 1.75V* to 1.5V 5x L L 3.5V to 4.5V 1x H L 7V to 49V x L H 14V to 98V 4x H H *Requires either or V INB > 3.5V. The INH pin determines the high or rising edge threshod for V IN in each channe. If the monitored votage connected to rises to the scaed INHA votage then the OUT pin is pued high assuming PSA is ground. Likewise, the INL pin determines the ow or faing edge threshod for V IN in each channe. If fas to the scaed votage then the OUT pin is pued ow assuming PSA is ground. The amount of hysteresis referred to V IN is the difference in votage between INH and INL scaed according to the RS pin configuration. INH and INL have an aowabe votage range, V CM. Figure 1 shows the aowabe monitor votage at V IN for each range as a function of comparator reference input votage (INL, INH). Typicay, an externa resistive divider biased from is used to generate the INH and INL pin votages. A buit-in hysteresis feature requiring ony two resistors can be enabed on either the V IN rising edge by grounding INH or on the faing edge by grounding INL. For exampe, it is appropriate to ground INH to activate rising edge hysteresis if an accurate faing votage threshod is required for undervotage detection. Conversey, it is appropriate to ground INL for faing edge buit-in hysteresis if an accurate overvotage threshod is required. Do not ground both INH and INL. Osciation occurs if V INL > V INH uness INH buit-in hysteresis is enabed. 8 For more information

9 OPERATION The high votage OUT pins have the capabiity to be pued up to a user defined votage as high as 1V with an externa resistor. The LTC966 aso incudes an interna 5k pu-up resistor to an interna votage between 3.5V and 5V depending on input suppy votage. (See V OH in Eectrica Characteristics) Wire-OR functionaity is impemented by connecting OUTA and OUTB with appropriate monitor configuration. Suppy current is drawn from the higher of or V INB with priority given to. If both V IN pins fa beow the UVLO threshod then both OUT pins are pued ow regardess of the PS pin state. MONITOR THRESHOLD, V IN (V) 1 4x x 1 1x 5x COMPARATOR ERENCE INPUT (INL, INH) (V) LTC F1 Figure 1. Monitor Threshod Threshod vs Comparator Reference Inputs For more information 9

10 LTC966 APPLICATIONS INFORMATION Threshod Configuration Each LTC966 channe (A/B) monitors the votage appied to the corresponding V IN input. A comparator senses the V IN pin on one of its inputs through the interna resistive divider. The other input is connected to INH/INL that is in turn biased with externa resistive dividers off of the pin as shown in Figure a and b. The V IN rising and faing threshods are determined by: V IN(RISE) = RANGE V INH V IN(FALL) = RANGE V INL Where RANGE is the configured range of the interna resistive divider. In order to set the threshod for the LTC966, choose an appropriate range setting for the desired V IN votage threshod such that the INH and INL votages are within the specified common mode range, V CM. For exampe, if a faing threshod of 18V is desired for monitoring a 4V power suppy then a range greater than 1x is aowed. However, to maximize the accuracy of the V IN threshod the smaest acceptabe range is used, 1x in this case. To impement V of hysteresis referred to V IN this means: V INH = V, V INL = 1.8V With 1x range the V IN threshods are: V IN(RISE) = V, V IN(FALL) = 18V One possibe way to configure the threshods is by using three resistors to set the votages on INH and INL. See Figure a. The soution for R1, R and R3 provides three equations and three unknowns. Maximum resistor size is governed by maximum input eakage current. The maximum input eakage current beow 85 C is 1nA. For a maximum error of 1% due to both input currents, the resistive divider current shoud be at east 1 times the sum of the eakage currents, or.µa. If in this exampe, a eakage current error of.1% is desired then the tota divider resistance is 1.MΩ which resuts in a current of µa through this network. For R SUM = 1.MΩ R SUM =R1+R+R3 R1= V INL R SUM 1 ( ) V = ( 1.8V 1.MΩ ) = 899.5kΩ.4V For more information The cosest 1% vaue is 99kΩ. R can be determined from: ( ) R= V INH R SUM R1 V V 1.MΩ = ( ) 99kΩ = 9.kΩ.4V The cosest 1% vaue is 9.9kΩ. R3 can be determined from R SUM : R3 = R SUM R1 R = 1.MΩ 99kΩ 9.9kΩ =.1kΩ The cosest 1% vaue is kω. Pugging the standard vaues back into the equations yieds the design vaues for the V INH and V INL votages: V INH =.1V, V INL = 1.819V The corresponding threshod votages are: V IN(RISE) =.1V, V IN(FALL) = 18.19V Another possibe way to configure the threshods is with independent dividers using two resistors per threshod to set the votages on INH and INL. See Figure b. Care must be taken such that the threshods are not set too cose to each other, otherwise the mismatch of the resistors may cause the votage at INL to be greater than the votage at INH which may cause the comparator to osciate. As in the previous exampe, if R SUM = 1.MΩ is chosen and the target for V INL is 1.8V: R SUM =R1+R ( ) R1= V INL R SUM V = ( 1.8V 1.MΩ ) = 899.5kΩ.4V The cosest 1% vaue is 99kΩ. R can be determined by: R = ( V V INL ) R1 V INL = (.4V 1.8V) ( 99kΩ) 1.8V = 34kΩ

11 APPLICATIONS INFORMATION The cosest 1% vaue is 31kΩ. Pugging the standard vaues back into the equation for V INL yieds the design votage for V INL : ( ) ( ) V INL = R1 V R1+R ( ) ( ) = 1.84V 99kΩ.4V = 31kΩ + 99kΩ At this point in the independent divider exampe ony the vaues required to set the votage at INL have been found. Repeat the process for the INH input by substituting the above equations with V INH for V INL, R3 for R1, R4 for R and V INH =.V. R3 R R1 OUTA 1/ LTC966 RS1A INHA V IN RSA PSA Figure a. Three-Resistor Threshod Configuration Figure b. Two-Resistor Threshod Configuration Using Buit-In Hysteresis The LTC966 has the capabiity of simpifying the threshod configuration such that ony two resistors per channe are required. The device pins can be configured to seect a buit-in hysteresis votage, V HYS, which can be appied to either the rising or faing threshod depending on whether the INH or INL pin is grounded. Note that the hysteresis votage at each range setting remains at a fixed vaue. Figure 3 introduces exampes of each configuration. For exampe, if INH is biased from an externa divider and the INL pin is grounded, then hysteresis is enabed on the ow or faing threshod. The ow threshod is then V HYS reative to the high threshod determined by INH. Figure 3a introduces buit-in hysteresis on the rising edge because INH is pued to ground. A two-resistor network, R1 and R, is used to set the votage on INL using: R R1 = V V INL 1 R R1 R4 R3 V IN OUTA 1/ LTC966 RS1A INHA RSA PSA 966 Fab LTC966 Using buit-in hysteresis, the V IN threshods are: V IN(RISE) = RANGE (INL + V HYS ) V IN(FALL) = RANGE INL Figure 3b introduces buit-in hysteresis on the faing edge because INL is pued to ground. Simiary, a two-resistor network, R3 and R4, is used to set the votage on INH using: R4 R3 = V V INH 1 Using buit-in hysteresis the V IN threshods are: V IN(RISE) = RANGE INH V IN(FALL) = RANGE (INH V HYS ) Consider V INH = V with buit-in hysteresis activated on the faing edge. For 1x range, 1.1% faing hysteresis is obtained. If a arger percentage of hysteresis is desired then V INH is aternativey set to 1V and the range is seected to be x to obtain the same V IN threshod but with.% faing hysteresis. The amount of buit-in hysteresis is scaed according to Tabe. If more hysteresis is needed then it is impemented in the externa resistive divider as described in the Threshod Configuration section. R R1 V IN OUTA 1/ LTC966 RS1A INHA RSA PSA Figure 3a. Rising Edge Buit-In Hysteresis by Grounding INH Figure 3b. Faing Edge Buit-In Hysteresis by Grounding INL Tabe. Buit-In Hysteresis Votage vs Range RANGE V IN ERRED BUILT-IN HYSTERESIS 5x 11 1x x 44 4x 88 R4 R3 V IN OUTA 1/ LTC966 RS1A INH INL RSA PSA 966 F3ab For more information 11

12 LTC966 APPLICATIONS INFORMATION Error Anaysis V IN threshods are subject to the foowing errors: Votage Variation ( V ) Comparator Offset (V OS ) Interna Divider Range Error (A VERR ) Externa Resistive Divider Error (A XERR ) The effect these errors have on the V IN threshod is expressed by: V ERR =RANGE ±V OS ± V V INH(L) ± V INH(L) A XERR V ±RANGE A VERR V INH(L) A XERR = TOLERANCE V INH(L) V Externa divider error is determined by the percentage toerance vaues of the resistors. If 1% toerance resistors are used in the externa divider then there is a % worst-case votage error associated with it. The effects of comparator offset and V votage are uncorreated with each other. Therefore, a Root-Sum-Square can be appied to the error votage referred to V IN. Using the exampe from Threshod Configuration and assuming 1% resistors impement the externa resistive divider, the faing V IN threshod of approximatey 18V has an error toerance of: V ERR() = RANGE ( ) ± V V INL V 1.8V = ( 1) ±4.4V = ±18 V ERR(EXT) = RANGE ( ) ±V INL.1 1 V INL V = ( 1) ( ±1.8V.5) = ±9 V ERR(VOS) = RANGE ( ) ±16 V ERR(RS) V ERR = ( )( ± V OS ) = 1 ( ) = ±16 ( )( ±A VERR )( ±V INL ) ( ) ( ±.4) ( 1.8V) = ±7 = RANGE = 1 V ERR() + V ERR(EXT) + V ERR(VOS) + V ERR(RS) = ( ±18) + ( ±9) + ( ±16) + ( ±7 ) = ±67 For more information The actua V IN faing threshod has an error toerance of ±67 or ±1.48%. Improving Threshod Accuracy The biggest threshod error terms are: Externa Resistive Divider Accuracy Votage Variation Even using 1% toerance resistors, externa resistive divider accuracy sti accounts for as much as ±% threshod error whie votage variation accounts for ±1% threshod error. In order to minimize these threshod error terms, an externa reference can be used to set the threshods for INH/INL as shown in Figure 4. An LT has an initia accuracy of.5% and provides bias via the.1% resistive divider network for INH and INL. It is biased off of the LTC966 pin. The threshod error toerance is cacuated using the method described in the Typica Appications section with V = ±1.4 given the initia accuracy of the LT V output and using.1% toerance resistors for the externa divider. V ERR() = RANGE ( ) ± V V INL V 1.8V = ( 1) ±1.4.48V = ±9 V ERR(EXT) = RANGE = ( 1) ( ±1.8V.5) = ±9 V ERR(VOS) = RANGE ( ) ±1.6 V ERR(RS) V ERR = ( ) ±V INL.1 1 V INL V ( )( ± V OS ) = 1 ( ) = ±16 ( )( ±A VERR )( ±V INL ) ( ) ( ±.4) ( 1.8V) = ±7 = RANGE = 1 V ERR() + V ERR(EXT) + V ERR(VOS) + V ERR(RS) = ( ±9) + ( ±9) + ( ±16) + ( ±7 ) = ±75 The resuting V IN threshod error is reduced to ±.4% from ±1.48% in the previous error anaysis exampe.

13 APPLICATIONS INFORMATION 1µF Figure 4. Reducing V IN Threshod Error Disabing a Channe Figure 5 shows the proper technique for disabing a channe. Tabe 4 summarizes the correct connections. Correcty disabing an unused channe prevents its comparator output from chattering and introducing unwanted noise in the system. Tabe 4. Disabing a Channe PIN V IN INH INL RS1 RS PS OUT R k.1% R1 1.8M.1% OPEN R3 47.5k.1% LT OUT IN R4 1k OUTA 1/ LTC966 INHA RS1A RSA V IN Figure 5. Disabing a Channe V IN LTC966 INH INL 966 F4 CONNECT TO or or or Open Output Configuration with Poarity Seection The OUT pin may be used with a wide range of user-defined votages up to 1V with an externa resistor. Seect a resistor compatibe with desired output rise time and oad PSA 966 F5 OPEN LTC966 current specifications. When the status outputs are ow, power is dissipated in the pu-up resistors. An interna pu-up is present if the OUT pins are eft foating or if ow power consumption is required. The interna pu-up resistor does not draw current if an externa resistor pus OUT up to a votage greater than V OH. If PS is connected to ground, the comparator output is noninverting. This means that OUT pus ow when V IN fas beow the scaed INL votage. OUT is reeased after V IN rises above the scaed INH votage. Likewise, if PS is connected to or a votage >V TH, the comparator output is inverting. This means that OUT pus ow when V IN rises above the scaed INH votage and is reeased when V IN fas beow the scaed INL votage. If both V IN pins fa beow the UVLO threshod minus hysteresis, the outputs are pued to ground. The outputs are guaranteed to stay ow for V INB 1.5V regardess of the output ogic configuration. It is recommended that circuit board traces associated with the OUT pin be ocated on a different ayer than those associated with the INH/INL and pins where possibe to avoid capacitive couping. Hot Swap Events The LTC966 can withstand high votage transients up to 14V. However, when a suppy votage is abrupty connected to the input resonant ringing can occur as a resut of series inductance. The peak votage coud rise to x the input suppy, but in practice can reach.5x if a capacitor with a strong votage coefficient is present. Circuit board trace inductances of as itte as 1nH can produce significant ringing. Ringing beyond the absoute maximum specification can be destructive to the part and shoud be avoided whenever possibe. One effective means to eiminate ringing seen at the V IN pins and to protect the part is to incude a 1kΩ to 5kΩ resistance between the monitored votage and the V IN pin as shown in Figure 6. This provides damping for the resonant circuit. If there is a decouping capacitor on the /V INB pins the time constant formed by the RC network shoud be considered. For more information 13

14 LTC966 APPLICATIONS INFORMATION V IN R S 1k LTC966 R S LTC966 /V INB R S INH INH LTC966 C INL C INL 966 F7ab 966 F6 Figure 6. Hot Swap Protection High Votage Pin Creepage/Cearance Options Appropriate spacing between component ead traces is critica to avoid fashover between conductors. There are mutipe industry and safety standards that have different spacing requirements depending on factors such as operating votage, presence of conforma coat, eevation, etc. The LTC966 is avaiabe in a -ead SW package which offers pin-to-pin cearance of at east.76mm (.3in) to satisfy high votage externa component ead specifications for standards such as the UL695 and IPC1. The package incorporates unconnected pins between a adjacent high votage and ow votage pins to maximize PC board trace cearance. For votages >3V the SW shoud be used, otherwise the smaer QFN is sufficient when cearance is not an issue. For more information, refer to the printed circuit board design standards described in IPC1 and UL695. RESISTANCE VALUE (kω) 1 1 7a 1 7c Figure 7. Using Series Resistance to Dampen Transient Response.4V 5/DIV CAPACITANCE VALUE (µf) V 1nF 1nF + 4.3kΩ.1µF + 1.5kΩ 1µF + 6Ω 966 F7c 7b Votage Reference The pin is a buffered reference with a votage of V referenced to. A bypass capacitor up to 1pF in vaue can be driven by the pin directy. Larger capacitances require a series resistance to dampen the transient response as shown in Figure 7A. If a resistive divider is aready present then the bypass capacitor can be connected to the INH or INL pin as shown in Figure 7B. Figure 7C shows the resistor vaue required for different capacitor vaues to achieve critica damping. Bypassing the reference can hep prevent fase tripping of the comparators by preventing gitches on the INH/INL pins. Figure 8 shows the reference oad transient response. Figure 9 shows the reference ine transient response. If there is a decouping capacitor on the INH/INL pin the time constant formed by the RC network shoud be considered. Use a capacitor with a compatibe votage rating. 14 1µA 1µA.4V 1/DIV For more information 8V 1V/DIV 3.5V LOAD CURRENT 1µs/DIV 966 F8 Figure 8. V Load Transient V 1nF 1µF + 6Ω 1µs/DIV 966 F9 Figure 9. V Line Transient

15 LTC966 TYPICAL APPLICATIONS 48V UV/OV Monitor The circuit in Figure 1 monitors a singe 48V suppy and is configured for UV/OV window detection. Channe A is used to monitor undervotage conditions where the 36V threshod is determined by 1.8V at scaed by x. Channe B is used to monitor overvotage conditions where the 7V threshod is determined by the same 1.8V at INHB with 4x range. UV is pued high to indicate an undervotage condition when the suppy drops beow the UV threshod. Therefore PSA is pued to to obtain the correct poarity on OUTA. OV is pued high when the suppy rises above the OV threshod which means PSB is pued to ground to obtain the appropriate output poarity. Connecting INHA and INLB to ground enabes interna hysteresis for each channe in the appropriate direction and reduces the number of externa components. ±15V Undervotage Monitor The LTC966 can be used to monitor a positive and a negative suppy simutaneousy. In the circuit shown in Figure 11, Channe B is used to monitor the 15V suppy by connecting V INB s interna resistor divider to and configuring to 5x range. The votage at the V IN sensing input of the Channe B comparator is fixed at 48. When the 15V suppy is undervotage INHB > 48 and OUTB is pued ow because PSB is connected to ground. As the negative suppy comes into reguation the comparator monitors the INHB pin to detect when its votage crosses 48 corresponding to 14.3V. UVB is reeased indicating that there is no onger an undervotage condition. As the negative suppy drops out of reguation the comparator monitors the INLB pin to detect when its votage crosses 48, corresponding to 13.6V due to the externa divider 48V OV/UV MONITOR CHANNEL RISING THRESHOLD FALLING THRESHOLD HYSTERESIS RANGE A 36.6V 36.V.6V x B 7.V 71.V 1.V 4x 48V 5V C1 1pF 1V R 94k INHA V INB OUTA R3 1k R4 1k UV R1 887k INHB INLB LTC966 OUTB OV 5V SYS PSA RS1A RSA PSB RS1B RSB 966 F1 Figure 1. Use Range Seection and Buit-In Hysteresis to Minimize Externa Components For more information 15

16 LTC966 TYPICAL APPLICATIONS gain. UVB is pued ow after the comparator detects the threshod crossing to indicate an undervotage condition. Channe A is configured to monitor for an undervotage condition on the 15V suppy by puing UVA ow when the positive suppy drops beow 13.6V. 48V UV/OV Votage Monitor In the circuit shown in Figure 1, the LTC966 is configured as a 48V UV/OV monitor by referencing the pin to the negative suppy. R1 through R4 configure the UV and OV threshods, where channe A and B are configured simiary to the 48V UV/OV monitor circuit in Figure 1. Hysteresis for each comparator is impemented by the externa resistor network. High votage OUT pins aow a pair of 4N5 opto-coupers to be used in transating the status signas for the 5V system. R5, R6, R7 and R8 set the maximum current through the optos to be approximatey 4.mA. If an exposed pad is present it shoud be tied to the pin or eft open. ±15V UV MONITOR CHANNEL RISING THRESHOLD FALLING THRESHOLD HYSTERESIS RANGE A 14.3V 13.5V.8V 1x B 14.4V 13.6V.8V 5x 15V 5V R S 6 C1 1µF 1V R3 16k R 1.4k R1 6k R4 18k R5 8.6k R6 1.4M V INB INHA OUTA LTC966 INHB OUTB INLB PSA RS1A RSA PSB RS1B RSB R7 1k R8 1k UVA UVB 5V SYS RTN 15V 965 F11 Figure 11. Dua Poarity Votage Monitoring 16 For more information

17 PACKAGE DESCRIPTION Pease refer to for the most recent package drawings. LTC966 UD Package 16-Lead Pastic QFN (3mm 3mm) (Reference LTC DWG # Rev Ø).7 ± ±.5.1 ± ±.5 (4 SIDES) PACKAGE OUTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3. ±.1 (4 SIDES) PIN 1 TOP MARK (NOTE 6).5 ±.5.5 BSC.75 ± ±.1 (4-SIDES) BOTTOM VIEW EXPOSED PAD R =.115 TYP PIN 1 NOTCH R =. TYP OR.5 45 CHAMFER 1.4 ±.1 (UD16) QFN NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO- VARIATION (WEED-). DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A ERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE.5 ±.5.5 BSC For more information 17

18 LTC966 PACKAGE DESCRIPTION Pease refer to for the most recent package drawings. SW Package -Lead Pastic Sma Outine (Wide.3 Inch) (Reference LTC DWG # ).3 ±.5 TYP N.5 BSC.45 ± ( ) NOTE MIN.35 ±.5 N NOTE ( ) 1 3 N/ N/ RECOMMENDED SOLDER PAD LAYOUT.5 (.17) RAD MIN ( ) NOTE ( ) 8 TYP (.36.64) ( ) (.9.33) NOTE 3 (1.7) BSC.16.5 ( ) ( ) NOTE: TYP INCHES 1. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.6" (.15mm).4.1 (.1.35) S (WIDE) 5 18 For more information

19 REVISION HISTORY LTC966 REV DATE DESCRIPTION PAGE NUMBER A 9/15 Fixed typos 1, 3, 1, 11, 1, 15 B 3/16 Added ABS Max Rating for INHA, INHB, and INLB pins Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection For more of its information circuits as described herein wi not infringe on existing patent rights. 19

20 LTC966 TYPICAL APPLICATION RTN 48V UV/OV MONITOR CHANNEL RISING THRESHOLD FALLING THRESHOLD HYSTERESIS RANGE A 4.V 36.V 4.V x B 7.V 56.V 16.V 4x 4.mA AT 48V R6 1k 4N5 5V R9 1k 4.mA AT 48V R8 1k R1 1k UV OV 5V SYS C1 1pF 1V R4 66.5k R3 33.k R 66.5k INHA INHB V INB LTC966 OUTA OUTB R5 1k R7 1k 4N5 INLB R1 3k PSA RS1A RSA PSB RS1B RSB 966 F1 48V Figure 1. Monitoring Negative Votage with Isoation RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC136 Micropower Tripe Suppy Monitor for 5V/.5V, 3.3V and ADJ 4.75V, 3.118V, 1V Threshod (±.75%) and ADJ LTC144/LTC1441/ Utraow Power Singe/Dua Comparator with Reference Adjustabe Hysteresis, 3mm 3mm.75mm DFN Package LTC144 LTC176/LTC177/ Micropower Tripe Suppy Monitor Adjustabe Reset and Watchdog Timeouts LTC178 LTC1985 Micropower Tripe Suppy Monitor with Push-Pu Reset Output 5-Lead SOT-3 Package LTC9/LTC91/ LTC9 Programmabe Quad Suppy Monitor Adjustabe Reset, Watchdog Timer and Toerance, 1-Lead MSOP and DFN Packages LTC93 Precision Quad Suppy Monitor 6-Lead SOT-3 and DFN Packages LTC94/LTC95/ Three-State Programmabe Precision Dua Suppy Monitor 8-Lead SOT-3 and DFN Packages LTC96/LTC97 LTC98 Precision Six-Suppy Monitor (Four Fixed and Two Adjustabe) 8-Lead TSOT-3 and DFN Packages LTC99/LTC919 Precision Tripe/Dua Input UV, OV and Negative Votage Monitor Shunt Reguated V CC Pin, Adjustabe Threshod and Reset LTC91 Octa Positive/Negative Votage Monitor Separate V CC Pin, Eight Inputs, Up to Two Negative Monitors Adjustabe Reset Timer, 16-Lead SSOP and DFN Packages LTC91/LTC913/ LTC914 Singe/Dua/Quad UV and OV Votage Monitors Separate V CC Pin, Adjustabe Reset Timer LTC915/LTC916/ LTC917/LTC918 Singe Votage Supervisors with 7 Pin-Seectabe Threshods Manua Reset and Watchdog Functions, 8- and 1-Lead TSOT-3, MSOP and DFN Packages LTC965 1V Micropower Singe Votage Monitor 3.5V to 98V Monitoring Range, 3.5V to 1V Operating Range, 7µA Quiescent Current LTC96 36V Nano-Current Two Input Votage Monitor 36V, 85nA Quiescent Current, mm mm 8-Lead DFN and TSOT-3 Packages LT67 Micropower Dua Comparator with 4 Reference SOT-3, mm 3mm DFN Package Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA For more information (48) FAX: (48) LT 316 REV B PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 15