LTC2912 Single UV/OV Voltage Monitor DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

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1 LTC9 Single UV/OV Voltage Monitor FEATURES Monitors Single Voltage Adjustable UV and OV Trip Values Guaranteed Threshold Accuracy: ±.% Power Supply Glitch Immunity Adjustable Reset Timeout with Timeout Disable 9μA Quiescent Current Open-Drain OV and UV Outputs Guaranteed OV and UV for V Available in 8-Lead ThinSOT TM and (mm mm) DFN Packages APPLICATIONS Desktop and Notebook Computers Network Servers Core, I/O Voltage Monitors DESCRIPTION The LTC 9 voltage monitor is designed to detect power supply undervoltage and overvoltage events. The and monitor inputs include filtering to reject brief glitches, thereby ensuring reliable reset operation without false or noisy triggering. An adjustable timer defines the duration of the overvoltage and undervoltage reset outputs which function independently. While the LTC9 operates directly from.v to 6V supplies, an internal shunt regulator coupled with low supply current demand allows operation from higher voltages such as V, V or 8V. Three output configurations are available: the LTC9- has a latch control for the OV output; the LTC9- has an OV and UV output disable feature for margining applications; the LTC9- is identical to the LTC9- but with a noninverting, OV output. The LTC9 provides a precise, versatile, space-conscious micropower solution for voltage monitoring., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Single OV/UV Supply Monitor,.V ±% Tolerance Reset Time-Out Period vs Capacitance POWER SUPPLY.V 7.k k.k.μf OV LTC9- UV LATCH GND TMR SYSTEM 9 TAa UV/OV TIMEOUT PERIOD, t UOTO (ms) nf TIMEOUT = ms. TMR PIN CAPACITANCE, C TMR (nf) 9 G8 9fa

2 LTC9 ABSOLUTE MAXIMUM RATINGS (Note ) Terminal Voltages (Note )....V to 6V OV, UV, OV....V to 6V TMR...V to ( +.V),, LATCH, DIS....V to 7.V Terminal Currents I VCC...mA I UV, I OV, I OV...mA PACKAGE/ORDER INFORMATION LATCH UV OV GND TOP VIEW TMR TS8 PACKAGE 8-LEAD PLASTIC TSOT- T JMAX = C, θ JA = 9 C/W TMR TOP VIEW 9 8 LATCH 7 UV 6 OV GND DDB PACKAGE 8-LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = 76 C/W EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING* LTC9CTS8- LTCJW LTC9CDDB- LCJZ LTC9ITS8- LTCJW LTC9IDDB- LCJZ LTC9HTS8- LTCJW LTC9HDDB- LCJZ DIS UV OV GND TOP VIEW TMR TS8 PACKAGE 8-LEAD PLASTIC TSOT- T JMAX = C, θ JA = 9 C/W TMR TOP VIEW 9 8 DIS 7 UV 6 OV GND DDB PACKAGE 8-LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = 76 C/W EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING* LTC9CTS8- LTCJX LTC9CDDB- LCKB LTC9ITS8- LTCJX LTC9IDDB- LCKB LTC9HTS8- LTCJX LTC9HDDB- LCKB LATCH UV OV GND TOP VIEW TMR TS8 PACKAGE 8-LEAD PLASTIC TSOT- T JMAX = C, θ JA = 9 C/W Operating Temperature Range LTC9C... C to 7 C LTC9I... C to 8 C LTC9H... C to C Storage Temperature Range TSOT... 6 C to C DFN... 6 C to C Lead Temperature (Soldering, sec) TSOT... C TMR TOP VIEW 9 8 LATCH 7 UV 6 OV GND DDB PACKAGE 8-LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = 76 C/W EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING* LTC9CTS8- LTCJY LTC9CDDB- LCKC LTC9ITS8- LTCJY LTC9IDDB- LCKC LTC9HTS8- LTCJY LTC9HDDB- LCKC Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: *The temperature grade is identifi ed by a label on the shipping container. 9fa

3 ELECTRICAL CHARACTERISTICS Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. LTC9 The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = C. =.V, =.V, =.V, LATCH = unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V SHUNT Shunt Regulator Voltage I CC = ma V C < T A < V ΔV SHUNT Shunt Regulator Load Regulation I CC = ma to ma mv Supply Voltage (Note ). V SHUNT V R(MIN) Minimum Output Valid DIS = V V (UO) Supply Undervoltage Lockout DIS = V, Rising.9. V Δ(UYST) Supply Undervoltage Lockout Hysteresis DIS = V mv I CC Supply Current =.V to 6V 9 7 μa V UOT Undervoltage/Overvoltage Threshold 9 8 mv t UOD Undervoltage/Overvoltage Threshold to V Hn = V UOT mv or V Ln = V UOT + mv μs Output Delay I L, Input Current ± na C < T A < ± na t UOTO UV/OV Time-Out Period C TMR = nf ms C < T A < 6 8. ms V LATCH(VIH) OV Latch Clear Input High. V V LATCH(VIL) OV Latch Clear Input Low.8 V I LATCH LATCH Input Current V LATCH >.V ± μa I DIS DIS Input Current V DIS >.V. μa V DIS(VIH) DIS Input High. V V DIS(VIL) DIS Input Low.8 V I TMR(UP) TMR Pull-Up Current V TMR = V...8 μa C < T A <...8 μa I TMR(DOWN) TMR Pull-Down Current V TMR =.6V...8 μa C < T A <...8 μa V TMR(DIS) Timer Disable Voltage Referenced to 8 7 mv V OH Output Voltage High UV/OV/OV =.V, I UV/OV = μa V V OL Output Voltage Low UV/OV/OV =.V, I UV/OV =.ma = V, I UV = μa.... Note : maximum pin voltage is limited by input current. Since the pin has an internal 6.V shunt regulator, a low impedance supply that exceeds 6V may exceed the rated terminal current. Operation from higher voltage supplies requires a series dropping resistor. See Applications Information. V V 9fa

4 LTC9 TIMING DIAGRAMS Monitor Timing Monitor Timing V UOT V UOT t UOD t UOTO t UOD t UOTO UV V 9 TD OV V 9 TD Monitor Timing (TMR Pin Strapped to ) Monitor Timing (TMR Pin Strapped to ) V UOT V UOT t UOD t UOD t UOD t UOD UV V 9 TD OV V 9 TD TYPICAL PERFORMANCE CHARACTERISTICS. Input Threshold Voltage vs Temperature Supply Current vs Temperature 6.8 Shunt Voltage vs Temperature THRESHOLD VOLTAGE, V UOT (V) I CC (μa) = V =.V =.V (V) ma ma ma ma μa.9 TEMPERATURE ( C) 7 TEMPERATURE ( C) 7 6. TEMPERATURE ( C) 7 9 G 9 G 9 G 6.7 Shunt Voltage vs I CC 7 Typical Transient Duration vs Comparator Overdrive.8 UV Output Voltage vs (V) C C 6. 8 C 6 8 I CC (ma) TYPICAL TRANSIENT DURATION (μs) 6. =.V = 6V RESET OCCURS ABOVE CURVE COMPARATOR OVERDRIVE PAST THRESHOLD (%) UV VOLTAGE (V).6.. UV WITHOUT PULL-UP SUPPLY VOLTAGE, (V) UV WITH k PULL-UP 9 G 9 G 9 G6 9fa

5 TYPICAL PERFORMANCE CHARACTERISTICS LTC9 UV VOLTAGE (V) UV Output Voltage vs =.V SEL = UV/OV TIMEOUT PERIOD, t UOTO (ms) Reset Time-Out Period vs Capacitance PULL-DOWN CURRENT, I UV (ma) UV, I SINK vs =.V SEL = UV AT mv UV AT mv SUPPLY VOLTAGE, (V). TMR PIN CAPACITANCE, C TMR (nf) SUPPLY VOLTAGE, (V) 9 G7 9 G8 9 G9 UV/OV, V OL (V) UV/OV, Voltage Output Low vs Output Sink Current 8 C C C UV/OV TIMEOUT PERIOD, t OUTO (ms) Reset Timeout Period vs Temperature C TMR = nf I UV/OV (ma) 6 TEMPERATURE ( C) 7 9 G 9 G PIN FUNCTIONS (DFN/TSOT Packages) DIS (Pin 8/Pin, LTC9-): Output Disable Input. Disables the OV and UV output pins. When DIS is pulled high, the OV and UV pins are not asserted except during a UO condition. Pin has a weak (μa) internal pull-down to GND. Leave pin open if unused. Exposed Pad (Pin 9, DDB Package): Exposed Pad may be left open or connected to device ground. GND (Pin /Pin ): Device Ground. LATCH (Pin 8/Pin, LTC9-, LTC9-): OV/OV Latch Clear/Bypass Input. When pulled high, OV/OV latch is cleared. While held high, OV/OV has a similar delay and output characteristic as UV. OV (Pin 6/Pin, LTC9-, LTC9-): Overvoltage Logic Output. Asserts low when the input voltage is above threshold. Latched low (LTC9-). Held low for programmed delay time after input is valid (LTC9-). Pin has a weak pull-up to and may be pulled above using an external pull-up. Leave pin open if unused. 9fa

6 LTC9 PIN FUNCTIONS (DFN/TSOT Packages) OV (Pin 6/Pin, LTC9-): Overvoltage Logic Output. Asserts high with a weak internal pull-up to when the input is above threshold. Latches high. May be pulled above using an external pull-up. Leave pin open if unused. TMR (Pin /Pin ): Reset Delay Timer. Attach an external capacitor (C TMR ) of at least pf to GND to set a reset delay time of 9ms/nF. A nf capacitor will generate an 8.ms reset delay time. Tie pin to to bypass timer. UV (Pin 7/Pin ): Undervoltage Logic Output. Asserts low when the input voltage is below threshold. Held low for a programmed delay time after the input is valid. Pin has a weak pull-up to and may be pulled above using an external pull-up. Leave pin open if unused. (Pin /Pin 8): Supply Voltage. Bypass this pin to GND with a.μf (or greater) capacitor. Operates as a direct supply input for voltages up to 6V. Operates as a shunt regulator for supply voltages greater than 6V and should have a resistance between the pin and the supply to limit input current to no greater than ma. When used without a current-limiting resistance, pin voltage must not exceed 6V. (Pin /Pin 7): Voltage High Input. When the voltage on this pin is below.v, an undervoltage condition is triggered. Tie pin to if unused. (Pin /Pin 6): Voltage Low Input. When the voltage on this pin is above.v, an overvoltage condition is triggered. Tie pin to GND if unused. BLOCK DIAGRAM TMR OSCILLATOR k UV PULSE GENERATOR UV 7 DISABLE UO V UO k OV PULSE GENERATOR DISABLE LTC9- LTC9- OV/OV 6.V GND LTC9- OV LATCH CLEAR/BYPASS LATCH 8 LTC9-, LTC9- V + V μa DIS 8 LTC9-6 9 BD 9fa

7 APPLICATIONS INFORMATION Voltage Monitoring The LTC9 is a low power voltage monitoring circuit with an undervoltage and an overvoltage input. A timeout period that holds OV and UV asserted after a fault has cleared is adjustable using an external capacitor and may be externally disabled. When configured to monitor a positive voltage V n using the -resistor circuit configuration shown in Figure, will be connected to the high side tap of the resistive divider and will be connected to the low side tap of the resistive divider. -Step Design Procedure The following -step design procedure allows selecting appropriate resistances to obtain the desired UV and OV trip points for the voltage monitor circuit in Figure. For supply monitoring, V n is the desired nominal operating voltage, I n is the desired nominal current through the resistive divider, V OV is the desired overvoltage trip point and V UV is the desired undervoltage trip point.. Choose R A to obtain the desired OV trip point R A is chosen to set the desired trip point for the overvoltage monitor. R A V V =. n () I V V n n R C OV LTC9 LTC9. Choose R B to obtain the desired UV trip point Once R A is known, R B is chosen to set the desired trip point for the undervoltage monitor. R B V V =. n RA () I V n UV. Choose R C to complete the design Once R A and R B are known, R C is determined by: R C V = n RA RB () I n If any of the variables V n, I n, V UV or V OV change, then each step must be recalculated. Voltage Monitor Example A typical voltage monitor application is shown in Figure. The monitored voltage is a V ±% supply. Nominal current in the resistive divider is μa.. Find R A to set the OV trip point of the monitor. R A =. V V µa. V. k. Find R B to set the UV trip point of the monitor. R B =. V V µa. V. k. k. Determine R C to complete the design. R B +.V + UV R V C =. k. k k µa V V ±% V R A Figure. -Resistor Positive UV/OV Monitoring Confi guration + OV 9 F R C k R B.k R A.k OV LTC9- UV GND 9 F Figure. Typical Supply Monitor 9fa 7

8 LTC9 APPLICATIONS INFORMATION Power-Up/Power-Down As soon as reaches V during power up, the UV output asserts low and the OV output weakly pulls to. The LTC9 is guaranteed to assert UV low, OV high (LTC9-, LTC9-) and OV low (LTC9-) under conditions of low, down to = V. Above = V (.V maximum), the and inputs take control. Once the input and become valid an internal timer is started. After an adjustable delay time, UV weakly pulls high. Threshold Accuracy Reset threshold accuracy is important in a supply-sensitive system. Ideally, such a system resets only if supply voltages fall outside the exact thresholds for a specified margin. Both LTC9 inputs have a relative threshold accuracy of ±.% over the full operating temperature range. For example, when the LTC9 is programmed to monitor a V input with a % tolerance, the desired UV trip point is.v. Because of the ±.% relative accuracy of the LTC9, the UV trip point can be anywhere between.v and.67v which is.v ±.%. Likewise, the accuracy of the resistances chosen for R A, R B and R C can affect the UV and OV trip points as well. Using the example just given, if the resistances used to set the UV trip point have % accuracy, the UV trip range is between.v and.6v. This is illustrated in the following calculations. The UV trip point is given as: R V UV =.V + C R A + R B The two extreme conditions, with a relative accuracy of.% and resistance accuracy of %, result in: and R V UV(MIN) =.V.98 + C.99 ( R A + R B ). R V UV(MAX) =.V. + C. ( R A + R B ).99 For a desired trip point of.v, Therefore, R C R A + R B = 8 V UV(MIN) =.V =.V and V UV(MAX) =.V =.6V Glitch Immunity In any supervisory application, noise riding on the monitored DC voltage causes spurious resets. To solve this problem without adding hysteresis, which causes a new error term in the trip voltage, the LTC9 lowpass filters the output of the first stage comparator at each input. This filter integrates the output of the comparator before asserting the UV or OV logic. A transient at the input of the comparator of sufficient magnitude and duration triggers the output logic. The Typical Performance Characteristics show a graph of the Transient Duration vs Comparator Overdrive. UV/OV Timing The LTC9 has an adjustable timeout period (t UOTO ) that holds OV, OV or UV asserted after each fault has cleared. This delay assures a minimum reset pulse width allowing settling time for the monitored voltage after it has entered the valid region of operation. 8 9fa

9 LTC9 APPLICATIONS INFORMATION When the input drops below its designed threshold, the UV pin asserts low. When the input recovers above its designed threshold, the UV output timer starts. If the input remains above the designed threshold when the timer finishes, the UV pin weakly pulls high. However, if the input falls below its designed threshold during this timeout period, the timer resets and restarts when the input is above the designed threshold. The OV and OV outputs behave as the UV output when LATCH is high (LTC9-, LTC9-). Selecting the UV/OV Timing Capacitor The UV and OV timeout period (t UOTO ) for the LTC9 is adjustable to accommodate a variety of applications. Connecting a capacitor, C TMR, between the TMR pin and ground sets the timeout period. The value of capacitor needed for a particular timeout period is: C TMR = t UOTO 9 [F/s] The Reset Timeout Period vs Capacitance graph found in the Typical Performance Characteristics shows the desired delay time as a function of the value of the timer capacitor that must be used. The TMR pin must have a minimum pf load or be tied to. For long timeout periods, the only limitation is the availability of a large value capacitor with low leakage. Capacitor leakage current must not exceed the minimum TMR charging current of.μa.tying the TMR pin to bypasses the timeout period. Undervoltage Lockout When falls below V, the LTC9 asserts an undervoltage lockout (UO) condition. During UO, UV is asserted and pulled low while OV and OV are cleared and blocked from asserting. When rises above V, UV follows the same timing procedure as an undervoltage condition on the input. Shunt Regulator The LTC9 has an internal shunt regulator. The pin operates as a direct supply input for voltages up to 6V. Under this condition, the quiescent current of the device remains below a maximum of 7μA. For voltages higher than 6V, the device operates as a shunt regulator and should have a resistance R Z between the supply and the pin to limit the current to no greater than ma. When choosing this resistance value, select an appropriate location on the I-V curve shown in the Typical Performance Characteristics to accommodate any variations in due to changes in current through R Z. UV, OV and OV Output Characteristics The DC characteristics of the UV, OV and V pull-up and pull-down strength are shown in the Typical Performance Characteristics. Each pin has a weak internal pull-up to and a strong pull-down to ground. This arrangement allows these pins to have open-drain behavior while possessing several other beneficial characteristics. The weak pull-up eliminates the need for an external pull-up resistor when the rise time on the pin is not critical. On the other hand, the open-drain configuration allows for wired-or connections, and is useful when more than one signal needs to pull down on the output. of V guarantees a maximum V OL =.V at UV. At = V, the weak pull-up current on OV is barely turned on. Therefore, an external pull-up resistor of no more than k is recommended on the OV pin if the state and pull-up strength of the OV pin is crucial at very low. Note however, by adding an external pull-up resistor, the pull-up strength on the OV pin is increased. Therefore, if it is connected in a wired-or connection, the pull-down strength of any single device must accommodate this additional pull-up strength. Output Rise and Fall Time Estimation The UV, OV and OV outputs have strong pull-down capability. The following formula estimates the output fall time (9% to %) for a particular external load capacitance (C LOAD ): t FALL. R PD C LOAD where R PD is the on-resistance of the internal pull-down transistor, typically Ω at > V and at room temperature ( C). C LOAD is the external load capacitance on the pin. Assuming a pf load capacitance, the fall time is 6.ns. 9fa 9

10 LTC9 APPLICATIONS INFORMATION The rise time on the UV, OV and V pins is limited by a k pull-up resistance to. A similar formula estimates the output rise time (% to 9%) at the UV, OV and OV pins: t RISE. R PU C LOAD where R PU is the pull-up resistance. OV/OV Latch (LTC9-, LTC9-) With the LATCH pin held low, the OV pin latches low (LTC9-) and the OV pin latches high (LTC9-) when an OV condition is detected. The latch is cleared by raising the LATCH pin high. If an OV condition clears while LATCH is held high, the latch is bypassed and the OV and OV pins behave the same as the UV pin with a similar timeout period at the output. If LATCH is pulled low while the timeout period is active, the OV and OV pins latch as before. Disable (LTC9-) The LTC9- allows disabling the UV and OV outputs via the DIS pin. Pulling DIS high forces both outputs to remain weakly pulled high, regardless of any faults that occur on the inputs. However, if a UO condition occurs, UV asserts and pulls low, but the timeout function is bypassed. UV pulls high as soon as the UO condition is cleared. DIS has a weak μa (typical) internal pull-down current guaranteeing normal operation with the pin left open. TYPICAL APPLICATIONS Dual UV/OV Supply Monitor,.V ±% Tolerance 8V Supply Monitor (<±% = Powergood) POWER SUPPLY.V C BYP.μF R C 7.k OV R B LTC9- k UV 6 7 R A.k LATCH 8 GND TMR C TMR nf SYSTEM 9 TA TIMEOUT = ms POWER SUPPLY 8V R C 7.M R B 8.6k R A 7k C BYP.μF GND R Z k LTC9- TMR OV UV DIS C TMR nf R PG k TIMEOUT = 8ms POWERGOOD LED 9 TA Dual UV Supply Monitor,.V,.V, % Tolerance POWER SUPPLIES.V.V C BYP.μF R B.9k R B 9.k R A k TMR 6 V H OV LTC9-7 UV 8 V L DIS R A GND k R OV k R UV k SYSTEM 9 TA 9fa

11 PACKAGE DESCRIPTION DDB Package 8-Lead Plastic DFN (mm mm) (Reference LTC DWG # -8-7 Rev B) LTC9. ±.. ±..6 ±. ( SIDES).7 ±. PACKAGE OUTLINE. ±.. BSC. ±. ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN BAR TOP MARK (SEE NOTE 6). REF. ±. ( SIDES) NOTE:. DRAWING CONFORMS TO VERSION (WECD-) IN JEDEC PACKAGE OUTLINE M-9. DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE. ±. ( SIDES).7 ±.. R =. TYP.6 ±. ( SIDES) R =. TYP. ±.. ±. ( SIDES) BOTTOM VIEW EXPOSED PAD 8. ±.. BSC PIN R =. OR. CHAMFER (DDB8) DFN 9 REV B TS8 Package 8-Lead Plastic TSOT- (Reference LTC DWG # -8-67). MAX.6 REF.9 BSC (NOTE ). REF.8 MAX.6 REF. MIN.8 BSC..7 (NOTE ) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR.6 BSC PLCS (NOTE ). BSC DATUM A. MAX.... REF NOTE:. DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE. DIMENSIONS ARE INCLUSIVE OF PLATING.9..9 BSC (NOTE ) TS8 TSOT- 8. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR. MOLD FLASH SHALL NOT EXCEED.mm 6. JEDEC PACKAGE REFERENCE IS MO-9 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 9fa

12 LTC9 TYPICAL APPLICATION Single UV/OV Supply Monitor with.v ±% POWER SUPPLY V.V.μF Q k 7.k k.k OV LTC9- UV LATCH GND TMR nf TIMEOUT = ms SYSTEM 9 TA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC69 V Supply Monitor, Watchdog Timer and Battery Backup.6 Threshold LTC69-..V Supply Monitor, Watchdog Timer and Battery Backup.9V Threshold LTC699 V Supply Monitor and Watchdog Timer.6 Threshold LTC V Supply Monitor, Watchdog Timer and Push-Button Reset.7V/.6V Threshold LTC6/ LTC6-. Micropower Precision Triple Supply Monitor for V/.V,.V.7V,.8V, V Threshold (±.7%) and ADJ LTC6 Precision Triple Supply Monitor for PCI Applications Meets PCI t FAIL Timing Specifi cations LTC76-./ Micropower Triple Supply Monitor for.v/v,.v and ADJ Adjustable RESET and Watchdog Time-Outs LTC76- LTC78-.8/ Micropower Triple Supply Monitor with Open-Drain Reset -Lead SOT- Package LTC78-. LTC98-.8 Micropower Triple Supply Monitor with Open-Drain Reset -Lead SOT- Package LTC9 Programmable Quad Supply Monitor Adjustable RESET, -Lead MSOP and mm mm -Lead DFN Package LTC9 Programmable Quad Supply Monitor Adjustable RESET and Watchdog Timer, 6-Lead SSOP Package LTC9 Programmable Quad Supply Monitor Adjustable RESET and Tolerance, 6-Lead SSOP Package, Margining Functions LTC9 Precision Quad Supply Monitor 6-Lead TSOT- Package, Ultralow Voltage Reset LTC9 -State Programmable Precision Dual Supply Monitor Adjustable Tolerance, 8-Lead TSOT- Package LTC9 -State Programmable Precision Dual Supply Monitor Adjustable RESET and Tolerance, 8-Lead TSOT- Package LTC96 Precision Dual Supply Monitor -Selectable and Adjustable Separate Pin, RST/RST Outputs LTC97 Precision Dual Supply Monitor -Selectable and Adjustable Separate, Adjustable Reset Timer LTC98 Precision Six Supply Monitor (Four Fixed & Adjustable) 8-Lead TSOT- and DFN Packages LTC99 Prevision Dual Input UV, OV and Negative Voltage Monitor Separate Pin, Adjustable Reset Timer, 8-Lead TSOT- and DFN Packages LTC9 Dual UV/OV Voltage Monitor Separate Pin, Two Inputs, Adjustable Reset Timer, -Lead MSOP and DFN Packages LTC9 Quad UV/OV Positive/Negative Voltage Monitor Separate Pin, Four inputs, Up To Two Negative Monitors, Adjustable Reset Timer, 6-Lead TSSOP and DFN Packages LT 7 REV A PRINTED IN USA Linear Technology Corporation 6 McCarthy Blvd., Milpitas, CA 9-77 (8) -9 FAX: (8) -7 LINEAR TECHNOLOGY CORPORATION 6 9fa

LTC2935 Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds FEATURES

LTC2935 Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds FEATURES Ultra-Low Power Supervisor with Power-Fail Output, Selectable Thresholds FEATURES n 5nA Quiescent Current n ±1.5% (Max) Accuracy over Temperature n Integrated Precision Attenuators n Eight Pin-Selectable