LTC692/LTC693 Microprocessor Supervisory Circuits DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

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1 Microprocessor Supervisory Circuits FEATURES n Guaranteed Reset Assertion at = n.5ma Maximum Supply Current n Fast (5ns Maximum) Onboard Gating of RAM Chip Enable Signals n.0 Precision oltage Monitor n Power OK/Reset Time Delay: 200ms or Adjustable n Minimum External Component Count n μa Maximum Standby Current n oltage Monitor for Power-Fail or Low Battery Warning n Thermal Limiting n Performance Specifi ed Over Temperature n Superior Upgrade for MAX690 Family n SO8 and SO6 Packaging APPLICATIONS n Critical μp Power Monitoring n Intelligent Instruments n Battery-Powered Computers and Controllers n Automotive Systems DESCRIPTION The LTC 692/ provide complete power supply monitoring and battery control functions for microprocessor reset, battery backup, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the chip enable output unconditionally write-protects external memory. In addition, the output is guaranteed to remain logic low even with as low as. The LTC692/ power the active CMOS RAMs with a charge-pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC692/ provide an internal comparator with a user-defi ned threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset timeout period. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.. TYPICAL APPLICATION Output oltage vs Supply oltage IN 7. 0μF 5k 0k IN LT086-5 ADJ OUT 00μF MICROPROCESSOR, BATTERY BACKUP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS OUT LTC692 BATT PFI PFO WDI POWER TO CMOS RAM 00Ω μp μp NMI I/O LINE μp SYSTEM μp POWER 692_ TA0 OUTPUT OLTAGE () T A = 25 C EXTERNAL PULL-UP = 0μA BATT = SUPPLY OLTAGE () 692_ TA02

2 ABSOLUTE MAXIMUM RATINGS Terminal oltage to 6.0 BATT to 6.0 All Other Inputs to ( OUT 0.) Input Current mA BATT... 50mA... 20mA (Notes, 2) OUT Output Current... Short-Circuit Protected Power Dissipation mW Operating Temperature Range LTC692C/C... 0 C to 70 C LTC692I... 0 C to 85 C Storage Temperature Range C to 50 C Lead Temperature (Soldering, 0 sec) C PIN CONFIGURATION TOP IEW OUT PFI 2 N8 PACKAGE 8-LEAD PDIP TOP IEW BATT WDI PFO S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 0 C, θ JA = 0 C/W (N) T JMAX = 0 C, θ JA = 80 C/W (S) S8 PACKAGE CONDITIONS: PCB MOUNT ON FR MATERIAL, STILL AIR AT 25 C, COPPER TRACE BATT OUT BATT ON LOW LINE OSC IN OSC SEL N PACKAGE 6-LEAD PDIP 6 5 WDO CE IN 2 CE OUT WDI 0 PFO 9 PFI SW PACKAGE 6-LEAD PLASTIC SO T JMAX = 0 C, θ JA = 0 C/W S6 PACKAGE CONDITIONS: PCB MOUNT ON FR MATERIAL, STILL AIR AT 25 C, COPPER TRACE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC692CN8#PBF LTC692CN8#TRPBF LTC692CN8 8-Lead Plastic DIP 0 C to 70 C LTC692CS8#PBF LTC692CS8#TRPBF Lead Plastic SO 0 C to 70 C LTC692IS8#PBF LTC692IS8#TRPBF 692I 8-Lead Plastic SO 0 C to 85 C CN#PBF CN#TRPBF CN 6-Lead Plastic DIP 0 C to 70 C CS#PBF CS#TRPBF CS 6-Lead Plastic SO 0 C to 70 C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: 2

3 PRODUCT SELECTION GUIDE PINS THRESHOLD () WATCHDOG TIMER BATTERY BACKUP POWER-FAIL WARNING RAM WRITE- PROTECT PUSHBUTTON CONDITIONAL BATTERY BACKUP LTC X X X 6.0 X X X X LTC X X X LTC X X X X LTC X X X LTC X X X X LTC X LTC22 8.7/.62 X X LTC X X X X X X LTC X X X LTC X X X X ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25 C. = full operating range, BATT = 2.8, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Backup Switching.50 Operating oltage Range BATT 2.00 OUT Output oltage I OUT = ma 0.05 l I OUT = 50mA OUT in Battery Backup Mode I OUT = 250μA, < BATT BATT 0. BATT 0.02 Supply Current (Exclude I OUT ) I OUT 50mA ma l ma Supply Current in Battery Backup Mode = 0, BATT = μa l μa Battery Standby Current 5. > > BATT μa ( = Discharge, = Charge) l μa Battery Switchover Threshold BATT Power Up Power Down m m Battery Switchover Hysteresis 20 m BATT ON Output oltage (Note ) I SINK =.2mA 0. BATT ON Output Short-Circuit Current (Note ) BATT ON = OUT, Sink Current 5 ma BATT ON = 0, Source Current μa Reset and Watchdog Timer Reset oltage Threshold l Reset Threshold Hysteresis 0 m Reset Active Time (Note 5) OSC SEL High, = l ms ms

4 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25 C. = full operating range, BATT = 2.8, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Watchdog Timeout Period, Internal Oscillator Long Period, = sec l sec Short Period, = ms l ms Watchdog Timeout Period, External Clock (Note 6) Long Period Short Period Reset Active Time PSRR ms/ Watchdog Timeout Period PSRR, Internal OSC ms/ Minimum WDI Input Pulse Width IL = 0., IH =. l 200 ns Output oltage at = I SINK = 0μA, = 200 m and LOW LINE Output oltage (Note ) and WDO Output oltage (Note ),, WDO, LOW LINE Output Short-Circuit Current (Note ) WDI Input Threshold WDI Input Current I SINK =.6mA, =.2 I SOURCE = μa, =.5 I SINK =.6mA, = I SOURCE = μa, =.2.5 Output Source Current Output Sink Current Logic Low Logic High.5 WDI = OUT WDI = 0 l l Clock Cycles μa ma μa μa Power-Fail Detector PFI Input Threshold = l PFI Input Threshold PSRR 0. m/ PFI Input Current ±0.0 ±25 na PFO Output oltage (Note ) I SINK =.2mA I SOURCE = μa.5 0. PFO Short-Circuit Source Current (Note ) PFI = High, PFO = 0 PFI = Low, PFO = OUT μa ma PFI Comparator Response Time (Falling) Δ IN = 20m, OD = 5m 2 μs PFI Comparator Response Time (Rising) (Note ) Chip Enable Gating CE IN Threshold Δ IN = 20m, OD = 5m with 0kΩ Pull-Up IL IH μs μs 0.8 CE IN Pull-Up Current (Note 7) μa CE OUT Output oltage I SINK =.2mA 0. I SOURCE = ma I SOURCE = μa, CC = 0 OUT.50 OUT 0.05 CE Propagation Delay CE OUT Output Short-Circuit Current =, C L = 20pF Output Source Current Output Sink Current l ns ns ma ma

5 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25 C. = full operating range, BATT = 2.8, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator OSC IN Input Current (Note 7) ±2 μa OSC SEL Input Pull-Up Current (Note 7) 5 μa OSC IN Frequency Range OSC SEL = 0 l khz OSC IN Frequency with External Capacitor OSC SEL = 0, C OSC = 7pF khz Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to. Note : For military temperature range, consult the factory. Note : The output pins of BATT ON, LOW LINE, PFO, WDO, and have weak internal pull-ups of typically μa. However, external pull-up resistors may be used when higher speed is required. Note 5: The LTC692/ have minimum reset active times of 0ms (200ms typically). The reset active time of the can be adjusted (see Table 2 in Applications Information Section). Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (see Block Diagram). ariation in the timeout period is caused by phase errors which occur when the oscillator divides the external clock by 6. The resulting variation in the timeout period is 6 clocks plus one clock of jitter. Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pull-ups which pull to the supply when the input pins are fl oating. 5

6 TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT OLTAGE () OUT vs I OUT SLOPE = 5Ω = BATT = 2.8 T A = 25 C OUTPUT OLTAGE () OUT vs I OUT SLOPE = 25Ω = 0 BATT = 2.8 T A = 25 C PFI INPUT THRESHOLD () Power Failure Input Threshold vs Temperature = LOAD CURRENT (ma) LOAD CURRENT (μa) TEMPERATURE ( C) 692_ TPC0 692_ TPC02 692_ TPC0 ACTIE TIME Reset Active Time vs Temperature = OLTAGE THRESHOLD () Reset oltage Threshold vs Temperature PFO OUTPUT OLTAGE () Power-Fail Comparator Response Time PFI. PFI = 20m STEP PFO = T A = 25 C 0pF TEMPERATURE ( C) TEMPERATURE ( C) TIME (μs) _ TPC0 692_ TPC05 692_ TPC06 PFO OUTPUT OLTAGE () Power-Fail Comparator Response Time = T A = 25 C PFI. PFO 0pF PFO OUTPUT OLTAGE () Power-Fail Comparator Response Time with Pull-Up Resistor = T A = 25 C PFI. PFO 0k 0pF..29 PFI = 20m STEP..29 PFI = 20m STEP TIME (μs) TIME (μs) _ TPC07 692_ TPC08 6

7 PIN FUNCTIONS BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes low when OUT is internally connected to. The output typically sinks 5mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of OUT. BATT ON goes high when OUT is internally switched to BATT. CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor s address line and/or decoder output. See Applications Information section and Figure 5 for additional information. CE OUT : Logic Output on the Chip Enable Gating Circuit. When is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When is below the reset voltage threshold CE OUT is forced high (see Figure 5). : Ground Pin. LOW LINE: Logic Output from Comparator C. LOW LINE indicates a low line condition at the input. When falls below the reset voltage threshold (.0 typically), LOW LINE goes low. As soon as rises above the reset voltage threshold, LOW LINE returns high (see Figure ). LOW LINE goes low when drops below BATT (see Table ). OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and when OSC SEL is forced low. In this confi guration the nominal reset active time and watchdog timeout period are determined by the number of clocks or set by the formula (see Applications Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical. OSC IN selects between the.6 seconds and 00ms typical watchdog timeout periods. In both cases the timeout period immediately after a reset is.6 seconds typical. OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog timeout period. Forcing OSC SEL low allows OSC IN to be driven from an external clock signal or an external capacitor to be connected between OSC IN and. LTC692/ PFI: Power Failure Input. PFI is the noninverting input to the power-fail comparator, C. The inverting input is internally connected to a. reference. The power failure output remains high when PFI is above. and goes low when PFI is below.. Connect PFI to or OUT when C is not used. PFO: Power Failure Output from C. PFO remains high when PFI is above. and goes low when PFI is below.. When is lower than BATT, C is shut down and PFO is forced low. : Logic Output for μp Reset Control. Whenever falls below either the reset voltage threshold (.0 typically) or BATT, goes active low. After returns to, reset pulse generator forces to remain active low for a minimum of 0ms. When the watchdog timer is enabled but not serviced prior to a preset timeout period, reset pulse generator also forces to active low for a minimum of 0ms for every preset timeout period (see Figure ). The reset active time is adjustable on the. An external pushbutton reset can be used in connection with the output. See Pushbutton Reset in the Applications Information section. : is an Active High Logic Output. It is the inverse of. BATT : Backup Battery Input. When falls below BATT, auxiliary power connected to BATT is delivered to OUT through PMOS switch, M2. If backup battery or auxiliary power is not used, BATT should be connected to. : Supply Input. The pin should be bypassed with a capacitor. OUT : oltage Output for Backed-Up Memory. Bypass with a capacitor of or greater. During normal operation, OUT obtains power from through an NMOS power switch, M, which can deliver up to 50mA and has a typical on-resistance of 5Ω. When is lower than BATT, OUT is internally switched to BATT. If OUT and BATT are not used, connect OUT to. 7

8 PIN FUNCTIONS WDI: Watchdog Input. WDI is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both and WDO low. Floating WDI disables the watchdog timer. The timer resets itself with each transition of the watchdog input (see Figure ). WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog timeout period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure ). BLOCK DIAGRAM BATT M2 OUT M C2 CHARGE PUMP BATT ON. C LOW LINE CE OUT CE IN PFI C PFO OSC IN OSC SEL OSC PULSE GENERATOR WDI TRANSITION DETECTOR WATCHDOG TIMER WDO LTC692/ BD 8

9 APPLICATIONS INFORMATION Microprocessor Reset The LTC692/ use a bandgap voltage reference and a precision voltage comparator C to monitor the supply input on (see Block Diagram). When falls below the reset voltage threshold, the output is forced to active low state. The reset voltage threshold accounts for a 0% variation on, so the output becomes active low when falls below.50 (.0 typical). On power-up, the signal is held active low for a minimum of 0ms after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the. On power down, the signal remains active low even with as low as. This capability helps hold the microprocessor in stable shutdown condition. Figure shows the timing diagram of the signal. The precision voltage comparator, C, typically has 0m of hysteresis which ensures that glitches at the pin do not activate the output. Response time is typically 0μs. To help prevent mistriggering due to transient loads, pin should be bypassed with a capacitor with the leads trimmed as short as possible. The has two additional outputs: and LOW LINE. is an active high output and is the inverse of. LOW LINE is the output of the precision voltage comparator, C. When falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as rises above the reset voltage threshold. Battery Switchover The battery switchover circuit compares to the BATT input, and connects OUT to whichever is higher. When rises to 70m above BATT, the battery switchover comparator, C2, connects OUT to through a charge pumped NMOS power switch, M. When falls to 50m above BATT, C2 connects OUT to BATT through a PMOS switch, M2. C2 has typically 20m of hysteresis to prevent spurious switching when remains nearly equal to BATT. The response time of C2 is approximately 20μs. During normal operation, the LTC692/ use a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to OUT from and has a typical on-resistance of 5Ω. The OUT pin should be bypassed with a capacitor of or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from OUT, or a lower dropout ( OUT voltage differential) is desired, the should be used. This product provides BATT ON output to drive the base of the external PNP transistor (Figure 2). If higher currents are needed with the LTC692, a high current Schottky diode can be connected from the pin to the OUT pin to supply the extra current. 2 2 = OLTAGE THRESHOLD 2 = OLTAGE THRESHOLD THRESHOLD HYSTERESIS t t t = ACTIE TIME LOW LINE 692_ F0 Figure. Reset Active Time 9

10 APPLICATIONS INFORMATION ANY PNP POWER TRANSISTOR I = OUT BATT R 5 BATT ON OUT BATT 2 R OUT LTC692 BATT 692_ F02 692_ F0 Figure 2. Using BATT ON to Drive External PNP Transistor The LTC692/ are protected for safe area operation with a short-circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long periods of time, thermal shutdown turns the power switch off until the device cools down. The threshold temperature for thermal shutdown is approximately 55 C with about 0 C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the BATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. The LTC692/ use a charge-pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by the BATT pin is strictly junction leakage. A 25Ω PMOS switch connects the BATT input to OUT in battery backup mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. The supply current in battery backup mode is μa maximum. The operating voltage at the BATT pin ranges from 2.0 to.0. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short-term Figure. Charging External Battery Through OUT memory backup instead of a battery. The charging resistor for the rechargeable batteries should be connected to OUT since this eliminates the discharge path that exists when the resistor is connected to (Figure ). Replacing the Backup Battery When changing the backup battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the BATT pin. The oscillation cycle is as follows: When BATT reaches within 50m of, the LTC692/ switch to battery backup. OUT pulls BATT low and the devices go back to normal operation. The leakage current then charges up the BATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from BATT to will hold the pin low while changing the battery. For example, the battery standby current is μa maximum over temperature and the external resistor required to hold BATT below is: R 50m A μ With =.2, a.9m resistor will work. With a battery, this resistor will draw only 0.77μA from the battery, which is negligible in most cases. 0

11 APPLICATIONS INFORMATION If battery connections are made through long wires, a 0Ω to 00Ω series resistor and a capacitor are recommended to prevent any overshoot beyond due to the lead inductance (Figure ). Table shows the state of each pin during battery backup. When the battery switchover section is not used, connect BATT to and OUT to. 0Ω.9M BATT LTC _ F0 Figure. 0Ω/ Combination Eliminates Inductive Overshoot and Prevents Spurious Resets During Battery Replacement Memory Protection The includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when is at an invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When is, CE OUT follows CE IN with a typical propagation delay of 20ns. When falls below the reset voltage threshold or BATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of Table. Input and Output Status in Battery Backup Mode SIGNAL OUT BATT BATT ON PFI PFO LOW LINE WDI WDO CE IN CE OUT OSC IN OSC SEL STATUS C2 monitors for active switchover OUT is connected to BATT through an internal PMOS switch The supply current is μa maximum Logic high. The open-circuit output voltage is equal to OUT Power failure input is ignored Logic low Logic low Logic high. The open-circuit output voltage is equal to OUT Logic low Watchdog input is ignored Logic high. The open-circuit output voltage is equal to OUT Chip Enable input is ignored Logic high. The open-circuit output voltage is equal to OUT OSC IN is ignored OSC SEL is ignored battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NORAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor s address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. Memory protection can also be achieved with the LTC692 by using as shown in Figure 7. 2 = OLTAGE THRESHOLD 2 = OLTAGE THRESHOLD THRESHOLD HYSTERESIS CE IN CE OUT OUT = BATT OUT = BATT 692_ F05 Figure 5. Timing Diagram for CE IN and CE OUT

12 APPLICATIONS INFORMATION OUT CE OUT BATT CE IN 0μF 20ns PROPAGATION DELAY FROM DECODER TO μp 6252 RAM CS 692_ F06 Figure 6. A Typical Nonvolatile CMOS RAM Application OUT LTC692 BATT 0μF CS 6228 RAM CS CS2 692_ F07 Figure 7. Write-Protect for RAM with the LTC692 Power-Fail Warning The LTC692/ generate a power failure output (PFO) for early warning of failure in the microprocessor s power supply. This is accomplished by comparing the power failure input (PFI) with an internal. reference. PFO goes low when the voltage at the PFI pin is less than.. Typically PFI is driven by an external voltage divider (R and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below., several milliseconds before the supply falls below the maximum reset voltage threshold of.50. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and or. The power-fail comparator, C, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R sinks current from the summing junction at the PFI pin. =. R R2 H R R When PFO output is high, the series combination of R and R source current into the PFI summing junction.. R (.)R L = R2.(R R) Assuming R << R, R HYSTERESIS = R 2

13 APPLICATIONS INFORMATION LTC692/ IN 7. 0μF R 5k R2 0k LT086-5 IN OUT ADJ 00μF R 00k R 0k TO μp LTC692 PFO PFI 692_ F08 Figure 8. Monitoring Unregulated DC Supply with the LTC692/LT69 Power-Fail Comparator IN 6. 0μF LT086-5 IN OUT ADJ 0μF R R 27k 0k R 2.7M R2 8.2k TO μp PFO PFI LTC _ F09 R5.k Figure 9. Monitoring Regulated DC Supply with the LTC692/LT69 Power-Fail Comparator Example : The circuit in Figure 8 demonstrates the use of the power-fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input IN is 00m/ms and the total time to execute a shutdown procedure is 8ms. Also, the noise of IN is 200m. With these assumptions in mind, we can reasonably set L = 7.2 which is.2 greater than the sum of maximum reset voltage threshold and the dropout voltage of LT (..) and HYSTERESIS = 850m. R HYSTERESIS = 850m R = R 5.88 R Choose R = 00k and R = 5k. Also select R = 0k which is much smaller than R. 7.2 =. 5 k (.)5k R2. ( 0k) R2 = 0.k, Choose nearest 5% resistor 0k and recalculate L, (.)5 L =. 5k k 0k.(0 k) = 72. =. 5k 5k H 0k 00k = 8.5 ( ) = 0.7ms 00m/ms HYSTERESIS = = 8m The 0.7ms allows enough time to execute shutdown procedure for microprocessor and 8m of hysteresis would prevent PFO from going low due to the noise of IN.

14 APPLICATIONS INFORMATION Example 2: The circuit in Figure 9 can be used to measure the regulated supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the supply reaches the desired level (e.g.,.6). Monitoring the Status of the Battery C can also monitor the status of the memory backup battery (Figure 0). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. R M R2 M R L 20K BATT PFI OPTIONAL TEST LOAD CE OUT PFO CE IN 692_ F0 LOW-BATTERY SIGNAL TO μp I/O PIN I/O PIN Watchdog Timer The LTC692/ provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the watchdog input (WDI) within a selected timeout period, is forced to active low for a minimum of 0ms. The reset active time is adjustable on the. Since many systems cannot service the watchdog timer immediately after a reset, the has longer timeout period (.0 second minimum) right after a reset is issued. The normal timeout period (70ms minimum) becomes effective following the first transition of WDI after is inactive. The watchdog timeout period is fixed at a.0 second minimum on the LTC692. Figure shows the timing diagram of watchdog timeout period and reset active time. The watchdog timeout period is restarted as soon as is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to timeout, the watchdog timer is reset and begins to timeout again. To ensure the watchdog timer does not timeout, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum timeout period. If the input to the WDI pin remains either high or low, reset pulses will be issued every.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when falls below the reset voltage threshold or BATT. Figure 0. Backup Battery Monitor with Optional Test Load = WDI WDO t = ACTIE TIME t 2 = NORMAL WATCHDOG TIME-OUT PERIOD t = WATCHDOG TIME-OUT PERIOD IMMEDIATELY AFTER A t 2 t t t 692_ F Figure. Watchdog Timeout Period and Reset Active Time

15 APPLICATIONS INFORMATION The provides an additional output (watchdog output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when falls below the reset voltage threshold or BATT. The has two additional pins OSC SEL and OSC IN, which allow reset active time and watchdog timeout period to be adjusted per Table 2. Several confi gurations are shown in Figure 2. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog timeout period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 0ms minimum. OSC IN selects between the second and 70ms minimum normal watchdog timeout periods. In both cases, the timeout period immediately after a reset is at least second. EXTERNAL CLOCK EXTERNAL OSCILLATOR OSC SEL 8 OSC SEL 8 OSC IN 7 OSC IN 7 INTERNAL OSCILLATOR.6 SECOND WATCHDOG 8 FLOATING OSC SEL OR HIGH INTERNAL OSCILLATOR 00ms WATCHDOG OSC SEL 8 FLOATING OR HIGH 7 FLOATING OSC IN OR HIGH OSC IN 7 692_ F2 Figure 2. Oscillator Confi gurations Table 2. Reset Active Time and Watchdog Timeout Selections WATCHDOG TIMEOUT PERIOD ACTIE TIME IMMEDIATELY AFTER OSC SEL OSC IN NORMAL (SHORT PERIOD) (LONG PERIOD) Low External Clock Input 02 clks 096 clks 208 clks Low External Capacitor* 00ms 7pF C.6 sec 7pF C 800ms 7pF C Floating or High Low 00ms.6 sec 200ms Floating or High Floating or High.6 sec.6 sec 200ms *The nominal internal frequency is 0.2kHz. The nominal oscillator frequency with external capacitor is f OSC (Hz) = 8,000 C (pf) 5

16 APPLICATIONS INFORMATION Pushbutton Reset The LTC692/ do not provide a logic input for direct connection to a pushbutton. However, a pushbutton in series with a 00Ω resistor connected to the output pin (Figure ) provides an alternative for manual reset. Connecting a capacitor to the pin debounces the pushbutton input. The 00Ω resistor in series with the pushbutton is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the pins of the MPU and LTC692/LT69 below ground. LTC692 00Ω Figure. The External Pushbutton Reset MPU (e.g. 6805) 692_ F TYPICAL APPLICATIONS Capacitor Backup with 7HC06 Switch Write-Protect for Additional RAMs R 0k R2 0k 0 2 7HC μF OUT BATT LOW LINE OUT CE OUT BATT CE IN LOW LINE 0μF 20ns PROPAGATION DELAY CS A 6252 RAM A CS 6228 RAM B 692_ TA0 CS B CS CS RAM C CS C CS CS 2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs 692_ TA0 6

17 PACKAGE DESCRIPTION N8 Package 8-Lead PDIP (Narrow.00 Inch) (Reference LTC DWG # ) ( ) (..65).0 ±.005 (.02 ± 0.27).00* (0.60) MAX ( ) ( ).065 (.65) TYP.00 (2.5) BSC NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.00 INCH (0.25mm).20 (.08) MIN.08 ±.00 (0.57 ± 0.076).020 (0.508) MIN.255 ±.05* (6.77 ± 0.8) 2 N8 002 S8 Package 8-Lead Plastic Small Outline (Narrow.50 Inch) (Reference LTC DWG # ).050 BSC.05 ± ( ) NOTE MIN.60 ± ( ) ( ) NOTE.00 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT ( ) ( ) 0 8 TYP (.6.752) ( ) ( ) NOTE: INCHES. DIMENSIONS IN (MILLIMETERS).0.09 ( ) TYP 2. DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.006" (0.5mm).050 (.270) BSC SO8 00 7

18 PACKAGE DESCRIPTION N Package 6-Lead PDIP (Narrow.00 Inch) (Reference LTC DWG # ) ( ).0 ±.005 (.02 ± 0.27) (..65) * (9.558) MAX ( ) ( ).020 (0.508) MIN.20 (.08) MIN.00 (2.5) BSC NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.00 INCH (0.25mm).065 (.65) TYP.08 ±.00 (0.57 ± 0.076) N ±.05* (6.77 ± 0.8) SW Package 6-Lead Plastic Small Outline (Wide.00 Inch) (Reference LTC DWG # ).00 ±.005 TYP N.050 BSC.05 ± ( ) NOTE N.20 MIN.25 ±.005 NOTE.9.9 ( ) 2 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT (0.27) RAD MIN ( ) NOTE ( ) 0 8 TYP.09.0 ( ) (0.90.) (.270) ( ) NOTE BSC ( ) ( ) TYP NOTE: INCHES. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE. PIN IDENT, NOTCH ON TOP AND CAITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.006" (0.5mm) ( ) S6 (WIDE)

19 REISION HISTORY (Revision history begins at Rev B) RE DATE DESCRIPTION PAGE NUMBER B 0/0 Revised Features section to remove UL Recognized and UL logo. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 9

20 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC690 Supply Monitor, Watchdog Timer and Battery Backup.6 Threshold LTC69-.. Supply Monitor, Watchdog Timer and Battery Backup 2.9 Threshold LTC22 Supply Monitor, Watchdog Timer and Pushbutton Reset.7/.62 Threshold LTC26 Micropower Precision Triple Supply Monitor.72,.8, Threshold (±0.75%) LTC56 Precision Triple Supply Monitor for PCI Applications Meets PCI t FALL Timing Specifi cations LTC726 Micropower Triple Supply Monitor for 2./,. and ADJ Adjustable and Watchdog Timeouts LTC727 Micropower Triple Supply Monitor with Open-Drain Reset Individual Monitor Outputs in MSOP LTC728 Micropower Triple Supply Monitor with Open-Drain Reset 5-Lead SOT-2 Package LTC2900 Programmable Quad Supply Monitor Adjustable 0-Lead MSOP and mm mm 0-Lead DFN LTC290 Programmable Quad Supply Monitor Adjustable and Watchdog Timer, 6-Lead SSOP Package LTC2902 Programmable Quad Supply Monitor Adjustable and Tolerance, 6-Lead SSOP Package, Margining LTC290 Precision Quad Supply Monitor 6-Lead SOT-2 Package, Ultralow oltage Reset LTC290 -State Programmable Precision Dual Supply Monitor Adjustable Tolerance, 8-Lead SOT-2 Package LTC2905 -State Programmable Precision Dual Supply Monitor Adjustable and Tolerance, 8-Lead SOT-2 Package LTC2906 Precision Dual Supply Monitor Selectable and Adjustable Separate Pin, RST/RST Outputs LTC2907 Precision Dual Supply Monitor Selectable and Adjustable Separate Pin, Adjustable Reset Timer LTC2908 Precision Six Supply Monitor (Four Fixed and 2 Adjustable) 8-Lead SOT-2 and DDB Packages LTC2909 Precision Triple/Dual Input U, O 2 ADJ Inputs LTC290 Octal Positive/Negative oltage Monitor 6-Lead SSOP and 5mm mm DFN Packages LTC292 Single U/O oltage Monitor, Adjustable U and O 8-Lead TSOT and mm 2mm DFN Packages LTC29 Dual U/O oltage Monitor 0-Lead MSOP and mm mm DFN Packages LTC29 Qual U/O Positive/Negative oltage Monitor 6-Lead SSOP and 5mm mm DFN Packages LTC295 Single Supervisor with 27 Selectable Thresholds 0-Lead MSOP and mm 2mm DFN-0 Packages LTC296 Single Supervisor with 9 Selectable Thresholds Manual Reset, 0-Lead MSOP and mm 2mm DFN-0 Packages 20 LT 00 RE B PRINTED IN USA Linear Technology Corporation 60 McCarthy Blvd., Milpitas, CA (08) FAX: (08) LINEAR TECHNOLOGY CORPORATION 99