MAX691A/MAX693A/ MAX800L/MAX800M. Microprocessor Supervisory Circuits. Features. General Description. Applications. Typical Operating Circuit

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1 Click here for production status of specific part numbers. // General Description The // microprocessor (μp) supervisory circuits are pin-compatible upgrades to the MAX69, MAX693, and MAX695. They improve performance with 30μA supply current, 200ms typ reset active delay on power-up, and 6ns chip-enable propagation delay. Features include write protection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a output that is valid with CC down to. The / have a 4.65 typical reset-threshold voltage, and the /s reset threshold is 4.4 typical. The guarantee power-fail accuracies to ±2%. Applications Computers Controllers Intelligent Instruments Critical μp Power Monitoring Typical Operating Circuit + 5 REGULATOR *MaxCap N F* NO CONNECTION 3 CC BATT 5 BATT ON OUT 2 CE OUT 9 3 PFI CE IN 4 WDI 7 OSC IN 0 PFO 5 LOW LINE WDO 6 4 SYSTEM STATUS INDICATORS 0.µF ADDRESS DECODE AUDIBLE ALARM CMOS RAM MaxCap is a registered trademark of Kanthal Globar, Inc. 2 A0-A5 I/O µp NMI Features 200ms Power-OK/Reset Timeout Period μa Standby Current, 30μA Operating Current On-Board Gating of Chip-Enable Signals, 0ns max Delay MaxCap or SuperCap Compatible Guaranteed Assertion to CC = + oltage Monitor for Power-Fail or Low-Battery Warning Power-Fail Accuracy Guaranteed to ±2% (/M) Available in 6-Pin Narrow SO, Plastic DIP, and TSSOP Packages Ordering Information PART TEMP RANGE PIN- PACKAGE CUE -0 C to +70 C 6 TSSOP CSE -0 C to +70 C 6 Narrow SO CWE -0 C to +70 C 6 Wide SO CPE -0 C to +70 C 6 Plastic DIP C/D -0 C to +70 C Dice* EUE -0 C to +70 C 6 TSSOP ESE -40 C to +5 C 6 Narrow SO EWE -40 C to +5 C 6 Wide SO EPE -40 C to +5 C 6 Plastic DIP Ordering Information continued at end of data sheet. *Dice are specified at T A = +25 C, DC parameters only. Devices in PDIP, SO, and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. Pin Configuration TOP IEW BATT OUT CC BATT ON LOW LINE OSC IN DIP/SO/TSSOP WDO 3 CE IN 2 CE OUT WDI 0 PFO 9 PFI ; Rev 4; 4/

2 Absolute Maximum Ratings Terminal oltage (with respect to ) CC to +6 BATT to +6 All Other Inputs to ( OUT + 0.3) Input Current CC Peak...0A CC Continuous...250mA BATT Peak...250mA BATT Continuous...25mA, BATT ON...00mA All Other Outputs...25mA Continuous Power Dissipation (T A = +70 C) TSSOP (derate 6.70mW/ C above +70 C)...533mW Narrow SO (derate.70mw/ C above +70 C)...696mW Wide SO (derate 9.52mW/ C above +70 C)...762mW Plastic DIP (derate 0.53mW/ C above +70 C)...42mW CERDIP (derate 0.00mW/ C above +70 C)...00mW Operating Temperature Ranges MAX69_AC /MAX00_C...0 C to +70 C MAX69_AE /MAX00_E C to +5 C MAX69_AMJE C to +25 C Storage Temperature Range C to +60 C Lead Temperature (soldering, 0s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (, : CC = to +5.5;, : CC = +4.5 to +5.5; BATT = 2., T A = T MIN to T MAX, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Operating oltage Range, CC, BATT (Note ) OUT Output CC = 4.5 CC -to- OUT On-Resistance CC = 4.5 OUT in Battery-Backup Mode BATT-to- OUT On-Resistance Supply Current in Normal Operating Mode (excludes I OUT ) Supply Current in Battery- Backup Mode (excludes I OUT ) (Note 2) BATT Standby Current (Note 3) Battery Switchover Threshold I OUT = 25mA CC CC I OUT = 250mA I OUT = 20mA MAX69_AC CC CC MAX69_AE, MAX00_C/E CC MAX69_A/M CC MAX69_AC/AE, MAX00_C/E CC CC CC MAX69_AC, MAX00_C 0..2 MAX69_AE, MAX00_E 0..4 MAX69_A/M 0..6 BATT = 4.5, I OUT = 20mA BATT BATT = 2., I OUT = 0mA BATT BATT = 2.0, I OUT = 5mA BATT BATT = BATT = BATT = CC > BATT µa CC < BATT -.2, BATT = 2. BATT CC T A = +25 C 0.04 T A = T MIN + T MIN 5 T A = +25 C T A = T MIN + T MIN Power-up BATT Power-down BATT Ω Ω µa µa Maxim Integrated 2

3 Electrical Characteristics (continued) (, : CC = to +5.5;, : CC = +4.5 to +5.5; BATT = 2., T A = T MIN to T MAX, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Switchover Hysteresis 60 m BATT ON Output Low oltage BATT ON Output Short-Circuit Current AND WATCHDOG TIMER Reset Threshold oltage I SINK = 3.2mA I SINK = 25mA Sink current ma Source current 5 00 µa, , , T A = +25 C, CC falling , T A = +25 C, CC falling Reset Threshold Hysteresis 5 m CC to Delay Power-down 0 µs LOW LINE-to- Delay 00 ns Reset Active Timeout Period, Internal Oscillator Reset Active Timeout Period, External Clock (Note 4) Watchdog Timeout Period, Internal Oscillator Watchdog Timeout Period, External Clock (Note 4) Minimum Watchdog Input Pulse Width Output oltage Output Short-Circuit Current Output oltage Low (Note 5) LOW LINE Output oltage LOW LINE Output Short-Circuit Current WDO Output oltage WDO Output Short-Circuit Current WDI Threshold oltage (Note 6) WDI Input Current Power-up ms Power-up 204 Clock Cycles Long period sec Short period ms Long period 4096 Clock Short period 024 Cycles IL = 0., IH = 0.75 x CC 00 ns I SINK = 50μA, CC =, BATT = 0, CC falling I SINK = 3.2mA, CC = I SOURCE =.6mA, CC = Output source current 7 20 ma I SINK = 3.2mA I SINK = 3.2mA, CC = I SOURCE = μa, CC = Output source current 5 00 µa I SINK = 3.2mA 0.4 I SOURCE = 500μA, CC = Output source current 3 0 ma IH 0.75 x CC IL 0. WDI = WDI = OUT µa Maxim Integrated 3

4 Electrical Characteristics (continued) (, : CC = to +5.5;, : CC = +4.5 to +5.5; BATT = 2., T A = T MIN to T MAX, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS POWER-FAIL COMPARATOR PFI Input Threshold MAX69_AC/AE/AM, CC = MAX00_C/E, CC = PFI Leakage Current ±0.0 ±25 na PFO Output oltage PFO Output Short-Circuit Current PFI-to-PFO Delay CHIP-ENABLE GATING I SINK = 3.2mA 0.4 I SOURCE = μa, CC = Output source current 5 00 µa IN = -20m, OD = 5m 25 IN = 20m, OD = 5m 60 CE IN Leakage Current Disable mode ±0.005 ± μa CE IN-to- CE OUT Resistance (Note 7) CE OUT Short-Circuit Current (Reset Active) CE IN-to- CE OUT Propagation Delay (Note ) CE OUT Output-oltage High (Reset Active) Enable mode Ω Disable mode, CE OUT = ma 50Ω source impedance driver, C LOAD = 50pF 6 0 ns CC = 5, I OUT = -00μA 3.5 CC = 0, BATT = 2., I OUT = μa 2.7 -to-ce OUT Delay Power-down 2 µs INTERNAL OSCILLATOR OSC IN Leakage Current = ±5 µa OSC IN Input Pullup Current = OUT or floating, OSC IN = μa Input Pullup Current = μa OSC IN Frequency Range = 0 50 khz OSC IN External Oscillator OUT - OUT - IH Threshold oltage IL OSC IN Frequency with External Capacitor = 0, COSC = 47pF 00 khz Note : Either CC or BATT can go to 0, if the other is greater than 2.0. Note 2: The supply current drawn by the / from the battery excluding I OUT typically goes to 0μA when (BATT - ) < CC < BATT. In most applications, this is a brief period as CC falls through this region. Note 3: + = battery-discharging current, -- = battery-charging current. Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. Note 5: is an open-drain output and sinks current only. Note 6: WDI is internally connected to a voltage divider between OUT and. If unconnected, WDI is driven to.6 (typ), disabling the watchdog function. Note 7: The chip-enable resistance is tested with CC = for the / and CC = +4.5 for the /. CE IN = CE OUT = CC /2. Note : The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. µs Maxim Integrated 4

5 Typical Operating Characteristics (T A = +25 C, unless otherwise noted.) CC SUPPLY CURRENT (µa) CC SUPPLY CURRENT (NORMAL OPERATING MODE) CC = 5 BATT = 2. PFI, CE IN = 0 toc0 BATTERY SUPPLY CURRENT (µa) BATTERY SUPPLY CURRENT (BATTERY-BACKUP MODE) CC = 5 BATT = 2. NO LOAD TOC-02 CE ON-RESISTANCE (Ω) CHIP-ENABLE ON-RESISTANCE CC = 4.75 BATT = 2. CE IN = CC /2 toc BATT-to-OUT ON-RESISTANCE (Ω) BATT to OUT ON-RESISTANCE BATT = 2.0 BATT = 2. BATT = 4.5 CC = toc04 CC-to-OUT ON-RESISTANCE (Ω) CC to OUT ON-RESISTANCE CC = 5, BATT = toc05 PFI THRESHOLD () PFI THRESHOLD 0.25 CC = +5, BATT = 0 NO LOAD ON PFO toc06 THRESHOLD () BATT = 2. THRESHOLD toc07 OUTPUT RESISTANCE (Ω) OUTPUT RESISTANCE CC = 5, BATT = 2. SOURCING CURRENT CC = 0, BATT = 2. SINKING CURRENT toc0 DELAY (ms) DELAY CC = 0 TO 5 STEP BATT = 2. toc Maxim Integrated 5

6 Typical Operating Characteristics (continued) (T A = +25 C, unless otherwise noted.) IBATT (µa) BATTERY CURRENT vs. INPUT SUPPLY OLTAGE BATT = 2. I OUT = 0A CC () toc0 WATCHDOG AND TIMEOUT PERIOD (sec) WATCHDOG AND TIMEOUT PERIOD vs. OSC IN TIMING CAPACITOR (COSC) 00 CC = 5 LONG WATCHDOG BATT = 2. TIMEOUT PERIOD 0 ACTIE TIMEOUT PERIOD SHORT WATCHDOG TIMEOUT PERIOD COSC (pf) toc PROPAGATION DELAY (ns) CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE CC = 5 CE IN = 0 TO 5 DRIER SOURCE C LOAD (pf) toc2 CC TO OUT (m) CC TO OUT vs. OUTPUT CURRENT (NORMAL OPERATING MODE) CC = 4.5 BATT = 0 SLOPE = 0.Ω toc3 BATT to OUT (m) BATT TO OUT vs. OUTPUT CURRENT (BATTERY-BACKUP MODE) CC = 0 BATT = 4.5 SLOPE = Ω toc4 5 CC THRESHOLD HI LOW LINE LO HI LO HI 0ms 00ns CC TO LOW LINE AND CE OUT DELAY toc I OUT (ma) 0 00 I OUT (ma) CE OUT LO 2µs Maxim Integrated 6

7 Pin Description PIN NAME FUNCTION BATT Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to. 2 OUT to CC. When CC falls below BATT and is below the reset threshold, OUT connects to BATT. Connect Output Supply oltage. When CC is greater than BATT and above the reset threshold, OUT connects a 0.µF capacitor from OUT to. Connect OUT to CC if no backup battery is used. 3 CC Input Supply oltage, 5 Input. 4 Ground. 0 reference for all signals. 5 BATT ON Battery-On Output. When OUT switches to BATT, BATT ON goes high. When OUT switches to CC, BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for OUT current require- ments greater than 250mA. 6 LOW LINE LOW LINE output goes low when CC falls below the reset threshold. It returns high as soon as CC rises above the reset threshold. 7 OSC IN 9 PFI 0 PFO WDI External Oscillator Input. When is unconnected or driven high, a 0µA pull-up connects from OUT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3). Oscillator Select. When is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When is low, the external oscillator input (OSC IN) is enabled (Table ). has a 0µA internal pull-up. Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than.25, PFO goes low. When PFI is not used, connect PFI to or OUT. Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than.25. This is an uncommitted comparator, and has no effect on any other internal circuitry. Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time- out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran- sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between OUT and, which sets it to mid-supply when left unconnected. 2 CE OUT Chip-Enable Output. CE OUT goes low only when CE IN is low and CC is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 5µs or until CE IN goes high, whichever occurs first. 3 CE IN Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to or OUT. 4 WDO Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. 5 Detailed Description Output goes low whenever CC falls below the reset threshold. will remain low typically for 200ms after CC crosses the reset threshold on power-up. 6 is an active-high output. It is open drain, and the inverse of. and Outputs The // s and outputs ensure that the μp (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors during power-down or brownout conditions. The output is active low, and typically sinks 3.2mA at 0. saturation voltage in its active state. When deasserted, sources.6ma at typically OUT output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.. When no backup battery is used, output is guaranteed to be valid down to CC =, and an external 0kΩ pulldown resistor on insures that it will be valid with CC down to (Figure ). As CC goes below, the gate drive to the output switch reduces accordingly, increasing the R DS(ON) and the saturation voltage. The 0kΩ pulldown resistor insures the parallel combination of switch plus resistor is around 0kΩ and the output saturation voltage is below 0.4 while sinking 40μA. When using a 0kΩ external pulldown resistor, the high state for output with CC = 4.75 will be 4.5 typical. Maxim Integrated 7

8 WDI 5 TO µp WDO kω t 2 t t t 3 t = TIMEOUT PERIOD t 2 = NORMAL WATCHDOG TIMEOUT PERIOD t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER Figure. Adding an external pulldown resistor ensures is valid with CC down to. Figure 2. Watchdog Timeout Period and Reset Active Time For battery voltages 2 connected to BATT, and remain valid for CC from 0 to 5.5. and are asserted when CC falls below the reset threshold (4.65 for the /, 4.4 for the /) and remain asserted for 200ms typ after CC rises above the reset threshold on power-up (Figure 5). The devices batteryswitchover comparator does not affect reset assertion. However, both reset outputs are asserted in batterybackup mode since CC must be below the reset threshold to enter this mode. Watchdog Function The watchdog monitors μp activity via the Watchdog Input (WDI). If the μp becomes inactive, and are asserted. To use the watchdog function, connect WDI to a bus line or μp I/O line. If WDI remains high or low for longer than the watchdog timeout period (.6s nominal), WDO,, and are asserted (see and Outputs section, and the Watchdog Output discussion on this page). Watchdog Input A change of state (high to low, low to high, or a minimum 00ns pulse) at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is.6s. To disable the watchdog function, leave WDI floating. An internal resistor network (00kΩ equivalent impedance at WDI) biases WDI to approximately.6. Internal comparators detect this level and disable the watchdog timer. When CC is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance. Watchdog Output The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when CC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, and are asserted for the reset timeout period (200ms typical). WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely, and will generate 200ms pulses every.6s. WDO has a 2 x TTL output characteristic. Selecting an Alternative Watchdog and Reset Timeout Period The and OSC IN inputs control the watchdog and reset timeout periods. Floating and OSC IN or tying them both to OUT selects the nominal.6s watchdog timeout period and 200ms reset timeout period. Connecting OSC IN to and floating or connecting to OUT selects the 00ms normal watchdog timeout delay and.6s delay immediately after reset. The reset timeout delay remains 200ms (Figure 2). Select alternative timeout periods by connecting to and connecting a capacitor between OSC IN and, or by externally driving OSC IN (Table and Figure 3). OSC IN is internally connected to a ±00nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watch- Maxim Integrated

9 Table. Reset Pulse Width and Watchdog Timeout Selections OSC IN NORMAL WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER TIMEOUT PERIOD Low External Clock Input 024 clks 4096 clks 204 clks Low External Capacitor (600/47pF x C)ms (2.4/47pF x C)sec (200/47pF x C)ms Floating Low 00ms.6s 200ms Floating Floating.6s.6s 200ms 50kHz N.C. N.C. Figure 3. Oscillator Circuits 7 EXTERNAL CLOCK OSC IN INTERNAL OSCILLATOR.6s WATCHDOG 7 OSC IN OSC IN dog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications Information section). Chip-Enable Signal Gating The // provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. All these parts use a series transmission gate from CE IN to CE OUT (Figure 4). The 0ns max CE propagation delay from CE IN to CE OUT enables the parts to be used with most μps. Chip-Enable Input The Chip-Enable Input (CE IN) is high impedance (disabled mode) while and are asserted. During a power-down sequence where CC falls below the reset threshold or a watchdog fault, CE IN assumes a high-impedance state when the voltage at CE IN goes N.C. 7 7 EXTERNAL OSCILLATOR INTERNAL OSCILLATOR 00ms WATCHDOG OSC IN high or 5μs after reset is asserted, whichever occurs first (Figure 5). During a power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset timeout period. In the high-impedance mode, the leakage currents into this terminal are ±μa max over temperature. In the lowimpedance mode, the impedance of CE IN appears as a 75Ω resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on the Chip-Enable Output (CE OUT) (see Chip-Enable Propagation Delay vs. CE OUT Load Capacitance in the Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point of CE IN to the 50% point of CE OUT using a 50Ω driver and 50pF of load capacitance (Figure 6). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low outputimpedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75Ω in series with the source driving CE IN. In the disabled mode, the 75Ω transmission gate is off and CE OUT is actively pulled to OUT. This source turns off when the transmission gate is enabled. LOW LINE Output LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2mA at 0.. For normal operation ( CC above the LOW LINE threshold), LOW LINE is pulled to OUT. Power-Fail Comparator The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC. Common uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating Circuit). Maxim Integrated 9

10 5 BATT ON 4.65* 6 LOW LINE CC 3 2 OUT BATT CE IN OSC IN 3 7 TIMEBASE FOR AND WATCHDOG CHIP-ENABLE OUTPUT CONTROL GENERATOR CE OUT WDI PFI 9 WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER 4 0 WDO PFO.25 * 4.4 FOR THE / 4 Figure 4. // Block Diagram 5.0 CC THRESHOLD 0 CE IN CE OUT 5µs 00µs 00µs LOGIC LEELS SHOWN ARE FROM 0 TO 5. Figure 5. Reset and Chip-Enable Timing Maxim Integrated 0

11 BATT CE IN CC CE OUT 2.0 to 5.5 BATT PFI CC PFO LOW BATT 50Ω OUTPUT IMPEDANCE C LOAD Figure 6. CE Propagation Delay Test Circuit Table 2. Input and Output Status in Battery-Backup Mode PIN NAME STATUS BATT Supply current is µa max. 2 3 OUT CC OUT is connected to BATT through an internal PMOS switch. Battery switchover comparator monitors CC for active switchover. 4 0, 0 reference for all signals. 5 BATT ON Logic high. The open-circuit output is equal to OUT. 6 LOWLINE Logic low* 7 OSC IN OSC IN is ignored. is ignored. 9 PFI 0 PFO The power-fail comparator remains active in the battery-backup mode for CC BATT -.2 typ. The power-fail comparator remains active in the battery-backup mode for CC BATT -.2 typ. Below this volt- age, PFO is forced low. WDI Watchdog is ignored. 2 CE OUT 3 CE IN High impedance 4 WDO Logic high. The open-circuit voltage is equal to OUT. Logic high. The open-circuit voltage is equal to OUT. 5 Logic low* 6 High impedance* * CC must be below the reset threshold to enter battery-backup mode. Figure 7. Low-Battery Indicator Power-Fail Input Power-Fail Input (PFI) is the input to the power-fail comparator. It has a guaranteed input leakage of ±25nA max over temperature. The typical comparator delay is 25μs from IL to OL (power failing), and 60μs from IH to OH (power being restored). If PFI is not used, connect it to ground. Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below.25. It typically sinks 3.2mA with a saturation voltage of 0.. With PFI above.25, PFO is actively pulled to OUT. Battery-Backup Mode Two conditions are required to switch to battery-backup mode: ) CC must be below the reset threshold, and 2) CC must be below BATT. Table 2 lists the status of the inputs and outputs in battery-backup mode. Battery-On Output The Battery-On (BATT ON) output indicates the status of the internal CC /battery-switchover comparator, which controls the internal CC and BATT switches. For CC greater than BATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0. saturation voltage. In battery-backup mode, this terminal sources approximately 0μA from OUT. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see Typical Operating Circuit). Input Supply oltage The Input Supply oltage ( CC ) should be a regulated 5. CC connects to OUT via a parallel diode and a large PMOS switch. The switch carries the entire cur-rent Maxim Integrated

12 load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than Ω each. The maximum continuous current is 250mA, but power-on transients may reach a maximum of A. Battery-Backup Input The Battery-Backup Input (BATT) is similar to the CC input except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 0Ω. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than μa over temperature and supply voltage (Figure ). Output Supply oltage The Output Supply oltage ( OUT ) pin is internally connected to the substrate of the IC and supplies current to the external system and internal circuitry. All opencircuit outputs will, for example, assume the OUT voltage in their high states rather than the CC voltage. At the maximum source current of 250mA, OUT will typically be 200m below CC. Decouple this terminal with a 0.μF capacitor. Applications Information The // are not short-circuit protected. Shorting OUT to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device. All open-circuit outputs swing between OUT and rather than CC and. If long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chip s protection diodes. There are three distinct modes of operation: ) Normal operating mode with all circuitry powered up. Typical supply current from CC is 35μA while only leakage currents flow from the battery. 2) Battery-backup mode where CC is typically within 0.7 below BATT. All circuitry is powered up and the supply current from the battery is typically less than 60μA. 3) Battery-backup mode where CC is less than BATT by at least 0.7. BATT supply current is μa max. Using SuperCap or MaxCap with the // BATT has the same operating voltage range as CC, and the battery switchover threshold voltages are typically ±30m centered at BATT, allowing use of a SuperCap and a simple charging circuit as a backup source (Figure 9). If CC is above the reset threshold and BATT is 0.5 above CC, current flows to OUT and CC from BATT until the voltage at BATT is less than 0.5 above CC. For example, with a SuperCap connected to BATT and through a diode to CC, if CC quickly changes from 5.4 to 4.9, the capacitor discharges through OUT and CC until BATT reaches 5. typ. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to CC. Also, if CC and BATT start from 0. above the reset thresh CC BATT N44 CC OUT 0.µF 0.47F* BATT OUT 2 4 * MaxCap Figure. CC and BATT to OUT Switch Figure 9. SuperCap or MaxCap on BATT Maxim Integrated 2

13 CE IN OUT Rp* CE OUT CE CE RAM R IN +5 C* PFI CC CE CE CE CE RAM 2 RAM 3 R2 TO µp R3 PFO *OPTIONAL *MAXIMUM Rp ALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM Rp ALUE IS kω. ACTIE-HIGH CE LINES FROM LOGIC CE CE RAM 4 5 PFO 0 0 TRIP =.25 H =.25 / R + R2 R2 L TRIP IN H R2 I I R3 L =.25 R + R2 I I R3 R R3 R2 Figure0. Alternate CE Gating Figure. Adding Hysteresis to the Power-Fail Comparator old and power is lost at CC, the SuperCap on BATT discharges through CC until BATT reaches the reset threshold; then the battery-backup mode is initiated and the current through CC goes to zero. Using Separate Power Supplies for BATT and CC If using separate power supplies for CC and BATT, BATT must be less than 0.3 above CC when CC is above the reset threshold. As described in the previous section, if BATT exceeds this limit and power is lost at CC, current flows continuously from BATT to CC via the BATT-to- OUT diode and the OUT -to- CC switch until the circuit is broken (Figure ). Alternate Chip-Enable Gating Using memory devices with both CE and CE inputs allows the CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to OUT, and connect CE OUT to the CE input of each memory device (Figure 0). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated. 5 PFO 0 +5 R R =.25 - TRIP R R2 NOTE: TRIP IS NEGATIE. PFI TRIP - Figure 2. Monitoring a Negative oltage - CC PFO 0 Maxim Integrated 3

14 MAXIMUM TRANSIENT DURATION (µs) CC = 5 T A = +25 C 0.µF CAPACITOR FROM OUT TO COMPARATOR OERDRIE, (Reset Threshold oltage - CC ) (m) Figure 3. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdriv Adding Hysteresis to the Power-Fail Comparator Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when IN is near the power-fail comparator trip point. Figure shows how to add hysteresis to the power-fail comparator. Select the ratio of R and R2 such that PFI sees.25 when IN falls to the desired trip point ( TRIP ). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R or R2. The current through R and R2 should be at least μa to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 0kΩ to prevent it from loading down the PFO pin. Capacitor C adds noise rejection. Monitoring a Negative oltage The power-fail comparator can be used to monitor a negative supply voltage using Figure 2 s circuit. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit s MAX79-6 accuracy is affected by the PFI threshold tolerance, the CC voltage, and resistors R and R2. Backup-Battery Replacement The backup battery may be disconnected while CC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses. Negative-Going CC Transients While issuing resets to the μp during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going CC transients (glitches). It is usually undesirable to reset the μp when CC experiences only small glitches. Figure 3 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing CC pulses, starting at 5 and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going CC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a CC transient that goes 00m below the reset threshold and lasts for 40μs or less will not cause a reset pulse to be issued. A 00nF bypass capacitor mounted close to the CC pin provides additional transient immunity. Connecting a Timing Capacitor at OSC IN When is connected to ground, OSC IN disconnects from its internal 0μA (typ) pullup and is internally connected to a ±00nA current source. When a capacitor is connected from OSC IN to ground (to select alternative reset and watchdog timeout periods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors or oscillator startup prob- Maxim Integrated 4

15 lems, minimize external current leakage sources at this pin, and locate the capacitor as close to OSC IN as possible. The sum of PC-board leakage plus OSC capacitor leakage must be small compared to ±00nA. Maximum CC Fall Time The CC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03/μs. A standard rule of thumb for filter capacitance on most regulators is on the order of 00μF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial CC fall rate is just the inverse or A/00μF = 0.0/μs. The CC fall rate decreases with time as CC falls exponentially, which more than satisfies the maximum fall-time requirement. Watchdog Software Considerations A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than pulsing the watchdog input high-low-high or lowhigh-low. This technique avoids a stuck loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 4 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should hang in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. START SET WDI LOW SUBROUTINE OR PROGRAM LOOP SET WDI HIGH RETURN END Figure 4. Watchdog Flow Diagram Maxim Integrated 5

16 Ordering Information (continued) PART TEMP RANGE PIN- PACKAGE EJE -40 C to +5 C 6 CERDIP MJE -55 C to +25 C 6 CERDIP** MSE/PR -55 C to +25 C 6 Narrow SO** MSE/PR-T -55 C to +25 C 6 Narrow SO** CUE -0 C to +70 C 6 TSSOP CSE -0 C to +70 C 6 Narrow SO CWE -0 C to +70 C 6 Wide SO CPE -0 C to +70 C 6 Plastic DIP C/D -0 C to +70 C Dice* EUE -40 C to +5 C 6 TSSOP ESE -40 C to +5 C 6 Narrow SO EWE -40 C to +5 C 6 Wide SO EPE -40 C to +5 C 6 Plastic DIP EJE -40 C to +5 C 6 CERDIP MJE -55 C to +25 C 6 CERDIP CUE -0 C to +70 C 6 TSSOP CSE -0 C to +70 C 6 Narrow SO CPE -0 C to +70 C 6 Plastic DIP EUE -40 C to +5 C 6 TSSOP ESE -40 C to +5 C 6 Narrow SO EPE -40 C to +5 C 6 Plastic DIP CUE -0 C to +70 C 6 TSSOP CSE -0 C to +70 C 6 Narrow SO CPE -0 C to +70 C 6 Plastic DIP EUE -40 C to +5 C 6 TSSOP ESE -40 C to +5 C 6 Narrow SO EPE -40 C to +5 C 6 Plastic DIP *Dice are specified at T A = +25 C, DC parameters only. **Contact factory for availability and processing to MIL-STD-3B. Devices in PDIP, SO and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. Chip Topography CC BATT ON LOW LINE OUT OSC IN PFI PFO BATT 0.07" (.77mm) SUBSTRATE CONNECTED TO OUT WDO CE IN CE OUT 0." (2.794mm) WDI Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PKG CODE OUTLINE NO. LAND PATTERN NO. 6 TSSOP U CERDIP J Narrow SO S Plastic DIP P Wide SO W Maxim Integrated 6

17 Revision History REISION NUMBER REISION DATE DESCRIPTION PAGES CHANGED 0 09/92 Initial release 2/92 Update Electrical Characteristics table. 2, 3, 4 2 5/93 Update Electrical Characteristics table, Tables and 2. 2, 3, 4, 9, 3 2/93 Update Electrical Characteristics table. 2, 3, 4 4 3/94 Update Electrical Characteristics table. 2, 3, 4 5 /94 Correction to Figure /95 Update to new revision and correct errors. 7 2/96 Update Electrical Characteristics table. 2, 3, 4 2/99 Updated Ordering Information, Pin Configuration, Absolute Maximum Ratings, and Package Information. 9 4/02 Corrected Ordering Information., 2, 6 0 /05 Added lead-free information., 6 /0 Updated Ordering Information., 6 2 9/4 No / OPNs; removed automotive reference from Applications section; updated Package Information table 3 /7 Updated Electrical Characteristics table 2 4 4/ Updated Ordering Information table 6, 6 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 20 Maxim Integrated Products, Inc. 7