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2 FEATURES n Monitors Four Voltages Simultaneously n Adjustable UV and OV Trip Values n Guaranteed Threshold Accuracy: ±.% of Monitored Voltage over Temperature n Input Glitch Rejection n Monitors up to Two Negative Voltages n Buffered V Reference Output n Adjustable Reset Timeout with Timeout Disable n μa Quiescent Current n Open-Drain OV and UV Outputs n Guaranteed OV and UV for V n Available in -Lead SSOP and -Lead (mm mm) DFN Packages APPLICATIONS n Desktop and Notebook Computers n Network Servers n Core, I/O Voltage Monitors LTC9 Quad UV/OV Positive/Negative Voltage Monitor DESCRIPTION The LTC 9 is a quad input voltage monitor intended for monitoring multiple voltages in a variety of applications. Dual inputs for each monitored voltage allow monitoring four separate undervoltage (UV) conditions and four separate overvoltage (OV) conditions. All monitors share a common undervoltage output and a common overvoltage output. The LTC9- has latching capability for the overvoltage output. The LTC9- has functionality to disable both the overvoltage and undervoltage outputs. Polarity selection and a buffered reference allow monitoring up to two separate negative voltages. A three-state input pin allows setting the polarity of two inputs without requiring any external components. Glitch filtering ensures reliable reset operation without false or noisy triggering. The LTC9 provides a precise, versatile, space-conscious, micropower solution for voltage monitoring. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Quad UV/OV Supply Monitor,% Tolerance, V,.V,.V,.V PWER SUPPLIES V.V.V.V.μF Input Threshold Voltage vs Temperature.k.k 9.k.k VH SEL VL VH VL REF VH VL VH LTC9- VL OV UV LATCH TMR C TMR nf SYSTEM 9 TAa TIMEOUT = ms THRESHOLD VOLTAGE, VOUT (V) TEMPERATURE ( C) 9 TAb

3 LTC9 ABSOLUTE MAXIMUM RATINGS Terminal Voltages (Note )....V to V OV, UV....V to V TMR...V to (.V) VLn, VHn, LATCH, DIS, SEL....V to.v Terminal Currents I VCC...mA Reference Load Current (I REF )...±ma I UV, I OV...mA PACKAGE/ORDER INFORMATION (Notes, ) Operating Temperature Range LTC9C... C to C LTC9I... C to C LTC9H... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec) SSOP... C VH VL VH VL VH VL VH VL TOP VIEW TMR SEL LATCH UV OV REF 9 DHC PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA =. C/W EXPOSED PAD (PIN ) PCB CONNECTION OPTIONAL VH VL VH VL VH VL VH VL TOP VIEW TMR SEL LATCH UV OV REF 9 GN PACKAGE -LEAD PLASTIC SSOP T JMAX = C, θ JA = C/W ORDER PART NUMBER LTC9CDHC- LTC9IDHC- LTC9HDHC- ORDER PART NUMBER LTC9CGN- LTC9IGN- LTC9HGN- DHC PART MARKING* GN PART MARKING 9 9I 9H VH VL VH VL VH VL VH VL TOP VIEW TMR SEL DIS UV OV REF 9 DHC PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA =. C/W EXPOSED PAD (PIN ) PCB CONNECTION OPTIONAL VH VL VH VL VH VL VH VL TOP VIEW TMR SEL DIS UV OV REF 9 GN PACKAGE -LEAD PLASTIC SSOP T JMAX = C, θ JA = C/W ORDER PART NUMBER LTC9CDHC- LTC9IDHC- LTC9HDHC- ORDER PART NUMBER LTC9CGN- LTC9IGN- LTC9HGN- DHC PART MARKING* GN PART MARKING 9 9I 9H Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: *The temperature grade is identifi ed by a label on the shipping container.

4 ELECTRICAL CHARACTERISTICS LTC9 The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = C. =.V, VLn =.V, VHn =.V, LATCH =, SEL =, DIS = Open unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V SHUNT Shunt Regulator Voltage I CC = ma l...9 V ºC < T A < ºC l... V ΔV SHUNT Shunt Regulator Load Regulation I CC = ma to ma l mv Supply Voltage (Note ) l. V SHUNT V R(MIN) Minimum Output Valid DIS = V l V (UVLO) Supply Undervoltage Lockout Rising, DIS = V l.9. V Δ(UVHYST) Supply Undervoltage Lockout Hysteresis DIS = V l mv I CC Supply Current =.V to V l μa V REF Reference Output Voltage I VREF = ±ma l.9. V ºC < T A < ºC l.9. V V UOT Undervoltage/Overvoltage Voltage Threshold l 9 mv t UOD Undervoltage/Overvoltage Voltage Threshold VHn = V UOT mv or VLn = V UOT mv l μs to Output Delay I VHL VHn, VLn Input Current l ± na ºC < T A < ºC l ± na t UOTO UV/OV Time-Out Period C TMR = nf l.. ms ºC < T A < ºC l. ms V LATCH(IH) OV Latch Clear Input High l. V V LATCH(IL) OV Latch Clear Threshold Input Low l. V I LATCH LATCH Input Current V LATCH >.V l ± μa V DIS(IH) DIS Input High l. V V DIS(IL) DIS Input Low l. V I DIS DIS Input Current V DIS >.V l μa I TMR(UP) TMR Pull-Up Current V TMR = V l... μa ºC < T A < ºC l... μa I TMR(DOWN) TMR Pull-Down Current V TMR =.V l... μa ºC < T A < ºC l... μa V TMR(DIS) Timer Disable Voltage Referenced to l mv V OH Output Voltage High UV/OV =.V, I UV/OV = μa l V V OL Output Voltage Low UV/OV =.V, I UV/OV =.ma = V, I UV = μa Three-State Input SEL V IL Low Level Input Voltage l. V V IH High Level Input Voltage l. V V Z Pin Voltage when Left in Hi-Z State I SEL = ±μa l..9. V ºC < T A < ºC l..9. V I SEL SEL High, Low Input Current l ± μa I SEL(MAX) Maximum SEL Input Current SEL Tied to Either or l ± μa l l.... V V

5 LTC9 ELECTRICAL CHARACTERISTICS Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : All currents into pins are positive; all voltages are referenced to unless otherwise noted. Note : maximum pin voltage is limited by input current. Since the pin has an internal.v shunt regulator, a low impedance supply that exceeds V may exceed the rated terminal current. Operation from higher voltage supplies requires a series dropping resistor. See Applications Information. TIIMING DIAGRAMS VHn Monitor Timing VLn Monitor Timing VHn V UOT VLn V UOT t UOD t UOTO t UOD t UOTO UV V 9 TD OV V 9 TD VHn Monitor Timing (TMR Pin Strapped to ) VLn Monitor Timing (TMR Pin Strapped to ) VHn V UOT VLn V UOT t UOD t UOD t UOD t UOD UV V 9 TD OV V 9 TD NOTE: WHEN AN INPUT IS CONFIGURED AS A NEGATIVE SUPPLY MONITOR, VHn WILL TRIGGER AN OV CONDITION AND VLn WILL TRIGGER A UV CONDITION TYPICAL PERFORMANCE CHARACTERISTICS Specifi cations are at T A = C, =.V unless otherwise noted. Input Threshold Voltage vs Temperature Supply Current vs Temperature Shunt Voltage vs Temperature THRESHOLD VOLTAGE, V OUT (V) I CC (μa) = V =.V =.V (V) ma ma ma ma μa.9 TEMPERATURE ( C) TEMPERATURE ( C). TEMPERATURE ( C) 9 G 9 G 9 G

6 TYPICAL PERFORMANCE CHARACTERISTICS Specifi cations are at T A = C, =.V unless otherwise noted. LTC9 (V)..... Shunt Voltage vs I CC C C. C I CC (ma) 9 G REFERENCE VOLTAGE, V REF (V) Buffered Reference Voltage vs Temperature TEMPERATURE ( C) 9 G TYPICAL TRANSIENT DURATION (μs) Transient Duration vs Comparator Overdrive. =.V = V RESET OCCURS ABOVE CURVE COMPARATOR OVERDRIVE PAST THRESHOLD (%) 9 G UV/OV TIMEOUT PERIOD, t UOTO (ms) 9 Reset Timeout Period vs Temperature C TMR = nf UV VOLTAGE (V).... UV Output Voltage vs UV WITHOUT k PULL-UP UV WITH k PULL-UP UV VOLTAGE (V) UV Output Voltage vs VHn =.V SEL = TEMPERATURE ( C)..... SUPPLY VOLTAGE, (V) SUPPLY VOLTAGE, (V) 9 G 9 G 9 G9 PULL-DOWN CURRENT, I UV (ma) UV, I SINK vs VHn =.V SEL = UV AT mv UV AT mv UV/OV, V OL (V)..... UV/OV Voltage Output Low vs Output Sink Current C C C UV/OV TIMEOUT PERIOD, t UOTO (ms) Reset Timeout Period vs Capacitance SUPPLY VOLTAGE, (V) I UV/OV (ma). TMR PIN CAPACITANCE, C TMR (nf) 9 G 9 G 9 G

7 LTC9 PIN FUNCTIONS DIS (Pin, LTC9-): Output Disable Input. Disables the OV and UV output pins. When DIS is pulled high, the OV and UV pins are not asserted except during a UVLO condition. Pin has a weak (μa) internal pull-down to. Leave pin open if unused. Exposed Pad (Pin, DFN Package): Exposed Pad may be left open or connected to device ground. (Pin 9): Device Ground LATCH (Pin, LTC9-): OV Latch Clear/Bypass Input. When pulled low, OV is latched when asserted. When pulled high, OV latch is cleared. While held high, OV has the same delay and output characteristics as UV. OV (Pin ): Overvoltage Logic Output. Asserts low when any positive polarity input voltage is above threshold or any negative polarity input voltage is below threshold. Latched low (LTC9-). Held low for an adjustable delay time after all inputs are valid (LTC9-). Pin has a weak pull-up to and may be pulled above using an external pull-up. Leave pin open if unused. REF (Pin ): Buffered Reference Output. V reference used for the offset of negative-monitoring applications. The buffered reference sources and sinks up to ma. The reference drives capacitive loads up to nf. Larger capacitive loads may cause instability. Leave pin open if unused. SEL (Pin ): Input Polarity Select Three-State Input. Connect to, or leave unconnected in open state to select one of three possible input polarity combinations (refer to Table ). TMR (Pin ): Reset Delay Timer. Attach an external capacitor (C TMR ) of at least pf to to set a reset delay time of 9ms/nF. A nf capacitor will generate an.ms reset delay time. Tie pin to to bypass timer. UV (Pin ): Undervoltage Logic Output. Asserts low when any positive polarity input voltage is below threshold or any negative polarity input voltage is above threshold. Held low for an adjustable delay time after all voltage inputs are valid. Pin has a weak pull-up to and may be pulled above using an external pull-up. Leave pin open if unused. (Pin ): Supply Voltage. Bypass this pin to with a.μf (or greater) capacitor. Operates as a direct supply input for voltages up to V. Operates as a shunt regulator for supply voltages greater than V and must have a resistance between the pin and the supply to limit input current to no greater than ma. When used without a current-limiting resistance, pin voltage must not exceed V. VH/VH (Pin /Pin ): Voltage High Inputs and. When the voltage on this pin is below.v, an undervoltage condition is triggered. Tie pin to if unused. VH/VH (Pin /Pin ): Voltage High Inputs and. The polarity of the input is selected by the state of the SEL pin (refer to Table ). When the monitored input is configured as a positive voltage, an undervoltage condition is triggered when the pin is below.v. When the monitored input is configured as a negative voltage, an overvoltage condition is triggered when the pin is below.v. Tie pin to if unused. VL/VL (Pin /Pin ): Voltage Low Inputs and. When the voltage on this pin is above.v, an overvoltage condition is triggered. Tie pin to if unused. VL/VL (Pin /Pin ): Voltage Low Inputs and. The polarity of the input is selected by the state of the SEL pin (refer to Table ). When the monitored input is configured as a positive voltage, an overvoltage condition is triggered when the pin is above.v. When the monitored input is configured as a negative voltage, an undervoltage condition is triggered when the pin is above.v. Tie pin to if unused.

8 LTC9 BLOCK DIAGRAM TMR VH OSCILLATOR k UV VL UV PULSE GENERATOR VH UVLO VL UVLO V OV PULSE GENERATOR DISABLE k OV VH OV LATCH CLEAR/BYPASS LATCH VL VH LTC9- V DIS V μa LTC9- VL.V REF V THREE-STATE POLARITY DECODER 9 BUFFER SEL 9 - BD

9 LTC9 APPLICATIONS INFORMATION Voltage Monitoring The LTC9 is a low power quad voltage monitoring circuit with four undervoltage and four overvoltage inputs. A timeout period that holds OV or UV asserted after all faults have cleared is adjustable using an external capacitor and is externally disabled. Each voltage monitor has two inputs (VHn and VLn) for detecting undervoltage and overvoltage conditions. When confi gured to monitor a positive voltage V n using the -resistor circuit configuration shown in Figure, V Hn is connected to the high-side tap of the resistive divider and VLn is connected to the low-side tap of the resistive divider. If an input is configured as a negative voltage monitor, the outputs UV n and OV n in Figure are swapped internally. V n is then connected as shown in Figure. Note, VHn is still connected to the high-side tap and VLn is still connected to the low-side tap. Polarity Selection The three-state polarity-select pin (SEL) selects one of three possible polarity combinations for the input thresholds, as described in Table. When an input is configured for negative supply monitoring, VHn is configured to trigger an overvoltage condition and VLn is configured to trigger an undervoltage condition. With this configuration, an OV condition occurs when the supply voltage is more negative than the configured threshold and a UV condition occurs when the voltage is less negative than the configured threshold. V n The three-state input pin SEL is connected to, or left unconnected during normal operation. When the pin is left unconnected, the maximum leakage allowed from the pin is ±μa to ensure it remains in the open state. Table shows the three possible selections of polarity based on the SEL pin connection. Table. Voltage Polarity Programming (V UOT =.V Typical) SEL V INPUT V INPUT Positive Positive Open VH < V UOT UV VL > V UOT OV Positive VH < V UOT UV VL > V UOT OV Negative VH < V UOT OV VL > V UOT UV VH < V UOT UV VL > V UOT OV Negative VH < V UOT OV VL > V UOT UV Negative VH < V UOT OV VL > V UOT UV -Step Design Procedure The following -step design procedure allows selecting appropriate resistances to obtain the desired UV and OV trip points for the positive voltage monitor circuit in Figure and the negative voltage monitor circuit in Figure. LTC9 REF V R C LTC9 VHn R A VHn UV n OV n R B.V R B.V VLn OV n VLn UV n R A R C 9 F V n 9 F Figure. -Resistor Positive UV/OV Monitoring Confi guration Figure. -Resistor Negative UV/OV Monitoring Confi guration

10 LTC9 APPLICATIONS INFORMATION For positive supply monitoring, V n is the desired nominal operating voltage, I n is the desired nominal current through the resistive divider, V OV is the desired overvoltage trip point and V UV is the desired undervoltage trip point. For negative supply monitoring, to compensate for the V reference, V must be subtracted from V n, V OV and V UV before using each in the following equations.. Choose R A to obtain the desired OV trip point R A is chosen to set the desired trip point for the overvoltage monitor. R A =.V I n V n V OV (). Choose R B to obtain the desired UV trip point Once R A is known, R B is chosen to set the desired trip point for the undervoltage monitor. R B =.V V n R I n V A () UV. Choose R C to Complete the Design Once R A and R B are known, R C is determined by: R C = V n R I A R B () n If any of the variables V n, I n, V UV or V OV change, then each step must be recalculated. Positive Voltage Monitor Example A positive voltage monitor application is shown in Figure. The monitored voltage is a V ±% supply. Nominal current in the resistive divider is μa.. Find R A to set the OV trip point of the monitor. R A =.V µa V.V.k. Find R B to set the UV trip point of the monitor. R B =.V µa V.V.k.k. Determine R C to complete the design. R C = V µa.k.k k Negative Voltage Monitor Example A negative voltage monitor application is shown in Figure. The monitored voltage is a V ±% supply. Nominal current in the resistive divider is μa. For the negative case, V is subtracted from V n, V OV and V UV.. Find R A to set the OV trip point of the monitor. R A =.V V V µa.v V.k. Find R B to set the UV trip point of the monitor. R B =.V V V µa.v V.k.k. Determine R C to complete the design. R C = V V µa.k.k 9k V V V ±% V REF OV R C k R B.k R A.k VH LTC9 VL UV SEL OV 9 F R A.k R B.k R C 9k V V ±% LTC9 VH VL UV SEL 9 F Figure. Positive Supply Monitor Figure. Negative Supply Monitor 9

11 LTC9 APPLICATIONS INFORMATION Power-Up/Power-Down As soon as reaches V during power-up, the UV output asserts low and the OV output weakly pulls to. The LTC9 is guaranteed to assert UV low and OV high under conditions of low, down to = V. Above = V (.V maximum) the VH and VL inputs take control. Once all VH inputs and become valid an internal timer is started. After an adjustable delay time, UV weakly pulls high. Threshold Accuracy Reset threshold accuracy is important in a supply-sensitive system. Ideally, such a system resets only if supply voltages fall outside the exact thresholds for a specified margin. All LTC9 inputs have a relative threshold accuracy of ±.% over the full operating temperature range. For example, when the LTC9 is programmed to monitor a V input with a % tolerance, the desired UV trip point is.v. Because of the ±.% relative accuracy of the LTC9, the UV trip point is between.v and.v which is.v ±.%. Likewise, the accuracy of the resistances chosen for R A, R B and R C affect the UV and OV trip points as well. Using the example just given, if the resistances used to set the UV trip point have % accuracy, the UV trip range is between.v and.v. This is illustrated in the following calculations. The UV trip point is given as: R V UV =.V C R A R B The two extreme conditions, with a relative accuracy of.% and resistance accuracy of %, result in: R V UV(MIN) =.V.9 C.99 ( R A R B ). and R V UV(MAX) =.V. C. ( R A R B ).99 R For a desired trip point of.v, C = R A R B Therefore, V UV(MIN) =.V =.V and V UV(MAX) =.V...99 =.V Glitch Immunity In any supervisory application, noise riding on the monitored DC voltage causes spurious resets. To solve this problem without adding hysteresis, which causes a new error term in the trip voltage, the LTC9 lowpass filters the output of the first stage comparator at each input. This filter integrates the output of the comparator before asserting the UV or OV logic. A transient at the input of the comparator of sufficient magnitude and duration triggers the output logic. The Typical Performance Characteristics section shows a graph of the Transient Duration vs Comparator Overdrive.

12 APPLICATIONS INFORMATION UV/OV Timing The LTC9 has an adjustable timeout period (t UOTO ) that holds OV or UV asserted after all faults have cleared. This assures a minimum reset pulse width allowing a settling time delay for the monitored voltage after it has entered the valid region of operation. When any VH input drops below its designed threshold, the UV pin asserts low. When all inputs recover above their designed thresholds, the UV output timer starts. If all inputs remain above their designed thresholds when the timer finishes, the UV pin weakly pulls high. However, if any input falls below its designed threshold during this time-out period, the timer resets and restarts when all inputs are above the designed thresholds. The OV output behaves as the UV output when LATCH is high (LTC9-). Selecting the UV/OV Timing Capacitor The UV and OV timeout period (t UOTO ) for the LTC9 is adjustable to accommodate a variety of applications. Connecting a capacitor, C TMR, between the TMR pin and ground sets the timeout period. The value of capacitor needed for a particular timeout period is: C TMR = t UOTO 9 (F/s) The Reset Timeout Period vs Capacitance graph found in the Typical Performance Characteristics shows the desired delay time as a function of the value of the timer capacitor that must be used. The TMR pin must have a minimum of pf or be tied to. For long timeout periods, the only limitation is the availability of a large value capacitor with low leakage. Capacitor leakage current must not exceed the minimum TMR charging current of.μa. Tying the TMR pin to bypasses the timeout period. LTC9 Undervoltage Lockout When falls below V, the LTC9 asserts an undervoltage lockout (UVLO) condition. During UVLO, UV is asserted and pulled low while OV is cleared and blocked from asserting. When rises above V, UV follows the same timing procedure as an undervoltage condition on any input. Shunt Regulator The LTC9 has an internal shunt regulator. The pin operates as a direct supply input for voltages up to V. Under this condition, the quiescent current of the device remains below a maximum of μa. For voltages higher than V, the device operates as a shunt regulator and must have a resistance R Z between the supply and the pin to limit the current to no greater than ma. When choosing this resistance value, choose an appropriate location on the I-V curve shown in the Typical Performance Characteristics section to accommodate variations in due to changes in current through R Z. UV and OV Output Characteristics The DC characteristics of the UV and OV pull-up and pull-down strength are shown in the Typical Performance Characteristics section. Each pin has a weak internal pull-up to and a strong pull-down to ground. This arrangement allows these pins to have open-drain behavior while possessing several other beneficial characteristics. The weak pull-up eliminates the need for an external pull-up resistor when the rise time on the pin is not critical. On the other hand, the open-drain configuration allows for wired-or connections and is useful when more than one signal needs to pull down on the output. of V guarantees a maximum V OL =.V at UV.

13 LTC9 APPLICATIONS INFORMATION At = V, the weak pull-up current on OV is barely turned on. Therefore, an external pull-up resistor of no more than k is recommended on the OV pin if the state and pull-up strength of the OV pin is crucial at very low. Note however, by adding an external pull-up resistor, the pull-up strength on the OV pin is increased. Therefore, if it is connected in a wired-or connection, the pull-down strength of any single device must accommodate this additional pull-up strength. Output Rise and Fall Time Estimation The UV and OV outputs have strong pull-down capability. The following formula estimates the output fall time (9% to %) for a particular external load capacitance (C LOAD ): t FALL. R PD C LOAD where R PD is the on-resistance of the internal pull-down transistor, typically Ω at > V and at room temperature ( C). C LOAD is the external load capacitance on the pin. Assuming a pf load capacitance, the fall time is.ns. The rise time on the UV and OV pins is limited by a k pull-up resistance to. A similar formula estimates the output rise time (% to 9%) at the UV and OV pins: OV Latch (LTC9-) With the LATCH pin held low, the OV pin latches low when an OV condition is detected. The latch is cleared by raising the LATCH pin high. If an OV condition clears while LATCH is held high, the latch is bypassed and the OV pin behaves the same as the UV pin with a similar timeout period at the output. If LATCH is pulled low while the timeout period is active, the OV pin latches as before. Disable (LTC9-) The LTC9- allows disabling the UV and OV outputs via the DIS pin. Pulling DIS high forces both outputs to remain weakly pulled high, regardless of any faults that occur on the inputs. However, if a UVLO condition occurs, UV asserts and pulls low, but the timeout function is bypassed. UV pulls high as soon as the UVLO condition is cleared. DIS has a weak μa (typical) internal pull-down current guaranteeing normal operation with the pin left open. t RISE. R PU C LOAD where R PU is the pull-up resistance.

14 TYPICAL APPLICATIONS Quad UV/OV Supply Monitor, % Tolerance, V,.V,.V,.V LTC9 PWER SUPPLIES V.V.V.V C BYP.μF R C.k R B R A R C.k R B R A R C 9.k R B R A R C.k R B R A VL VH VL REF VH VL 9 VH SEL VH LTC9- VL OV UV LATCH TMR SYSTEM C TMR nf TIMEOUT = ms 9 TA Dual Positive and Dual Negative UV/OV Supply Monitor, % Tolerance, V,.V, V,.V PWER SUPPLIES V.V C BYP.μF R C.k R B R A R C.k R B R A R A.k R B Ω R C.9k R A.k R B Ω R C.k VH VL VH OV LTC9- VL REF VH VL VH VL 9 UV LATCH SEL TMR C TMR.nF SYSTEM.V V TIMEOUT = ms 9 TA

15 LTC9 Triple UV/OV Supply Monitor Powered from V, % Tolerance, V, V,.V V PWER SUPPLIES V.V R Z.k C BYP.μF R C k R B R A R C.k R B R A R C 9.k R B R A VL VH VL REF VH VL VH SEL VH LTC9- VL TMR OV UV LATCH SYSTEM 9 9 TA

16 PACKAGE DESCRIPTION DHC Package -Lead Plastic DFN (mm mm) (Reference LTC DWG # --) LTC9. ±.. ±. ( SIDES) R =. TYP 9 R =. TYP. ±.. ±.. ±.. ±. ( SIDES). ±.. BSC. ±. ( SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN TOP MARK (SEE NOTE ) PACKAGE OUTLINE. REF NOTE:. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-) IN JEDEC PACKAGE OUTLINE MO-9. DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS. ±. ( SIDES). ±.. ±. ( SIDES)... ±. ( SIDES) BOTTOM VIEW EXPOSED PAD. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE. ±.. BSC PIN NOTCH (DHC) DFN GN Package -Lead Plastic SSOP (Narrow. Inch) (Reference LTC DWG # --). ±..9.9* (..9) 9.9 (.9) REF. MIN...9. (..9)..** (..9). ±. RECOMMENDED SOLDER PAD LAYOUT. BSC..9 (..9). ±. (. ±.) TYP.. (..)..9 (..9).. (..) NOTE:. CONTROLLING DIMENSION: INCHES INCHES. DIMENSIONS ARE IN (MILLIMETERS). DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..) TYP. (.) BSC GN (SSOP) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

17 LTC9 TYPICAL APPLICATION Quad UV/OV Supply Monitor with LED Undervoltage and Overvoltage Indicator and Manual Undervoltage Reset Button, % Tolerance, V, V,.V,.V PWER SUPPLIES V V.V.V.μF.k.k VH SEL Ω LED Ω LED 9.k.M VL VH OV LTC9- VL UV REF VH LATCH SYSTEM VL VH k k VL TMR 9 TA C TMR nf TIMEOUT = ms MANUAL RESET BUTTON (NORMALLY OPEN) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC/ Micropower Precision Triple Supply Monitor for V/.V,.V,.V, V Threshold (±.%) LTC-..V and ADJ LTC-./ Micropower Triple Supply Monitor for.v/v,.v and ADJ Adjustable RESET and Watchdog Time-Outs LTC- LTC-./ Micropower Triple Supply Monitor with Open-Drain Reset Individual Monitor Outputs in MSOP LTC- LTC-./ Micropower Triple Supply Monitor with Open-Drain Reset -Lead SOT- Package LTC-. LTC-./ Micropower Triple Supply Monitor with Open-Drain Reset -Lead SOT- Package LTC- LTC9-. Micropower Triple Supply Monitor with Push-Pull Reset -Lead SOT- Package LTC9 Programmable Quad Supply Monitor Adjustable RESET, -Lead MSOP and mm x mm -Lead DFN Package LTC9 Programmable Quad Supply Monitor Adjustable RESET and Watchdog Timer, -Lead SSOP Package LTC9 Programmable Quad Supply Monitor Adjustable RESET and Tolerance, -Lead SSOP Package, Margining Functions LTC9 Precision Quad Supply Monitor -Lead SOT- Package, Ultralow Voltage Reset LTC9 Three-State Programmable Precision Dual Supply Monitor Adjustable Tolerance, -Lead SOT- Package LTC9 Three-State Programmable Precision Dual Supply Monitor Adjustable RESET and Tolerance, -Lead SOT- Package LTC9 Precision Dual Supply Monitor Selectable and Adjustable Separate Pin, RST/RST Outputs LTC9 Precision Dual Supply Monitor Selectable and Adjustable Separate, Adjustable Reset Timer LTC9 Precision Six Supply Monitor -Lead TSOT- and mm mm DFN Packages LTC99 Precision Dual Input UV, OV and Negative Voltage Monitor Separate Pin, Adjustable Reset Timer, -Lead TSOT- and mm mm DFN Packages LT REV A PRINTED IN USA Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - LINEAR TECHNOLOGY CORPORATION