The LTC 4359 is a positive high voltage, ideal diode. 12V, 20A Automotive Reverse-Battery Protection Power Dissipation vs Load Current V OUT TO LOAD

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1 Idea Diode Controer with Reverse Input Protection FEATURES n Reduces Power Dissipation by Repacing a Power Schottky Diode n Wide Operating Votage Range: V to 8V n Reverse Input Protection to V n Low 9 Shutdown Current n Low 15μA Operating Current n Smooth Switchover without Osciation n Contros Singe or Back-to-Back N-Channe MOSFETs n Avaiabe in 6-Lead (2mm 3mm) DFN and 8-Lead MSOP Packages APPLICATIONS n Automotive Battery Protection n Redundant Power Suppies n Suppy Hodup n Teecom Infrastructure n Computer Systems/Servers n Soar Systems DESCRIPTION The LTC 359 is a positive high votage, idea diode controer that drives an externa N-channe MOSFET to repace a Schottky diode. It contros the forward-votage drop across the MOSFET to ensure smooth current deivery without osciation even at ight oads. If a power source fais or is shorted, a fast turn-off minimizes reverse current transients. A shutdown mode is avaiabe to reduce the quiescent current to 9μA for oad switch and 1 for idea diode appications. When used in high current diode appications, the reduces power consumption, heat dissipation, votage oss and PC board area. With its wide operating votage range, the abiity to withstand reverse input votage, and high temperature rating, the satisfies the demanding requirements of both automotive and teecom appications. The aso easiy ORs power sources in systems with redundant suppies. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and Hot Swap is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION, 2A Automotive Reverse-Battery Protection Power Dissipation vs Load Current V SMAT7A 7V SMAJ2A BSC28N6NS SOURCE 359 TA1 V TO LOAD 7nF POWER DISSIPATION (W) SCHOTTKY DIODE (SBG2CT) POWER SAVED MOSFET (BSC28N6NS) CURRENT (A) TA1a For more information 1

2 ABSOLUTE MAXIMUM RATGS (Notes 1, 2), SOURCE,... V to 1V (Note 3)... 2V to 1V... 1V to 1V SOURCE... 1V to 8V (Note )... V SOURCE.3V to V SOURCE +1V Operating Ambient Temperature Range C... C to 7 C I... C to 85 C H... C to 125 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec) MS Package...3 C P CONFIGURATION TOP VIEW SOURCE DCB PACKAGE 6-LEAD (2mm 3mm) PLASTIC DFN T JMAX = 125 C, θ JA = 6 C/W EXPOSED PAD (P 7) PCB CONNECTION OPTIONAL SOURCE 2 NC 3 TOP VIEW 8 7 NC 6 5 MS8 PACKAGE 8-LEAD PLASTIC MSOP T JMAX = 125 C, θ JA = 163 C/W ORDER FORMATION Lead Free Finish TAPE AND REEL (MI) TAPE AND REEL PART MARKG* PACKAGE DESCRIPTION TEMPERATURE RANGE CDCB#TRMPBF CDCB#TRPBF LFKF 6-Lead (2mm 3mm) Pastic DFN C to 7 C IDCB#TRMPBF IDCB#TRPBF LFKF 6-Lead (2mm 3mm) Pastic DFN C to 85 C HDCB#TRMPBF HDCB#TRPBF LFKF 6-Lead (2mm 3mm) Pastic DFN C to 125 C LEAD FREE FISH TAPE AND REEL PART MARKG* PACKAGE DESCRIPTION TEMPERATURE RANGE CMS8#PBF CMS8#TRPBF LTFKD 8-Lead Pastic MSOP C to 7 C IMS8#PBF IMS8#TRPBF LTFKD 8-Lead Pastic MSOP C to 85 C HMS8#PBF HMS8#TRPBF LTFKD 8-Lead Pastic MSOP C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2 For more information

3 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2. A currents into pins are positive; a votages are referenced to uness otherwise specified. The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C, =, SOURCE =, uness otherwise noted. SYMBOL PARAMETER CONDITIONS M TYP MAX UNITS V Operating Suppy Range 8 V I Current = = =, = V = =, = V = V I Current =, In Reguation =, V SD = 1V = =, = V = =, = V =, = = V I SOURCE SOURCE Current =, V SD = 1V = SOURCE =, = V SOURCE = V V Gate Drive ( SOURCE) = V, I =, 1 = 8V to 8V; I =, V SD Source-Drain Reguation Votage ( ) V = 2.5V mv I (UP) Gate Pu-Up Current =, V SD =.1V I (DOWN) Gate Pu-Down Current Faut Condition, V = 5V, V SD = 1V Shutdown Mode, V = 5V, V SD =.7V t OFF Gate Turn-Off Deay Time V SD =.1V to 1V, V < 2V, C = pf ma V V ma ma.3.5 µs V (TH) Pin Input Threshod = V to 8V V V (FLT) Pin Foat Votage = V to 8V V I Pin Current =.5V, I, C =.5V, H = V Maximum Aowabe Leakage, V = V V SOURCE(TH) Reverse SOURCE Threshod for Off = V, I (DOWN) = 1mA V Note 3. An interna camp imits the pin to a minimum of 1V above. Driving this pin with more current than 1mA may damage the device. Note. An interna camp imits the pin to a minimum of 1V above or 1V above. Driving this pin to votages beyond the camp may damage the device. ma na For more information 3

4 TYPICAL PERFORMANCE CHARACTERISTICS 2 15 Current in Reguation Current in Shutdown SOURCE Current in Shutdown 5 = SOURCE = = V 1 8 = SOURCE = = V I () 1 I () 3 2 I SOURCE () V (V) G V (V) T A = 125 C T A = 85 C T A = 25 C T A = C G V SOURCE (V) T A = 125 C T A = 85 C T A = 25 C T A = C G3 I () Current vs Forward Votage Drop V = 8V V = V = V I SOURCE () SOURCE Current vs Forward Votage Drop V SOURCE = V V SOURCE > = SOURCE I + I SOURCE + I (ma) Tota Negative Current vs Negative Input Votage = SOURCE= V SD (V) G V SD (V) G VOLTAGE (V) 359 G6 2 1 Gate Current vs Forward Votage Drop V = V SOURCE = V = V +2.5V Gate Drive vs Gate Current 15 = SOURCE V > V = 8V 1 Gate Turn-Off Time vs Capacitance 8 V = V SD =.1V 1V 6 I () 1 V (V) t OFF (ns) V = V V SD (mv) I () C (nf) 359 G7 359 G8 359 G9 For more information

5 TYPICAL PERFORMANCE CHARACTERISTICS t PD (ns) Gate Turn-Off Time vs Initia Overdrive V = V SD = V ITIAL 1V t PD (ns) Gate Turn-Off Time vs Fina Overdrive V = V SD = 5mV V FAL CURRENT (A) Load Current vs Forward Votage Drop FDMS8611 FDB3632 FDS V ITIAL (V) G V FAL (V) G V SD (mv) G12 P FUNCTIONS Exposed Pad (DCB Package Ony): Exposed pad may be eft open or connected to. : Gate Drive Output. The pin pus high, enhancing the N-channe MOSFET when the oad current creates more than 3mV of votage drop across the MOSFET. When the oad current is sma, the gate is activey driven to maintain 3mV across the MOSFET. If reverse current fows, a fast pu-down circuit connects the to the SOURCE pin within.3μs, turning off the MOSFET. : Votage Sense and Suppy Votage. is the anode of the idea diode. The votage sensed at this pin is used to contro the MOSFET gate. NC (MS Package Ony): No Connection. Not internay connected. : Drain Votage Sense. is the cathode of the idea diode and the common output when mutipe s are configured as an idea diode-or. It connects either directy or through a 2k resistor to the drain of the N-channe MOSFET. The votage sensed at this pin is used to contro the MOSFET gate. : Shutdown Contro Input. The can be shut down to a ow current mode by puing the pin beow.6v. Puing this pin above 2V or disconnecting it aows an interna 2.6μA current source to turn the part on. Maintain board eakage to ess than 1nA for proper operation. The pin can be pued up to 1V or down to V with respect to without damage. If the shutdown feature is not used, connect to. SOURCE: Source Connection. SOURCE is the return path of the gate fast pu-down. Connect this pin as cose as possibe to the source of the externa N-channe MOSFET. : Suppy Votage Return and Device Ground. For more information 5

6 BLOCK DIAGRAM V V SOURCE 2.6 SHUTDOWN 1.7V + NEGATIVE COMP CHARGE PUMP TYP. 5kHz FPD COMP + AMP + + 3mV + 3mV 359 BD 6 For more information

7 OPERATION The contros an externa N-channe MOSFET to form an idea diode. The ampifier (see Bock Diagram) senses across and and drives the gate of the MOSFET to reguate the forward votage to 3mV. As the oad current increases, is driven higher unti a point is reached where the MOSFET is fuy on. Further increases in oad current resut in a forward drop of R DS(ON) I LOAD. If the oad current is reduced, the ampifier drives the MOSFET gate ower to maintain a 3mV drop. If the input votage is reduced to a point where a forward drop of 3mV cannot be supported, the ampifier drives the MOSFET off. In the event of a rapid drop in input votage, such as an input short-circuit faut or negative-going votage spike, reverse current temporariy fows through the MOSFET. This current is provided by any oad capacitance and by other suppies or batteries that feed the output in diode- OR appications. The FPD COMP (Fast Pu-Down Comparator) quicky responds to this condition by turning the MOSFET off in 3ns, thus minimizing the disturbance to the output bus. The, SOURCE, and pins are protected against reverse inputs of up to V. The NEGATIVE COMP detects negative input potentias at the SOURCE pin and quicky pus to SOURCE, turning off the MOSFET and isoating the oad from the negative input. When pued ow the pin turns off most of the interna circuitry, reducing the quiescent current to 9 and hoding the MOSFET off. The pin may be either driven high or eft open to enabe the. If eft open, an interna 2.6 current source pus high. In appications where is repaced with back-to-back MOSFETs, the pin serves as an on/off contro for the forward path, as we as enabing the diode function. APPLICATIONS FORMATION Bocking diodes are commony paced in series with suppy inputs for the purpose of ORing redundant power sources and protecting against suppy reversa. The repaces diodes in these appications with a MOSFET to reduce both the votage drop and power oss associated with a passive soution. The curve shown on page 1 iustrates the dramatic improvement in power oss achieved in a practica appication. This represents significant savings in board area by greaty reducing power dissipation in the pass device. At ow input votages, the improvement in forward votage oss is readiy appreciated where headroom is tight, as shown in Figure 2. The operates from V to 8V and withstands an absoute maximum range of V to 1V without damage. In automotive appications the operates through oad dump, cod crank and two-battery jumps, and it survives reverse battery connections whie aso protecting the oad. A /2A idea diode appication is shown in Figure 1. Severa externa components are incuded in addition to the MOSFET,. Idea diodes, ike their nonidea coun- For more information terparts, exhibit a behavior known as reverse recovery. In combination with parasitic or intentionay introduced inductances, reverse recovery spikes may be generated by an idea diode during commutation. D1, D2 and R1 protect against these spikes which might otherwise exceed the s V to 1V surviva rating. C aso pays a roe in absorbing reverse recovery energy. Spikes and protection schemes are discussed in detai in the Input Short-Circuit Fauts section. V D1 SMAT7A 7V D2 SMAJ2A BSC28N6NS SOURCE 359 F1 C 7nF Figure 1. /2A Idea Diode with Reverse Input Protection R1 V 2A 7

8 APPLICATIONS FORMATION CURRENT (A) MOSFET (BSC28N6NS) SCHOTTKY DIODE (SBG2CT) The MOSFET s on-resistance, R DS(ON), directy affects the forward votage drop and power dissipation. Desired forward votage drop shoud be ess than that of a diode for reduced power dissipation; 1mV is a good starting point. Choose a MOSFET which has: Forward Votage Drop R DS(ON) < I LOAD The resuting power dissipation is VOLTAGE (V) Figure 2. Forward Votage Drop Comparison Between MOSFET and Schottky Diode It is important to note that the pin, whie disabing the and reducing its current consumption to 9, does not disconnect the oad from the input since s body diode is ever-present. A second MOSFET is required for oad switching appications. MOSFET Seection A oad current passes through an externa MOSFET,. The important characteristics of the MOSFET are onresistance, R DS(ON), the maximum drain-source votage, BV DSS, and the gate threshod votage V GS(TH). Gate drive is compatibe with.5v ogic-eve MOSFETs over the entire operating range of V to 8V. In appications above 8V, standard 1V threshod MOSFETs may be used. An interna camp imits the gate drive to 15V maximum between the and SOURCE pins. For and higher appications, an externa Zener camp (D) must be added between and SOURCE to not exceed the MOSFET s V GS(MAX) during input shorts. The maximum aowabe drain-source votage, BV DSS, must be higher than the power suppy votage. If the input is grounded, the fu suppy votage wi appear across the MOSFET. If the input is reversed, and the output is hed up by a charged capacitor, battery or power suppy, the sum of the input and output votages wi appear across the MOSFET and BV DSS > + V F2 P d = (I LOAD ) 2 R DS(ON) Shutdown Mode In shutdown, the pus ow to SOURCE, turning off the MOSFET and reducing its current consumption to 9. Shutdown does not interrupt forward current fow, a path is sti present through s body diode, as shown in Figure 1. A second MOSFET is needed to bock the forward path; see the section Load Switching and Inrush Contro. When enabed the operates as an idea diode. If shutdown is not needed, connect to. may be driven with a 3.3V or 5V ogic signa, or with an open drain or coector. To assert ow, the pu down must sink at east 5 at 5mV. To enabe the part, must be pued up to at east 2V. If is driven with an open drain, open coector or switch contact, an interna pu-up current of 2.6 (1 minimum) asserts high and enabes the. If eakage from to ground cannot be maintained at ess than 1nA, add a pu-up resistor to >2V to assure turn on. The sef-driven open circuit votage is imited internay to 2.5V. When foating, the impedance is high and is subject to capacitive couping from nearby cock ines or traces exhibiting high dv/dt. Bypass to with 1nF to eiminate injection. Figure 3a is the simpest way to contro the shutdown pin. Since the contro signa ground is different from the pin reference,, there coud be momentary gitches on during transients. Figures 3b and 3c are aternative soutions that eve-shift the contro signa and eiminate gitches. 8 For more information

9 APPLICATIONS FORMATION OFF ON ON OFF ON OFF MOC 27M Figure 3a. Contro Figure 3b. Transistor Contro 2k 2k 2N5551 2k VN2222LL 8V 2N51 8V 1MΩ 2MΩ 359 F3a Figure 3c. Opto-Isoator Contro 359 F3b 359 F3c Input Short-Circuit Fauts The dynamic behavior of an active, idea diode entering reverse bias is most accuratey characterized by a deay foowed by a period of reverse recovery. During the deay phase some reverse current is buit up, imited by parasitic resistances and inductances. During the reverse recovery phase, energy stored in the parasitic inductances is transferred to other eements in the circuit. Current sew rates during reverse recovery may reach 1A/µs or higher. High sew rates couped with parasitic inductances in series with the input and output paths may cause potentiay destructive transients to appear at the, SOURCE and pins of the during reverse recovery. A zero impedance short-circuit directy across the input and ground is especiay troubesome because it permits the highest possibe reverse current to buid up during the deay phase. When the MOSFET finay interrupts the reverse current, the and SOURCE pins experience a negative votage spike, whie the pin spikes in the positive direction. To prevent damage to the under conditions of input short-circuit, protect the, SOURCE and pins as shown in Figure. The and SOURCE pins are protected by camping to the pin with two TransZorbs or TVS. For input votages and greater, D is needed to protect the MOSFET s gate oxide during input shortcircuit conditions. Negative spikes, seen after the MOSFET turns off during an input short, are camped by D2, a TVS. D2 aows reverse inputs to whie keeping the MOSFET off and is not required if reverse-input protection V PUT PARASITIC DUCTANCE + REVERSE RECOVERY CURRENT FDMS8611 PUT PARASITIC DUCTANCE + V PUT SHORT D1 SMAT7A 7V D2 SMAJ2A D DDZ9699T SOURCE C 1.5µF C LOAD R1 359 F Figure. Reverse Recovery Produces Inductive Spikes at the, SOURCE and Pins. The Poarity of Step Recovery Is Shown Across Parasitic Inductances For more information 9

10 APPLICATIONS FORMATION is not needed. D1, a 7V TVS, protects and SOURCE in the positive direction during oad steps and overvotage conditions. can be protected by an output capacitor, C of at east 1.5µF, a TVS across the MOSFET or by the MOSFET s avaanche breakdown. Care must be taken if the MOSFET s avaanche breakdown is used to protect the pin. The MOSFET s BV DSS must be sufficienty ower than 1V, and the MOSFET s avaanche energy rating must be ampe enough to absorb the inductive energy. If a TVS across the MOSFET or the MOSFET avaanche is used to protect the pin, C can be reduced to 7nF. C and R1 preserve the fast turn off time when output parasitic inductance causes the and votages to drop quicky. Paraeing Suppies Mutipe s can be used to combine the outputs of two or more suppies for redundancy or for droop sharing, as shown in Figure 5. For redundant suppies, the suppy with the highest output votage sources most or a of the oad current. If this suppy s output is quicky shorted to ground whie deivering oad current, the fow of current temporariy reverses and fows backwards through the s MOSFET. The senses this reverse current and activates a fast pu-down to quicky turn off the MOSFET. If the other, initiay ower, suppy was not deivering any oad current at the time of the faut, the output fas unti the body diode of its ORing MOSFET conducts. Meanwhie, the charges the MOSFET gate with 1 unti the forward drop is reduced to 3mV. If this suppy was sharing oad current at the time of the faut, its associated ORing MOSFET was aready driven partiay on. In this case, the wi simpy drive the MOSFET gate harder in an effort to maintain a drop of 3mV. Droop sharing can be accompished if both power suppy output votages and output impedances are neary equa. The 3mV reguation technique ensures smooth oad sharing between outputs without osciation. The degree of sharing is a function of MOSFET R DS(ON), the output impedance of the suppies and their initia output votages. Load Switching and Inrush Contro By adding a second MOSFET as shown in Figure 6, the can be used to contro power fow in the forward direction whie retaining idea diode behavior in the reverse direction. The body diodes of and Q2 prohibit V A = PSA RTNA V B = PSB RTNB A FDMS8611 D2A SMAJ2CA SOURCE D2B SMAJ2CA SOURCE R1A B FDMS8611 R1B 359 F5 C A 1.5µF C B 1.5µF 1A BUS V 28V D1 SMAJ58A 58V D2 SMAJ2A ON OFF C1 1nF Q2 FQA1N1 R R3 1Ω SOURCE FDMS8611 D DDZ9699T R1 Figure 6. 28V Load Switch and Idea Diode with Reverse Input Protection 359 F6 C 1.5µF V 28V 1A C LOAD 1 Figure 5. Redundant Power Suppies For more information

11 APPLICATIONS FORMATION current fow when the MOSFETs are off. serves as the idea diode, whie Q2 acts as a switch to contro forward power fow. On/off contro is provided by the pin, and C1 and R may be added if inrush contro is desired. When is driven high and provided V >V + 3mV, sources 1 and graduay charges C1, puing up both MOSFET gates. Q2 operates as a source foower and I RUSH = 1 C LOAD C1 If V <V + 3mV, the wi be activated but hods and Q2 off unti the input exceeds the output by 3mV. In this way norma diode behavior of the circuit is preserved, but with soft starting when the diode turns on. When is pued ow, pus the MOSFET gates down quicky to SOURCE turning off both forward and reverse paths, and the input current is reduced to 9. V V SOURCE S S MOSFET S G DCB6 D 8 D 7 D 6 D 5 Figure 7a. Layout, DCB6 Package S D S D MOSFET S D G D F7a V V Whie C1 and R may be omitted if soft starting is not needed, R3 is necessary to prevent MOSFET parasitic osciations and must be paced cose to Q2. SOURCE Layout Considerations Connect the, SOURCE and pins as cose as possibe to the MOSFET source and drain pins. Keep the traces to the MOSFET wide and short to minimize resistive osses as shown in Figure 7. Pace surge suppressors and necessary transient protection components cose to the using short ead engths. For the DFN package, pin spacing may be a concern at votages greater than 3V. Check creepage and cearance guideines to determine if this is an issue. To increase the effective pin spacing between high votage and ground pins, eave the exposed pad connection open. Use no-cean fux to minimize PCB contamination. Figures 8 through 18 show typica appications of the. V A 1.2V V B 1.2V MS8 Figure 7b. Layout, MS8 Package SOURCE SOURCE A BSC11N3LS R1A B BSC11N3LS C A 7nF C B 7nF 359 F7b V 1.2V 2A C LOAD R1B 359 F8 Figure V Diode OR For more information 11

12 TYPICAL APPLICATIONS Si87DY 1W SOLAR PANEL SHUNT REGULATOR SOURCE + BATTERY LOAD 359 F9 Figure 9. Lossess Soar Pane Isoation ES1D.7µF D6 SMCJ15A 15V V 2V IPB2N25N3G V 2V 7A C LOAD V 8V IPB2N25N3G D DDZ9699T R2 2k V 8V 1A C LOAD D DDZ9699T 1M Q3* BSS126 *DEPLETION MODE TRANSISTOR D1 SMAT7A 7V D2 MMSZ5231B 5.1V SOURCE C 7nF D3 BZG3C75 75V 1nF D1 DDZ9699 SOURCE D3 DDZ972 15V D5 S1B 359 F1 R1 2k 359 F11 Figure 1. 8V Idea Diode with Reverse Input Protection Figure 11. 2V Idea Diode 12 For more information

13 TYPICAL APPLICATIONS V D2 SMAJ2CA OFF ON C1 1nF Q2 BSC28N6NS R SOURCE R3 1Ω BSC28N6NS C 7nF V 1A C LOAD D3 S1B PUT 8.2M UV = 1.8V 1M 2M LTC15 + HYST REF + D2 SMAJ2CA Q2 BSC28N6NS BSC28N6NS 1V DDZ9697T SOURCE R1 PUT 359 F13 C 1.5µF R1 359 F12 V GND Figure 12. Load Switch and Idea Diode with Reverse Input Protection Figure 13. Load Switch and Idea Diode with Precise Undervotage Lockout V D DDZ9699T FDMS8611 V 1A D1 SMAT7A 7V D2 SMAJ2A SOURCE C 1.5µF R1 359 F1 Figure 1. Idea Diode with Reverse Input Protection D6 SMAT7A 7V V 8V FDMS8611 D DDZ9699T V 8V 1A D1 SMAT7A 7V SOURCE C 7nF R1 359 F15 Figure 15. 8V Idea Diode without Reverse Input Protection For more information 13

14 TYPICAL APPLICATIONS V A 28V D1A SMAJ58A 58V D2A SMAJ2A Q2A FQA1N1 DA DDZ9699T A FDMS8611 V 28V 1A C LOAD SOURCE OFF ON C A 1.5µF R1A V B 28V D1B SMAJ58A 58V D2B SMAJ2A OFF ON Q2B FQA1N1 DB DDZ9699T SOURCE B FDMS8611 C B 1.5µF R1B 359 F16 Figure 16. Diode-OR with Seectabe Power Suppy Feeds and Reverse Input Protection V D1 SMAT7A 7V D2 SMAJ2A SOURCE BSC28N6NS FDD16AN8A 1mΩ SMAJ58A 58V C 7nF 1Ω V CC SNS FB LTC k.99k 22µF A PUT (CLAMPED AT 16V) UV EN 27V TO 6V DC SURVIVAL V TO 1V TRANSIENT SURVIVAL R1 OV GND TMR FLT.1µF 359 F17 Figure 17. Overvotage Protector and Idea Diode Bocks Reverse Input Votage 1 For more information

15 PACKAGE DESCRIPTION Pease refer to for the most recent package drawings. DCB Package 6-Lead Pastic DFN (2mm 3mm) (Reference LTC DWG # Rev A).7 ± ± ±.5 (2 SIDES) 2.15 ±.5 PACKAGE LE.25 ±.5.5 BSC 1.35 ±.5 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 2. ±.1 (2 SIDES) R =.115 TYP R =.5 TYP 6. ±.1 3. ±.1 (2 SIDES) 1.65 ±.1 (2 SIDES) P 1 BAR TOP MARK (SEE NOTE 6).2 REF.75 ±.5..5 P 1 NOTCH R.2 OR.25 5 CHAMFER (DCB6) DFN ±.5.5 BSC 1.35 ±.1 (2 SIDES) BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWG TO BE MADE A JEDEC PACKAGE LE M-229 VARIATION OF (TBD) 2. DRAWG NOT TO SCALE 3. ALL DIMENSIONS ARE MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT CLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR P 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE For more information 15

16 PACKAGE DESCRIPTION Pease refer to for the most recent package drawings. MS8 Package 8-Lead Pastic MSOP (Reference LTC DWG # Rev G).889 ±.127 (.35 ±.5) 5.1 (.21) M ( ).2 ±.38 (.165 ±.15) TYP.65 (.256) BSC 3. ±.12 (.118 ±.) (NOTE 3) (.25) REF RECOMMENDED SOLDER PAD LAY GAUGE PLANE.18 (.7).25 (.1) DETAIL A NOTE: 1. DIMENSIONS MILLIMETER/(CH) 2. DRAWG NOT TO SCALE 6 TYP.53 ±.152 (.21 ±.6) DETAIL A SEATG PLANE.9 ±.152 (.193 ±.6) 1.1 (.3) MAX (.9.15) TYP.65 (.256) BSC DIMENSION DOES NOT CLUDE MOLD FLASH, PROTRUSIONS OR BURRS. MOLD FLASH, PROTRUSIONS OR BURRS SHALL NOT EXCEED.152mm (.6") PER SIDE. DIMENSION DOES NOT CLUDE TERLEAD FLASH OR PROTRUSIONS. TERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.152mm (.6") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMG) SHALL BE.12mm (.") MAX 3. ±.12 (.118 ±.) (NOTE ).86 (.3) REF.116 ±.58 (. ±.2) MSOP (MS8) 213 REV G 16 For more information

17 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 8/13 Corrected pu-up current from 2 to 2.6 5, 6, 7, 8 Updated Figure Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection For more of its circuits information as described herein wi not infringe on existing patent rights. 17

18 TYPICAL APPLICATION BACKPLANE 8V PLUG- CARD FDB3632 LTC26 Hot Swap CONTROLLER V 1 DDZ9699T SOURCE 1.5µF + C HOLDUP SMAT7A 7V GND GND 359 F18 Figure 18. Input Diode for Suppy Hod-Up on Pug-In Card RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC352 Idea Diode Controer with Monitor Contros N-Channe MOSFET, V to 18V Operation LTC35 Negative Votage Diode-OR Controer Contros Two N-Channe MOSFETs, 1µs Turn-Off, 8V Operation and Monitor LTC355 Positive Votage Diode-OR Controer Contros Two N-Channe MOSFETs,.5µs Turn-Off, 8V Operation and Monitor LTC357 Positive High Votage Idea Diode Contros Singe N-Channe MOSFET,.5µs Turn-Off, 8V Operation Controer LTC358 5A Idea Diode Interna N Channe MOSFET, 9V to 26.5V Operation LT363-1/LT363-2 High Votage Surge Stopper Stops High Votage Surges, V to 8V, 6V Reverse Input Protection LT256-1/LT256-2 Positive High Votage Hot Swap Controers Active Current Limiting, Suppies from 1.8V to 8V Latch-Off and Automatic Retry Option LTC26 Positive High Votage Hot Swap With I 2 C and ADC, Suppies from 8.5V to 8V Controer LTC36 Surge Stopper with Idea Diode V to 8V Operation, V Reverse Input, 2V Reverse Output 18 Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA For more information (8) FAX: (8) LT 813 REV A PRTED USA LEAR TECHNOLOGY CORPORATION 212