4A, 12V Overvoltage Output Regulator Overvoltage Protector Regulates Output at 27V During Transient V OUT 80V INPUT SURGE. 4.99k DC-DC CONVERTER

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1 LT-1 Overvotage Protection Reguator and Inrush Limiter FEATURES n Stops High Votage Surges n Adjustabe Output Camp Votage n Overcurrent Protection n Wide Operation Range: V to V n Reverse Input Protection to V n Low Shutdown Current n Adjustabe Faut Timer n Contros N-Channe MOSFET n Shutdown Pin Withstands V to 1V n Faut Output Indication n Spare Ampifi er for Leve Detection Comparator or Linear Reguator Controer n Avaiabe in (mm mm) 1-Pin DFN or 1-Pin MSOP Packages APPLICATIONS n Automotive/Avionic Surge Protection n Hot Swap/Live Insertion n High Side Switch for Battery Powered Systems L, LT, LTC and LTM are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. DESCRIPTION The LT -1 surge stopper protects oads from high votage transients. It reguates the output during an overvotage event, such as oad dump in automobies, by controing the gate of an externa N-Channe MOSFET. The output is imited to a safe vaue thereby aowing the oads to continue functioning. The LT-1 aso monitors the votage drop between the and SNS pins to protect against overcurrent fauts. An interna ampifi er imits the current sense votage to mv. In either faut condition, a timer is started inversey proportiona to MOSFET stress. If the timer expires, the pin pus ow to warn of an impending power down. If the condition persists, the MOSFET is turned off. The spare ampifier may be used as a votage detection comparator or as a inear reguator controer driving an externa PNP pass transistor. Back-to-back FETs can be used in ieu of a Schottky diode for reverse input protection, reducing votage drop and power oss. A shutdown pin reduces the quiescent current to ess than during shutdown. TYPICAL APPLICATION 1V A, 1V Overvotage Output Reguator Overvotage Protector Reguates Output at V During Transient 1mΩ IRLR9 V OUT PUT SURGE k 1k IN+ 1Ω SNS GATE OUT LTDE-1 1k.99k DC-DC CONVERTER V/DIV V OUT V/DIV 1V 1V V CLAMP UNDERVOLTAGE TMR TA1.1μF FAULT 1ms/DIV TA1b 1

2 LT-1 ABSOLUTE MAXIMUM RATINGS (Notes 1 and ),... V to 1V SNS... V or V to +.V OUT,,,....V to V GATE (Note )....V to V OUT + 1V, TMR, IN+....V to V,,... ma Operating Temperature Range LTC-1... C to C LTI-1... C to C LTH-1... C to 1 C Storage Temperature Range DE1... C to 1 C MS... C to 1 C Lead Temperature (Sodering, 1 sec, MS1)... C PIN CONFIGURATION TOP VIEW TMR OUT GATE SNS IN DE PACKAGE 1-LEAD (mm mm) PLASTIC DFN T JMAX = 1 C, θ JA = C/W EXPOSED PAD (PIN 1) PCB CONNECTION OPTIONAL OUT GATE SNS 1 TOP VIEW 1 9 MS PACKAGE 1-LEAD PLASTIC MSOP T JMAX = 1 C, θ JA = 1 C/W TMR ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTCDE-1#PBF LTCDE-1#TRPBF 1 1-Lead (mm mm) Pastic DFN C to C LTIDE-1#PBF LTIDE-1#TRPBF 1 1-Lead (mm mm) Pastic DFN C to C LTHDE-1#PBF LTHDE-1#TRPBF 1 1-Lead (mm mm) Pastic DFN C to 1 C LTCMS-1#PBF LTCMS-1#TRPBF LTCNS 1-Lead Pastic MSOP C to C LTIMS-1#PBF LTIMS-1#TRPBF LTCNS 1-Lead Pastic MSOP C to C LTHMS-1#PBF LTHMS-1#TRPBF LTCNS 1-Lead Pastic MSOP C to 1 C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTCDE-1 LTCDE-1#TR 1 1-Lead (mm mm) Pastic DFN C to C LTIDE-1 LTIDE-1#TR 1 1-Lead (mm mm) Pastic DFN C to C LTHDE-1 LTHDE-1#TR 1 1-Lead (mm mm) Pastic DFN C to 1 C LTCMS-1 LTCMS-1#TR LTCNS 1-Lead Pastic MSOP C to C LTIMS-1 LTIMS-1#TR LTCNS 1-Lead Pastic MSOP C to C LTHMS-1 LTHMS-1#TR LTCNS 1-Lead Pastic MSOP C to 1 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifi cations, go to:

3 ELECTRICAL CHARACTERISTICS LT-1 The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = C. = 1V uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Votage Range V I CC Suppy Current V = FLOAT 1 1. ma V = V LTI-1, LTC-1 LTH-1 I R Reverse Input Current V SNS = = V, Open V SNS = = V = V ΔV GATE GATE Pin Output High Votage = V; (V GATE V OUT ) V V; (V GATE V OUT ) I GATE,UP GATE Pin Pu-Up Current V GATE = 1V; = 1V V GATE = V; = V I GATE,DN GATE Pin Pu-Down Current Overvotage, V = 1.V, V GATE = 1V Overcurrent, V SNS = 1mV, V GATE = 1V Shutdown Mode, V = V, V GATE = 1V V Pin Servo Votage V GATE = 1V; V OUT = 1V, LTI-1, LTC-1 V GATE = 1V; V OUT = 1V, LTH I Pin Input Current V = 1.V. 1 ΔV SNS Overcurrent Faut Threshod ΔV SNS = ( V SNS ), = 1V, LTI-1, LTC-1 ΔV SNS = ( V SNS ), = 1V, LTH-1 ΔV SNS = ( V SNS ), = V, LTI-1, LTC-1 ΔV SNS = ( V SNS ), = V, LTH-1 I SNS SNS Pin Input Current V SNS = = 1V to V 1 I LEAK, Pins Leakage Current, = V. Pin Leakage Current = V. I TMR TMR Pin Pu-up Current V TMR = 1V, V = 1.V, ( V OUT ) =.V V TMR = 1V, V = 1.V, ( V OUT ) = V V TMR = 1.V, V = 1.V V TMR = 1V, ΔV SNS = mv, ( V OUT ) =.V V TMR = 1V, ΔV SNS = mv, ( V OUT ) = V TMR Pin Pu-down Current V TMR = 1V, V = 1V, ΔV SNS = V 1... V TMR TMR Pin Threshods From High to Low, = V to V V GATE From Low to High, = V to V ΔV TMR Eary Warning Period From going Low to GATE going Low, = V to V 1 1 mv + IN+ Pin Threshod V I IN+ IN+ Pin Input Current + = 1.V. 1 V OL,, Pins Output Low I SINK = ma I SINK =.1mA I OUT OUT Pin Input Current V OUT = = 1V V OUT = = 1V, V = V ΔV OUT OUT Pin High Threshod ΔV OUT = V OUT ; From Low to High... V V Pin Threshod = 1V to V V..1 V I Pin Current V = V 1 t OFF(OC ) Overcurrent Turn Off Deay Time GATE From High to Low, ΔV SNS = 1mV μs t OFF(OV) Overvotage Turn Off Deay Time GATE From High to Low, V = 1.V. 1 μs ma ma V V ma ma ma V V mv mv mv mv V V V mv ma Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note : A currents into device pins are positive; a currents out of device pins are negative. A votages are referenced to uness otherwise specifi ed. Note : An interna camp imits the GATE pin to a minimum of 1V above the OUT pin. Driving this pin to votages beyond the camp may damage the device.

4 LT-1 TYPICAL PERFORMANCE CHARACTERISTICS uness otherwise noted. Specifi cations are at = 1V, T A = C I CC (Shutdown) vs I CC vs I CC (Shutdown) vs Temperature 1 VCC = SNS I CC () 1 I CC () I CC (ma) (V) G1 1 (V) G (V) G Current vs Temperature GATE Pu-Up Current vs vs Temperature GATE Pu-Up Current V = V V GATE = V OUT = 1V I () 1 I GATE () 1 1 I GATE () TEMPERATURE (C) G 1 (V) G 1 1 TEMPERATURE (C) G GATE Pu-Down Current vs Temperature OVERVOLTAGE CONDITION V = 1.V 1 1 GATE Pu-Down Current vs Temperature OVERCURRT CONDITION ΔV SNS = 1mV 1 1 ΔV GATE vs I GATE V OUT = 1V I GATE(DOWN) (ma) I GATE(DOWN) (ma) ΔV GATE (V) TEMPERATURE ( C) G 1 1 TEMPERATURE (C) G I GATE () G9

5 TYPICAL PERFORMANCE CHARACTERISTICS uness otherwise noted. Specifi cations are at = 1V, T A = C LT-1 ΔV GATE (V) 1 1 ΔV GATE vs Temperature ΔV GATE vs vs ( V OUT ) Overvotage TMR Current 1 IGATE = 1 = V = V ΔV GATE (V) T A = C T A = C T A = C I TMR () 1 OVERVOLTAGE CONDITION V OUT = V V TMR = 1V 1 1 TEMPERATURE (C) G1 I GATE = 1 V OUT = 1 (V) G11 1 V OUT (V) G1 Overcurrent TMR Current vs ( V OUT ) Warning Period TMR Current vs TMR Pu-Down Current vs Temperature OVERCURRT CONDITION V OUT = V V TMR = 1V 1 OVERVOLTAGE, EARLY WARNING PERIOD 1 V = 1.V V TMR = 1.V 1... V TMR = 1V I TMR () 1 1 I TMR () I TMR () V OUT (V) G1 1 (V) G1 1 1 TEMPERATURE (C) G1 V OL (V) Output Low Votage vs Current t OFF (ns) 1 Overvotage Turn-Off Time vs Temperature OVERVOLTAGE CONDITION V = 1.V t OFF (μs) Overcurrent Turn-Off Time vs Temperature OVERCURRT CONDITION ΔV SNS = 1mV CURRT (ma) G1 1 1 TEMPERATURE ( C) G TEMPERATURE (C) G1

6 LT-1 PIN FUNCTIONS (DE/MS) (Pin 11 DE Ony): Ampifi er Output. Open coector output of the auxiiary ampifier. It is capabe of sinking up to ma from V. The negative input of the ampifier is internay connected to a 1.V reference. (Pin 9/Pin ): Open-Coector Enabe Output. The pin goes high impedance when the votage at the OUT pin is above (.V), indicating the externa MOSFET is fuy on. The state of the pin is atched unti the OUT pin votage resets at beow.v and goes back up above V. The interna NPN is capabe of sinking up to ma of current from V to drive an LED or opto-couper. Exposed Pad (Pin 1 DE Ony): Exposed pad may be eft open or connected to device ground (). (Pin /Pin 1): Votage Reguator Feedback Input. Connect this pin to the center tap of the output resistive divider connected between the OUT pin and ground. During an overvotage condition, the GATE pin is servoed to maintain a 1.V threshod at the pin. This pin is camped internay to V. Tie to to disabe the OV camp. (Pin /Pin ): Open-Coector Faut Output. This pin pus ow after the votage at the TMR pin has reached the faut threshod of 1.V. It indicates the pass transistor is about to turn off because either the suppy votage has stayed at an eevated eve for an extended period of time (votage faut) or the device is in an overcurrent condition (current faut). The interna NPN is capabe of sinking up to ma of current from V to drive an LED or opto-couper. GATE (Pin /Pin ): N-Channe MOSFET Gate Drive Output. The GATE pin is pued up by an interna charge pump current source and camped to 1V above the OUT pin. Both votage and current ampifiers contro the GATE pin to reguate the output votage and imit the current through the MOSFET. (Pin 1/Pin 9): Device Ground. IN+ (Pin 1 DE Ony): Positive Input of the Auxiiary Ampifi er. This ampifier can be used as a eve detection comparator with externa hysteresis or inear reguator controing an externa PNP transistor. This pin is camped internay to V. Connect to ground if unused. OUT (Pin /Pin ): Output Votage Sense Input. This pin senses the votage at the source of the N-channe MOSFET and sets the faut timer current. When the OUT pin votage reaches.v away from, the pin goes high impedance. (Pin /Pin ): Shutdown Contro Input. The LT-1 can be shutdown to a ow current mode by puing the pin beow the shutdown threshod of.v. Pu this pin above 1.V or disconnect it and aow the interna current source to turn the part back on. The eakage current to ground at the pin shoud be imited to no more than 1 if no pu up device is used to turn the part on. The pin can be pued up to 1V or beow by V without damage. SNS (Pin /Pin ): Current Sense Input. Connect this pin to the output of the current sense resistor. The current imit circuit contros the GATE pin to imit the sense votage between and SNS pins to mv. At the same time the sense ampifier aso starts a current source to charge up the TMR pin. This pin can be pued beow by up to V, though the votage difference with the pin must be imited to ess than V. Connect to if unused. TMR (Pin 1/Pin 1): Faut Timer Input. Connect a capacitor between this pin and ground to set the times for eary warning, faut and coo down periods. The current charging up this pin during faut conditions depends on the votage difference between the and OUT pins. When V TMR reaches 1.V, the pin pus ow to indicate the detection of a faut condition. If the condition persists, the pass transistor turns off when V TMR reaches the threshod of 1.V. The pu up current stops and a current source starts to pu the TMR pin down as soon as the faut condition disappears. When V TMR reaches the retry threshod of.v, the GATE pin pus high turning back on the pass transistor. (Pin /Pin ): Positive Suppy Votage Input. The positive suppy input ranges from V to V for norma operation. It can aso be pued beow ground potentia by up to V during a reverse battery condition, without damaging the part. The suppy current is reduced to with a the functiona bocks off.

7 LT-1 BLOCK DIAGRAM SNS GATE OUT mv + + CHARGE PUMP 1V + IA VA 1.V IN+ + 1.V AUXILLARY AMPLIFIER OC RESTART OUT CONTROL LOGIC GATEOFF OV 1.V +.V + I TMR + 1.V TMR BD

8 LT-1 OPERATION Some power systems must cope with high votage surges of short duration such as those in automobies. Load circuitry must be protected from these transients, yet high avaiabiity systems must continue operating during these events. The LT-1 is an overvotage protection reguator that drives an externa N-channe MOSFET as the pass transistor. It operates from a wide suppy votage range of V to V. It can aso be pued beow ground potentia by up to V without damage. The ow power suppy requirement of V aows it to operate even during cod cranking conditions in automotive appications. The interna charge pump turns on the N-channe MOSFET to suppy current to the oads with very itte power oss. Two MOSFETs can be connected back to back to repace an inine Schottky diode for reverse input protection. This improves the efficiency and increases the avaiabe suppy votage eve to the oad circuitry during cod crank. Normay, the pass transistor is fuy on, powering the oads with very itte votage drop. When the suppy votage surges too high, the votage ampifier (VA) contros the gate of the MOSFET and reguates the votage at the source pin to a eve that is set by the externa resistor divider from the OUT pin to ground and the interna 1.V reference. A current source starts charging up the capacitor connected at the TMR pin to ground. If the votage at the TMR pin, V TMR, reaches 1.V, the pin pus ow to indicate impending turn-off due to the overvotage condition. The pass transistor stays on unti the TMR pin reaches 1.V, at which point the GATE pin pus ow turning off the MOSFET. The potentia at the TMR pin starts decreasing as soon as the overvotage condition disappears. When the votage at the TMR pin reaches.v the GATE pin begins rising, turning on the MOSFET. The pin wi then go to a high impedance state. The faut timer aows the oads to continue functioning during short transient events whie protecting the MOSFET from being damaged by a ong period of suppy overvotage, such as a oad dump in automobies. The timer period varies with the votage across the MOSFET. A higher votage corresponds to a shorter faut timer period, ensuring the MOSFET operates within its safe operating area (SOA). The LT-1 senses an overcurrent condition by monitoring the votage across an optiona sense resistor paced between the and SNS pins. An active current imit circuit (IA) contros the GATE pin to imit the sense votage to mv. A current is aso generated to start charging up the TMR pin. This current is about times the current generated during an overvotage event. The pin pus ow when the votage at the TMR pin reaches 1.V and the MOSFET is turned off when it reaches 1.V. A spare ampifier (SA) is provided with the negative input connected to an interna 1.V reference. The output pu down device is capabe of sinking up to ma of current aowing it to drive an LED or opto couper. This ampifier can be configured as a inear reguator controer driving an externa PNP transistor or a comparator function to monitor votages. A shutdown pin turns off the pass transistor and reduces the suppy current to ess than.

9 APPLICATIONS INFORMATION The LT-1 can imit the votage and current to the oad circuitry during suppy transients or overcurrent events. The tota faut timer period shoud be set to ride through short overvotage transients whie not causing damage to the pass transistor. The seection of this N-channe MOSFET pass transistor is critica for this appication. It must stay on and provide a ow impedance path from the input suppy to the oad during norma operation and then dissipate power during overvotage or overcurrent conditions. The foowing sections describe the overcurrent and the overvotage fauts, and the seection of the timer capacitor vaue based on the required warning time. The seection of the N-channe MOSFET pass transistor is discussed next. Auxiiary ampifi er, reverse input, and the shutdown functions are covered after the MOSFET seection. Externa component seection is discussed in detai in the Design Exampe section. Overvotage Faut The LTC-1 imits the votage at the OUT pin during an overvotage situation. An interna votage ampifier reguates the GATE pin votage to maintain a 1.V threshod at the pin. During this period of time, the power MOSFET is sti on and continues to suppy current to the oad. This aows uninterrupted operation during short overvotage transient events. When the votage reguation oop is engaged for onger than the time-out period, set by the timer capacitor connected from the TMR pin to ground, an overvotage faut is detected. The GATE pin is pued down to the OUT pin by a 1mA current. After the faut condition has disappeared and a coo down period has transpired, the GATE pin starts to pu high again. This prevents the power MOSFET from being damaged during a ong period of overvotage, such as during oad dump in automobies. Overcurrent Faut The LT-1 features an adjustabe current imit that protects against short circuits or excessive oad current. During an overcurrent event, the GATE pin is reguated to imit the current sense votage across the and SNS pins to mv. LT-1 An overcurrent faut occurs when the current imit circuitry has been engaged for onger than the time-out deay set by the timer capacitor. The GATE pin is then immediatey pued ow by a 1mA current to turning off the MOSFET. After the faut condition has disappeared and a coo down period has transpired, the GATE pin is aowed to pu back up and turn on the pass transistor. Faut Timer The LT-1 incudes an adjustabe faut timer pin. Connecting a capacitor from the TMR pin to ground sets the deay timer period before the MOSFET is turned off. The same capacitor aso sets the coo down period before the MOSFET is aowed to turn back on after the faut condition has disappeared. Once a faut condition, either overvotage or overcurrent, is detected, a current source charges up the TMR pin. The current eve varies depending on the votage drop across the drain and source terminas of the power MOSFET(V DS ), which is typicay from the pin to the OUT pin. This scheme takes better advantage of the avaiabe Safe Operating Area (SOA) of the MOSFET than woud a fixed timer current. The timer function operates down to = V across the whoe temperature range. Faut Timer Current The timer current starts at around with.v or ess of V DS, increasing ineary to with V of V DS during an overvotage faut (Figure 1). During an overcurrent faut, it starts at with.v or ess of V DS but increases to with V across the MOSFET (Figure ). This arrangement aows the pass transistor to turn off faster during an overcurrent event, since more power is dissipated during this condition. Refer to the Typica Performance Characteristics section for the timer current at different V DS in both overvotage and overcurrent events. When the votage at the TMR pin, V TMR, reaches the 1.V threshod, the pin pus ow to indicate the detection of a faut condition and provide warning to the oad of the impending power oss. In the case of an overvotage faut, the timer current then switches to a fixed. 9

10 LT-1 APPLICATIONS INFORMATION V TMR(V) I TMR = I TMR = V TMR(V) The interva between asserting ow and the MOSFET turning off is given by: t WARNING = C TMR 1mV µa This fi xed eary warning period aows the systems to perform necessary backup or house keeping functions before the power suppy is cut off. After V TMR crosses the 1.V threshod, the pass transistor turns off immediatey. Note that during an overcurrent event, the timer current is not reduced to after V TMR has reached 1.V threshod, since it woud engthen the overa faut timer period and cause more stress on the power MOSFET. As soon as the faut condition has disappeared, a current starts to discharge the timer capacitor to ground. When V TMR reaches the.v threshod, the interna charge pump starts to pu the GATE pin high, turning on the 1 t = 1ms/μF V DS = V (I TMR = ) t WARNING = ms/μf t = 9.ms/F TOTAL FAULT TIMER = t + t WARNING V DS = 1V (I TMR = ) t WARNING = ms/μf Figure 1. Overvotage Faut Timer Current V DS = V (I TMR = ) t = 1.ms/μF TOTAL FAULT TIMER = t + t WARNING V DS = 1V (I TMR = ) t WARNING =.ms/μf Figure. Overcurrent Faut Timer Current TIME F1. TIME t WARNING t =.ms/μf =.ms/μf F MOSFET. The TMR pin is then activey reguated to.v unti the next faut condition appears. The tota coo down timer period is given by: t COOL = C TMR.V µa MOSFET Seection The LT-1 drives an N-channe MOSFET to conduct the oad current. The important features of the MOSFET are on-resistance R DS(ON), the maximum drain-source votage V (BR)DSS, the threshod votage, and the SOA. The maximum aowabe drain-source votage must be higher than the suppy votage. If the output is shorted to ground or during an overvotage event, the fu suppy votage wi appear across the MOSFET. The gate drive for the MOSFET is guaranteed to be more than 1V and ess than 1V for those appications with higher than V. This aows the use of standard threshod votage N-channe MOSFETs. For systems with ess than V, a ogic eve MOSFET is required since the gate drive can be as ow as.v. The SOA of the MOSFET must encompass a faut conditions. In norma operation the pass transistor is fuy on, dissipating very itte power. But during either overvotage or overcurrent fauts, the GATE pin is servoed to reguate either the output votage or the current through the MOSFET. Large current and high votage drop across the MOSFET can coexist in these cases. The SOA curves of the MOSFET must be considered carefuy aong with the seection of the faut timer capacitor. Transient Stress in the MOSFET During an overvotage event, the LT-1 drives a series pass MOSFET to reguate the output votage at an acceptabe eve. The oad circuitry may continue operating throughout this interva, but ony at the expense of dissipation in the MOSFET pass device. MOSFET dissipation or stress is a function of the input votage waveform, reguation votage and oad current. The MOSFET must be sized to survive this stress. Most transient event specifications use the mode shown in Figure. The ideaized waveform comprises a inear

11 APPLICATIONS INFORMATION LT-1 V PK V PK τ τ V REG t r t r F F Figure. Prototypica Transient Waveform where, ΔV SNS is the SSE pin threshod, and t TMR is the overcurrent timer interva. For = 1.V, V SNS = mv, R SNS = 1mΩ and C TMR = 1nF, P t is.w s ess than the transient SOA cacuated in the previous exampe. Nevertheess, to acramp of rise time t r, reaching a peak votage of V PK and exponentiay decaying back to with a time constant of t. A common automotive transient specifi cation has constants of t r = 1μs, V PK = V and τ = 1ms. A surge condition known as oad dump has constants of t r = ms, V PK = V and τ = ms. MOSFET stress is the resut of power dissipated within the device. For ong duration surges of 1ms or more, stress is increasingy dominated by heat transfer; this is a matter of device packaging and mounting, and heatsink therma mass. For short duration transients of ess than 1ms, MOSFET surviva is increasingy a matter of safe operating area (SOA), an intrinsic property of the MOSFET. SOA quantifies the time required at any given condition of V DS and I D to raise the junction temperature of the MOSFET to its rated maximum. MOSFET SOA is expressed in units of watt-squared-seconds (P t). This figure is essentiay constant for intervas of ess than 1ms for any given device type, and rises to infinity under DC operating conditions. Destruction mechanisms other than buk die temperature distort the ines of an accuratey drawn SOA graph so that P t is not the same for a combinations of I D and V DS. In particuar P t tends to degrade as V DS approaches the maximum rating, rendering some devices useess for absorbing energy above a certain votage. Cacuating Transient Stress To seect a MOSFET suitabe for any given appication, the SOA stress must be cacuated for each input transient which sha not interrupt operation. It is then a simpe matter to chose a device which has adequate SOA to survive the maximum cacuated stress. P t for a prototypica transient waveform is cacuated as foows (Figure ). Figure. Safe Operating Area Required to Survive Prototypica Transient Waveform Let a = V REG b = V PK ( = Nomina Input Votage) Then ( b a) 1 P t = I t r + b LOAD 1 a n b a + a + b ab Typicay V REG and τ >> t r simpyfying the above to P t = 1 I LOAD ( ) τ (W s) V PK V REG For the transient conditions of V PK = V, = 1V, V REG = 1V, t r = 1μs and τ = 1ms, and a oad current of A, P t is 1.W s easiy handed by a MOSFET in a D-pak package. The P t of other transient waveshapes is evauated by integrating the square of MOSFET power versus time. Cacuating Short Circuit Stress SOA stress must aso be cacuated for short circuit conditions. Short circuit P t is given by: P t = ( ΔV SNS /R SNS ) t TMR (W s) 11

12 LT-1 APPLICATIONS INFORMATION count for circuit toerances this figure shoud be doubed to 1.W s. Limiting Inrush Current and GATE Pin Compensation The LT-1 imits the inrush current to any oad capacitance by controing the GATE pin votage sew rate. An externa capacitor can be connected from GATE to ground to sow down the inrush current further at the expense of sower turn-off time. The LTC-1 does not need extra compensation components at the GATE pin for stabiity during an overvotage or overcurrent event. However, with fast, high votage transient steps at the input, a gate capacitor, C1, to ground is needed to prevent turn-on of the N-Channe MOSFET. The extra gate capacitance sows down the turn off time during faut conditions and may aow excessive current during an output short event. An extra resistor, R1, in series with the gate capacitor can improve the turn off time. A diode, D1, shoud be paced across R1 with the cathode connected to C1 as shown in Figure. Auxiiary Ampifi er An uncommitted ampifier is incuded in the LT-1 to provide fexibiity in the system design. With the negative input connected internay to the 1.V reference, the ampifier can be connected as a eve detect comparator with externa hysteresis. The open coector output pin,, is capabe of driving an opto or LED. It can aso interface with the system via a pu-up resistor to a suppy votage up to V. The ampifi er can aso be configured as a ow dropout inear reguator controer. With an externa PNP transistor, such as N9A, it can suppy up to 1mA of current with ony a few hundred mv of dropout votage. Current imit can be easiy incuded by adding two diodes and one resistor (Figure ). INPUT R 1k D1* BAV99 *.Ω LTDE-1 N9A OR BCP Figure. Auxiiary LDO Output with Optiona Current Limit Reverse Input Protection A bocking diode is commony empoyed when reverse input potentia is possibe, such as in automotive appications. This diode causes extra power oss, generates heat, and reduces the avaiabe suppy votage range. During cod crank, the extra votage drop across the diode is particuary undesirabe. The LT-1 is designed to withstand reverse votage without damage to itsef or the oad. The, SNS, and pins can withstand up to V of DC votage beow the potentia. Back-to-back MOSFETs must be used to eiminate the current path through their body diodes (Figure ). Figure shows the approach with a P-Channe MOSFET in pace of Q. 11 OUTPUT * OPTIONAL FOR CURRT LIMIT F R Q1 GATE LT-1 Figure D1 IN1W R1 F C1 Shutdown The LT-1 can be shut down to a ow current mode when the votage at the pin goes beow the shutdown threshod of.v. The quiescent current drops to. The pin can be pued up to or beow by up to V without damaging the pin. Leaving the pin open aows an interna current source to pu it up and turn on the part whie camping the pin to.v. The eakage current at the pin shoud be imited to no more than 1 if no pu up device is used to hep turn it on. 1

13 LT-1 APPLICATIONS INFORMATION 1V D* SMAJCA C.1μF R 1Ω R SNS 1mΩ *DIODES INC. SNS 11 1 IN+ D1 1N1 Q N9 Q IRLR9 R 1k R 1Ω LTDE-1 Q1 IRLR9 C TMR.1μF V OUT 1V, A CLAMPED AT 1V Figure. Overvotage Reguator with N-Channe MOSFET Reverse Input Protection 1V D* SMAJCA C.1μF R SNS 1mΩ SNS 11 1 IN+ *DIODES INC. Q Si D1 1N 1V R 1k Figure. Overvotage Reguator with P-Channe MOSFET Reverse Input Protection Suppy Transient Protection The LT-1 is 1% tested and guaranteed to be safe from damage with suppy votages up to V. Nevertheess, votage transients above 1V may cause permanent damage. During a short-circuit condition, the arge change in current fowing through power suppy traces and associated wiring can cause inductive votage transients which coud exceed 1V. To minimize the votage transients, the TMR 1 1 LTDE-1 TMR 1 1 C TMR.1μF R 1M Q1 IRLR9 GATE R 1Ω GATE OUT R 1Ω OUT 9 F 9 F R1 9k R1 9k R.99k V OUT 1V, A CLAMPED AT 1V R.99k power trace parasitic inductance shoud be minimized by using wide traces. A snubber circuit dampens the ringing associated with votage spikes. A 1Ω resistor in series with a.1μf capacitor between and is effective with up to 1μH feed point inductance. A surge suppressor, D, in Figure 9, at the input wi camp the votage spikes. A 1μF ceramic capacitor, C L, is needed at the OUT pin to camp the votage spike if the input votage rise time is D SMAJA R k R 1k C.1μF 1V UNDERVOLTAGE R 1Ω 1 IN+ 11 R SNS 1mΩ SNS Q1 IRLR9 LTDE-1 R 1Ω GATE TMR 1 1 OUT C TMR nf 9 Figure 9. Overvotage Reguator with Low Battery Detection faster than 1μs. A tota buk capacitance in the range of μf is aso required cose to the pin of the DC/DC converter, if not aready provided by the converter. Layout Considerations To achieve accurate current sensing, Kevin connection to the current sense resistor (R SNS in Figure 9) is recommended. The minimum trace width for 1oz copper foi is." per amp to ensure the trace stays at a reasonabe temperature.." per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about μω/square. Sma resistances can cause arge errors in high current appications. Noise immunity wi be improved significanty by ocating resistive dividers cose to the pins with short and traces. F9 R1 9k R.99k FAULT DC-DC CONVERTER C L 1μF CERAMIC 1

14 LT-1 APPLICATIONS INFORMATION Design Exampe As a design exampe, take an appication with the foowing specifications: = V to 1V DC with transient up to V, V OUT 1V, current imit (I LIM ) at A, ow battery detection at V, and 1ms of overvotage eary warning (Figure 9). First, cacuate the resistive divider vaue to imit V OUT to 1V during an overvotage event: ( ) R 1.V R1 + R V REG = = 1V Set the current through R1 and R during the overvotage condition to. R = 1.V µa = k Choose.99kΩ for R. ( 1V 1.V) R R1 = =.k 1.V The cosest standard vaue for R1 is 9kΩ. Next cacuate the sense resistor, R SNS, vaue: R SNS = mv I LIM = mv A = 1m C TMR is then chosen for 1ms of eary warning time: C TMR = 1ms µa 1mV = nf The cosest standard vaue for C TMR is nf. Finay, cacuate R and R for the V ow battery threshod detection: V = ( ) R 1.V R + R Choose 1kΩ for R. ( V 1.V) R R = = k 1.V Seect kω for R. The pass transistor, Q1, shoud be chosen to withstand the output short condition with = 1V. The tota overcurrent faut time is: t OC = nf.v. =.ms The power dissipation on Q1 equas to: P = 1V mv 1m = W These conditions are we within the Safe Operating Area of IRLR9. 1

15 LT-1 TYPICAL APPLICATIONS V Overvotage Reguator Withstands 1V at V R9 1k 1W Q1 IRF R 1Ω V OUT CLAMPED AT V R1 11k SNS GATE OUT D* SMATA R.99k LTDE-1 9 TMR *DIODES INC. 1 1 C TMR.1μF TA 1

16 LT-1 TYPICAL APPLICATIONS Overvotage Reguator with Low Battery Detection and Output Keep Aive During Shutdown 1k.W 1V D* SMAJA R k C.1μF R 1Ω R 1k R SNS 1mΩ 1 IN+ SNS Q1 IRLR9 GATE R 1Ω LTDE-1 OUT Q VN 11 R1 9k R.9k D1 1NA 1V 1W V DD R k LBO C 1μF V OUT 1V, A CLAMPED AT 1V *DIODES INC. TMR 1 1 C TMR.1μF TA 9 1

17 TYPICAL APPLICATIONS LT-1.A, V Hot Swap with Overvotage Output Reguation at V and UV Shutdown at V V D* SMATA R S 1Ω C S.1μF D1 1N1 BV = V R k *DIODES INC. 9 R SNS 1mΩ R 1Ω LTDE-1 TMR 1 1 C1.nF SNS GATE OUT Q1 FDB C TMR.1μF IN+ TA 1 11 R 1k R 1M R.k R k R1 k R.k PWRGD V OUT V.A C L μf.a, V Hot Swap with Overvotage Output Reguation at V and UV Shutdown at 1V V D* SMATA R S 1Ω C S.1μF D1 1N BV = 1V R k *DIODES INC. 9 R SNS 1mΩ R 1Ω C1.nF SNS GATE OUT Q1 FDB LTDE-1 TMR 1 1 C TMR.1μF IN+ TA 1 11 R 11k R 1M R.k R k R1 11k R.k PWRGD V OUT V.A C L μf 1

18 LT-1 PACKAGE DESCRIPTION DE/UE Package 1-Lead Pastic DFN (mm mm) (Reference LTC DWG # --19 Rev C). ±.. ±.. ±. 1. ±. ( SIDES) PACKAGE OUTLINE. ±.. ±. ( SIDES). BSC RECOMMDED SOLDER PAD PITCH AND DIMSIONS. ±.1 ( SIDES) R =. TYP R =.11 TYP 1. ±.1 PIN 1 TOP MARK (NOTE ). REF. ±.1 ( SIDES). ±. 1. ±. ( SIDES)... ±.. ±. ( SIDES) BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M-9. DRAWING NOT TO SCALE. ALL DIMSIONS ARE IN MILLIMETERS. DIMSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PREST, SHALL NOT EXCEED.1mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1. BSC PIN 1 NOTCH R =. OR. CHAMFER (UE1/DE1) DFN 9 REV C 1

19 PACKAGE DESCRIPTION LT-1 MS Package 1-Lead Pastic MSOP (Reference LTC DWG # --11).9 ±.1 (. ±.). (.) MIN.. (.1.1). ±. (.1 ±.1) TYP. (.19) BSC RECOMMDED SOLDER PAD LAYOUT. ±.1 (.11 ±.) (NOTE ) ±. (.19 ±.) REF GAUGE PLANE.1 (.). (.1) DETAIL A DETAIL A NOTE: 1. DIMSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE TYP. ±.1 (.1 ±.) SEATING PLANE.9 ±.1 (.19 ±.) 1.1 (.) MAX.1. (..11) TYP 1. (.19) BSC. DIMSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.1mm (.") PER SIDE. DIMSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.1mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.1mm (.") MAX. ±.1 (.11 ±.) (NOTE ). (.) REF.11 ±. (. ±.) MSOP (MS) REV E Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 19

20 LT-1 TYPICAL APPLICATION Overvotage Reguator with Linear Reguator Up to 1mA 1V D* SMAJA Q N9A R 1k C.1μF R 1Ω R SNS 1mΩ SNS 11 Q1 IRLR9 GATE R 1Ω LTDE-1 OUT IN+ 1 R1 9k R.99k R 9k R 9k.V, 1mA C 1μF C nf V OUT 1V, A CLAMPED AT 1V *DIODES INC. TMR TA 1 1 C TMR.1μF 9 RELATED PARTS PART NUMBER DESCRIPTION COMMTS LT11-1/LT11- Positive High Votage Hot Swap Controers Active Current Limiting, Suppies From 9V to V LTC19 Overvotage Protection Controer ThinSOT Package,.V to V LTC1 High Effi ciency Synchronous Step-Down Output Faut Protection, 1-Pin SSOP Switching Reguator LTC1 No R SSE Wide Input Range Synchronous Step-Down Controer Up to 9% Effi ciency, V V,.V V OUT (.9)( ), I OUT Up to A LTC99 Tripe/Dua Inputs UV/OV Negative Monitor Pin Seectabe Input Poarity Aows Negative and OV Monitoring LTC91/LTC91 Singe/Dua UV/OV Votage Monitor Ads UV and OV Trip Vaues, ±1.% Threshod Accuracy LTC91 Quad UV/OV Monitor For Positive and Negative Suppies LTC/LTC-1 -Phase, Dua, Synchronous Controer V V,.V V OUT 1V LTC/LTC-1 Low I Q, Dua, Synchronous Controer V V,.V V OUT 1V, Quiescent Current LTC/LTC-1 Low I Q, Synchronous Step-Down Controer Singe Channe LTC/LTC-1 LT Low I Q, Synchronous Step-Down Controer V V, 1.V V OUT V, 1 Quiescent Current LT LT LTC Dua, khz, -Phase Sychronous Step-Down Controer Positive V Hot Swap Controer with Open-Circuit Detect Positive High Votage Hot Swap Controer with ADC and I C Dua 1 Phased Controers, V to V, 9% Duty Cyce, mm mm QFN-, SSOP- Packages Fodback Current Limiting, Open-Circuit and Overcurrent Faut Output, Up to V Suppy Wide Operating Range.V to V LT1 Idea MOSFET ORing Diode Externa N-channe MOSFETs Repace ORing Diodes, 1.V to V LTC Negative Votage Diode-OR Controer Contros Two N-Channe MOSFETs, 1μs Turn-Off, V Operation LTC Positive Votage Diode-OR Controer Contros Two N-Channe MOSFETs,.μs Turn-Off, V Operation Hot Swap, No R SSE and ThinSOT are trademarks of Linear Technoogy Corporation. LT REV C PRINTED IN USA Linear Technoogy Corporation 1 McCarthy Bvd., Mipitas, CA 9-1 () -19 FAX: () - LINEAR TECHNOLOGY CORPORATION