DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO. LT4256-1/LT Positive High Voltage Hot Swap Controllers FEATURES

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1 Positive High Voltage Hot Swap Controllers FEATURES Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from.8v to 8V Foldback Current Limiting Overcurrent Fault Detection Drives an External N-Channel MOSFET Programmable Supply Voltage Power-Up Rate Undervoltage Protection Latch Off Operation Mode (LT-) Automatic Retry (LT-) Available in an 8-Pin SO Package APPLIC S U Hot Board Insertion Electronic Circuit Breaker/Power Bussing Industrial High Side Switch/Circuit Breaker V/8V Industrial/Alarm Systems Ideally Suited for V, V and 8V Distributed Power Systems TYPICAL APPLIC U DESCRIPTIO U The LT -/LT- are high voltage Hot Swap TM controllers that allow a board to be safely inserted and removed from a live backplane. An internal driver drives an external N-channel MOSFET switch to control supply voltages ranging from.8v to 8V. The LT-/LT- features an adjustable analog foldback current limit. If the supply remains in current limit for more than a programmable time, the N-channel MOSFET shuts off and the output asserts low. The LT- automatically restarts after a time-out delay. The LT- latches off until the pin is cycled low. The output indicates when the output voltage rises above a programmed level. An external resistor string from provides programmable undervoltage protection. The LT can be used as an upgrade to LT designs. See Table on page for upgraded specifications. The LT- and LT- are available in an 8-pin SO package that is pin compatible with the LT. 8V Telecom Systems, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 8V, A Hot Swap Controller V IN 8V SMAT7A (SHORT PIN).9k.µF 8.k nf.ω 8 7 SENSE LT-/ LT- TIMER FB IRF CMPZB V Ω.k nf Ω = V = V.k 7k TA C L 8V A V IN V/DIV V/DIV INRUSH CURRENT ma/div V/DIV LT Start-Up Behavior C L = µf.ms/div TA

2 ABSOLUTE AXI U RATI GS W W W (Note ) Supply Voltage ( ).... to V SENSE,.... to V (Note )....V to + V Maximum Input Current ()... µa FB,.... to V TIMER....V to.v Maximum Input Current (TIMER)... µa Operating Temperature LTC... C to 7 C LTI... C to 8 C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C U U PACKAGE/ORDER I FOR FB TOP VIEW 8 7 S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = C/W SENSE TIMER U W ORDER PART NUMBER LT-CS8 LT-IS8 LT-CS8 LT-IS8 S8 PART MARKING I I Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. = 8V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage.8 8 V I CC Operating Current.8.9 ma V LH Undervoltage Threshold Low-to-High Transition.9. V V HYS Hysteresis... V I IN Input Current.V. µa = V. µa V RTH Fault Latch Reset Threshold Voltage..8. V V SENSETRIP SENSE Pin Trip Voltage ( V SENSE ) FB = V. mv FB V mv I INSNS SENSE Pin Input Current V SENSE = 7 µa I PU Pull-Up Current Charge Pump On, V = 7V µa I PD Pull-Down Current Any Fault, V = V 8 ma V External N-Channel Gate Drive (Note ) V,.8V V V V 8V..8 V V FB FB Voltage Threshold FB High-to-Low Transition V FB Low-to-High Transition... V V FBHYS FB Hysteresis Voltage... V V OLPGD Output Low Voltage I O =.ma.. V I O = ma. V I Pin Leakage Current V = 8V. µa I INFB FB Input Current FB =.V. µa I TIMERPU TIMER Pull-Up Current TIMER = V, During Fault 7 µa I TIMERPD TIMER Pull-Down Current TIMER = V. µa V THTIMER TIMER Shut-Down Threshold C TIMER = nf.. V D TIMER Duty Cycle (RETRY Mode).. %

3 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. = 8V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t PHL Low to Low.7 µs t PLH High to High C = 9 µs t PHLFB FB Low to Low.8 µs t PLHFB FB High to High. µs t PHLSENSE ( V SENSE ) High to Low V SENSE = 7mV µs Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : An internal clamp limits the pin to a minimum of V above. Driving this pin to a voltage beyond the clamp voltage may damage the part. TYPICAL PERFOR A CE CHARACTERISTICS otherwise noted. UW Specifications are at T A = C unless Thresholds vs Temperature SENSE Pin Regulation Voltage vs Temperature I CC vs. 8. THRESHOLDS (V) L-H THRESHOLD H-L THRESHOLD SENSE PIN REGULN VOLTAGE (mv) 8 FB > V FB = V I CC (ma) (V) G G G I CC vs Temperature Thresholds vs Temperature Output Voltage vs I. = 8V. I CC (ma).... THRESHOLDS (V)..... L-H THRESHOLD H-L THRESHOLD V (V) I (ma) G G G

4 TYPICAL PERFOR A CE CHARACTERISTICS otherwise noted. UW Specifications are at T A = C unless Pin Pull-Up Current vs Temperature Pin Pull-Down Current vs Temperature. Pin Current vs Pin Voltage PIN PULL-UP CURRENT (µa) PIN PULL-DOWN CURRENT (ma) I (µa) V (V) G7 G8 G9 V Voltage vs Temperature. V Voltage vs Temperature TIMER Pin Currents vs Temperature = 8V. PULL-DOWN CURRENT V VOLTAGE (V) 8 = V =.8V V VOLTAGE (V) = 8V = V = 8V I TIMER (µa) 8 PULL-UP CURRENT G G G ITIMER (µa).. 8 TIMER Pin Currents vs PULL-DOWN CURRENT PULL-UP CURRENT TIMER SHUTDOWN THRESHOLD (V) Timer Shutdown Threshold vs Temperature 7 8 (V) G 7 G

5 TYPICAL PERFOR A CE CHARACTERISTICS otherwise noted. UW Specifications are at T A = C unless. FB Pin Current vs FB Pin Voltage Gate Pull-Down Capability vs Below Minimum Operating Voltage. I FB (µa).. I (ma ).. V FB (V) 8 (V) G G

6 PI FU CTIO S U U U (Pin ): Undervoltage Sense. is an input that enables the output voltage. When is driven above V, will start charging and the output turns on. When goes below.v, discharges and the output shuts off. Pulsing low for a minimum of µs after a current limit fault cycle resets the fault latch (LT-) and allows the part to turn back on. This command is only accepted after TIMER has discharged below.v. To disable sensing, connect to a voltage beween V and V. FB (Pin ): Power Good Comparator Input. FB monitors the output voltage through an external resistive divider. When the voltage on FB is lower than the high-to-low threshold of.99v, is pulled low and released when FB is pulled above the.v low-to-high threshold. The voltage present on FB affects foldback current limit (see Figure 7 and related discussion). (Pin ): Power Good Output. is pulled low whenever the voltage on FB falls below the.99v highto-low threshold voltage. It goes into a high impedance state when the voltage on FB exceeds the low-to-high threshold voltage. An external pull-up resistor can pull to a voltage higher or lower than. (Pin ): Device Ground. This pin must be tied to a ground plane for best performance. TIMER (Pin ): Timing Input. An external timing capacitor from TIMER to programs the maximum time the part is allowed to remain in current limit. When the part goes into current limit, a µa pull-up current source starts to charge the timing capacitor. When the voltage on TIMER reaches.v (typ), pulls low; the TIMER pull-up current will be turned off and the capacitor is discharged by a µa pull-down current. When TIMER falls below.v (typ), turns on again for the LT-. must be cycled low after TIMER has discharged below.v (typ) to reset the LT-. If is not cycled low (LT-), remains latched off and TIMER is discharged to near. Under an output short-circuit condition, the LT- cycles on and off with a % duty cycle. (Pin ): High Side Gate Drive for the External N- Channel MOSFET. An internal charge pump guarantees at least V of gate drive for supply voltages above V and.v of gate drive for supply voltages between.8v and V. The rising slope of the voltage on is set by an external capacitor connected from to and an internal µa pull-up current source from the charge pump output. If the current limit is reached, the voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. If the TIMER voltage ever exceeds.v, is pulled low. is also pulled to whenever is pulled low, the supply voltage drops below the externally programmed undervoltage threshold, or drops below the internal LO threshold (9.8V). is clamped internally to a maximum voltage of.v (typ) above under normal operating conditions. Driving this pin beyond the clamp voltage may damage the part. A Zener diode is needed between the gate and source of the external MOSFET to protect its gate oxide under instantaneous short-circuit conditions. See Applications Information. SENSE (Pin 7): Current Limit Sense Input. A sense resistor is placed in the supply path between and SENSE. The current limit circuit regulates the voltage across the sense resistor ( SENSE) to mv while in current limit when FB is V or higher. If FB drops below V, the regulated voltage across the sense resistor decreases linearly to mv when FB is V. To defeat current limit, connect SENSE to. (Pin 8): Input Supply Voltage. The positive supply input ranges from.8v to 8V for normal operation. I CC is typically.8ma. An internal circuit disables the LT-/LT- for inputs less than 9.8V (typ).

7 BLOCK DIAGRA W SENSE 8 7 V P GEN V P FB REF GEN.99V V + FOLDBACK mv ~ mv CURRENT LIMIT +.99V + CHARGE PUMP AND DRIVER 9.8V.V INTERNAL + + V + LOGIC TIMER LOW V P 8µA +.V TIMER HIGH TIMER µa BD 7

8 TEST CIRCUIT 8k 8V + FB SENSE pf TIMER F Figure TI I G DIAGRA S U W W V.V FB.V.99V t PLH t PHL t PLHFB t PHLFB +V +V F V V F Figure. to Timing Figure. to Timing SENSE mv t PHLSENSE F Figure. SENSE to Timing APPLIC S I FOR Hot Circuit Insertion 8 U W U U When circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. The transient currents can permanently damage the connector pins and glitch the system supply, causing other boards in the system to reset. The LT-/LT- are designed to turn on a board s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. Power-Up Sequence An external N-channel MOSFET pass transistor (Q) is placed in the power path to control the power up of the supply voltage (Figure ). Resistor R provides current detection and capacitor C controls the slew rate. Resistor R7 compensates the current control loop while R prevents high frequency oscillations in Q.

9 APPLIC S I FOR U W U U V IN 8V (SHORT PIN) C.µF D SMAT7A R.9k R 8.k R.Ω 8 7 SENSE LT-/ LT- FB C TIMER nf Q IRF R Ω R7 Ω C nf = V = V D CMPZB V R8.k R9.k + R 7k F C L 8V.A Figure. ma, 8V Application When the power pins first make contact, transistor Q is held off. If the voltage on is above the externally programmed undervoltage threshold, is above 9.8V, and the voltage on TIMER is less than.v (typ), transistor Q will be turned on (Figure ). The voltage on rises with a slope equal to µa/c and the supply inrush current is set at: I INRUSH = C L µa/c () where C L is the total load capacitance. To reduce inrush current, increase C or decrease load capacitance. If the voltage across the current sense resistor R reaches V SENSETRIP, the inrush current will be limited by the internal current limit circuitry. The voltage on is adjusted to maintain a constant voltage across the sense resistor and TIMER begins to charge. When the FB voltage goes above the low-to-high V FB threshold, goes high. Undervoltage Detection The LT-/LT- uses to monitor the voltage to determine when it is safe to turn on the load and allow the user the greatest flexibility for setting the threshold. Any time that goes below.v, will be pulled low until goes above V again. The threshold should never be set below the internal LO threshold (9.8V typically) because the benefit of s hysteresis will be lost, making the LT-/ I OUT ma/div Figure. Start-Up Waveforms LT- more susceptible to noise ( must be at least 9.8V when is at its.v threshold). is filtered with C to prevent noise spikes and capacitively coupled glitches from shutting down the LT-/LT- output erroneously. To calculate the threshold, use the following equations: VTHLH R= R V kω R + R kω V V/DIV V/DIV V/DIV THLH C L = µf R =. + R ms/div F where V THLH is the desired threshold voltage when is rising (L-H), etc. () () () 9

10 APPLIC S I FOR V SENSE U W U U mv mv RESPONSE TIME (µs) 8 V V FB F7 F8 V SENSE (mv) Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage Figure 8. Response Time to Overcurrent Figure shows how the LT-/LT- are commanded to shut off with a logic signal. This is accomplished by pulling the gate of the open-drain MOSFET, Q, (tied to the pin) high. Short-Circuit Protection The LT-/LT- features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. The current limit is set by placing a sense resistor (R) between and SENSE. The current limit threshold is calculated as: I LIMIT = mv/r () where R is the sense resistor. To limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed internally on FB. If the LT-/LT- go into current limit when the voltage on FB is V, the current limit circuit drives the pin to force a constant mv drop across the sense resistor. As the output at FB increases, the voltage across the sense resistor increases until the FB pin reaches V, at which point the voltage across the sense resistor is held constant at mv (see Figure 7). For a.ω sense resistor, the current limit is set at ma and folds back to ma when the output is shorted to ground. Thus, MOSFET peak power dissipation under short-circuit conditions is reduced from.w to.w. See the Layout Considerations section for important information about board layout to minimize current limit threshold error. The LT-/LT- also features a variable overcurrent response time. The time required for the part to regulate the voltage is a function of the voltage across the sense resistor connected between and SENSE. This helps to eliminate sensitivity to current spikes and transients that might otherwise unnecessarily trigger a current limit response and increase MOSFET dissipation. Figure 8 shows the response time as a function of the overdrive at SENSE. TIMER TIMER provides a method for programming the maximum time the part is allowed to operate in current limit. When the current limit circuitry is not active, the TIMER pin is pulled to by a µa current source. When the current limit circuitry becomes active, a 8µA pull-up current source is connected to TIMER and the voltage will rise with a slope equal to µa/c TIMER as long as the circuitry stays active. Once the desired maximum current limit time is known, the capacitor value is: C [ nf ] A t [ ms ]; µ = C =. V t ()

11 APPLIC S I FOR U W U U I OUT ma/div I OUT ma/div TIMER V/DIV TIMER V/DIV V/DIV V/DIV V/DIV V/DIV ms/div F9 ms/div F Figure 9. LT- Current Limit Waveforms When the TIMER pin reaches.v (typ), the internal fault latch is set causing to be pulled low and TIMER to be discharged to by the µa current source. The part is not allowed to turn on again until the voltage on TIMER falls below.v (typ). TIMER must never be pulled high by a low impedance because whenever TIMER rises above the upper threshold (typically.v) the pin characteristics change from a high impedance current source to a low impedance. Whenever is commanded off by any fault condition, it is discharged rapidly, turning off the external MOSFET. The waveform in Figure 9 shows how the output latches off following a current fault (LT-). The drop across the sense resistor is held at mv as the timer ramps up. Once TIMER reaches its shutdown threshold (.V typically), the circuit latches off. The LT- latches off after a current limit fault. After the LT- latches off, the part may be commanded to Figure. LT- Current Limit Waveforms start back up. This is accomplished by cycling to ground and then back high (this command can only be accepted after TIMER discharges back below the.v typical threshold, to prevent overheating transistor Q). Automatic Restart The LT- will automatically restart after an overcurrent fault. These waveforms are shown in Figure. The LT- functionality is as follows: When an overcurrent condition occurs, the pin is servoed to maintain a constant voltage across the sense resistor, and the capacitor C at the TIMER pin will begin to charge. When the voltage at the TIMER pin reaches.v (typ), the pin is pulled low. When the voltage at the TIMER pin ramps back down to.v (typ), the LT- turns on again. If the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. The duty cycle under short-circuit conditions is % which prevents Q from overheating.

12 APPLIC S I FOR U W U U OFF SIGNAL FROM MPU V IN 8V (SHORT PIN) VN Q C.µF D SMAT7A R.9k R 8.k R.Ω 8 7 SENSE LT-/ LT- Q IRF R Ω R7 Ω C nf D CMPZB V R8.k 8V A C L FB R9.k R k C nf TIMER = V = V F7 Figure. How to Use a Logic Signal to Control LT Turn-On/-Off V IN (SHORT PIN) C.µF D SMAT7A R.9k R 8.k R mω 8 7 SENSE LT-/ LT- FB Q IRF R Ω R7 Ω C nf R9.k D CMPZB V R8.k R 7k R 7k C L V LOGIC C nf TIMER = V = V F Q N9 Figure. Active Low Enable Application Power Good Detection The LT-/LT- includes a comparator for monitoring the output voltage. The output voltage is sensed through the FB pin via an external resistor string. The comparator s output () is an open collector capable of operating from a pull-up as high as 8V. can be used to directly enable/disable a power module with an active high enable input. Figure shows how to use to control an active low enable input power module. Signal inversion is accomplished by transistor Q and R. The thresholds for the FB pin are.v (low to high) and.99v (high to low). To calculate the thresholds, use the following equations: R8= V TH R9, high to low (7) 99. V kω R8 + R9 kω (8a) V =.V + R8 TH, low to high R9 (8b)

13 APPLIC S I FOR Supply Transient Protection The LT-/LT- is % tested and guaranteed to be safe from damage with supply voltages up to 8V. However, voltage transients above V may cause permanent damage. During a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed V. To minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a.µf bypass capacitor should be placed between and. A surge suppressor, as shown in the application diagrams, (Transzorb) at the input can also prevent damage from voltage transients. Pin A curve of gate drive vs is shown in Figure. is clamped to a maximum voltage of.8v above. This clamp is designed to sink the internal charge pump current. An external Zener diode must be used as shown in all applications. At a minimum input supply voltage of V, the minimum gate drive voltage is.v. When the input supply voltage is higher than V, the gate drive voltage is at least V and a standard threshold MOSFET can be used. In applications from V to V range, a logic level MOSFET must be used. In some applications it may be possible for the pin to ring below ground (due to the parasitic trace inductance). U W U U Higher current applications, especially where the output load is physically far away from the LT-/LT- will be more susceptible to these transients. This is normal and the LT-/LT- have been designed to allow for some ringing below ground. However, if the application is such that can ring more than V below ground, damage may occur to the LT- and an external diode from ground (anode) to (cathode) must be added to the circuit as shown in Figure (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected voltage). A capacitor placed from ground to directly at the LT-/ LT- can help reduce the amount of ringing on but it may not be enough for some applications. During a fault condition, the LT-/LT- pulls down on with a switch capable of sinking about ma. Once drops below the output voltage by a diode forward voltage, the external Zener will forward bias and will also be discharged to. In addition to the capacitance, the output capacitance will be discharged through the LT-/LT-. In applications utilizing very large external N-channel MOSFETs, the possibility exists for the MOSFET to turn on when initially inserted into a live backplane (before the LT-/LT- becomes active and pulls down on ). This is due to the drain to gate capacitance forcing current into R7 and C when the drain voltage steps up from ground to V IN with an extremely fast rise time. To alleviate this situation, a diode, D, should be put across R7 with the cathode connected to C as shown in Figure. V (V) (V) F Figure. V vs

14 APPLIC S I FOR U W U U V IN (SHORT PIN) C.µF D SMAT7A R.9k R 8.k R.Ω 8 7 SENSE LT-/ LT- FB Q IRF R Ω R7 Ω C nf D CMPZB V R8.k R9.k R 7k C L µf D MRAT C nf TIMER = V = V F Figure. Negative Output Voltage Protection Diode Application Notes on Using the LT in LT Applications Even though the LT and LT have the same pinout, several changes were made to improve overall system accuracy and increase noise immunity. These changes are spelled out in Table and must be accounted for if using the LT in an LT application. Layout Considerations To achieve accurate current sensing, a Kelvin connection to the current sense resistor (R in typical application circuit) is recommended. The minimum trace width for oz copper foil is." per amp to make sure the trace stays at a reasonable temperature.." per amp or wider is recommended. Note that oz copper exhibits a sheet resistance of about µω/. Small resistances can cause large errors in high current applications. Noise immunity will be improved significantly by locating resistor dividers close to the pins with short and traces. A.µF decoupling capacitor from to is also required. Table. Differences Between LT and LT SPECIFICN LT LT COMMENTS Threshold.V V Higher % Reference for Better Noise Immunity and System Accuracy FB Threshold.V.99V Higher % Reference for Better Noise Immunity and System Accuracy TIMER Current ±7% ±% More Accurate TIMEOUT TIMER Shutdown V.V.V Higher Trip Voltage for Better Noise Immunity I PU µa µa Higher Current to Accommodate Higher Leakage MOSFETs or Parallel Devices Resistor kω Ω Different Compensation for Current Limit Loop Foldback I LIM mv mv Slightly Different Current Limit Trip Point I LIM Threshold 7mV mv Slightly Different Current Limit Trip Point Fault Latch Reset.V.8V Better Noise Immunity Threshold Voltage

15 PACKAGE DESCRIPTIO U S8 Package 8-Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # -8-). BSC. ± (.8.) NOTE 8 7. MIN. ±..8. (.79.97)..7 (.8.988) NOTE. ±. TYP RECOMMENDED SOLDER PAD LAYOUT.8. (..).. (..8) 8 TYP..9 (..7).. (..).. (..7) NOTE: INCHES. DIMENSIONS IN (MILLIMETERS)..9 (..8) TYP. DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED." (.mm). (.7) BSC SO8 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

16 APPLIC S I FOR U W U U V IN (SHORT PIN) C.µF D SMAT7A R.9k R 8.k R.Ω 8 7 SENSE LT-/ LT- FB C TIMER nf Q IRF R Ω R7 Ω C nf = V = V D CMPZB V D N8W R8.k R9.k TA R 7k C L µf Figure. High dv/dt MOSFET Turn-On Protection Circuit RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT-/LT- Positive 8V Hot Swap Controller in SO-8 9V to 8V Operation, Active Current Limit, Autoretry/Latchoff LTC Single Hot Swap Controller with Multifunction Current Control.V to.v, Active Inrush Limiting, Dual Level Cicuit Breaker LTC 8V Hot Swap Controller in SOT- Floating Supply from V, Active Current Limiting, Fast Circuit Breaker LTC-/LTC- 8V Hot Swap Controller in MSOP Floating Supply from V, Active Current Limiting, Power Good Output LTC 8V Hot Swap Controller and Supply Sequencer Floating Supply from V, Active Current Limiting, Enables Three DC/DC Converters LT Positive High Voltage Hot Swap Controller.8V to V, Open-Circuit Detection Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9-77 (8) -9 FAX: (8) -7 LT/LWI/LT 7 REV A PRINTED IN USA LINEAR TECHNOLOGY CORPORN