FEATURES DESCRIPTIO TYPICAL APPLICATIO. LT Positive High Voltage Hot Swap Controller with Open-Circuit Detect APPLICATIO S

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1 FEATURES Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from.v to V Foldback Current Limiting Open Circuit and Overcurrent Fault Detect Drives an External N-Channel MOSFET Automatic Retry or Latched Off Operation After Overcurrent Fault Programmable Supply Voltage Power-Up Rate Open MOSFET Detection % Over and Undervoltage Detection Accuracy Available in a 6-Lead SSOP Package APPLICATIO S U LT6-3 Positive High Voltage Hot Swap Controller with Open-Circuit Detect DESCRIPTIO The LT 6-3 is a high voltage Hot Swap TM controller that allows a board to be safely inserted and removed from a live backplane. An internal driver controls the high side N-channel MOSFET gate for supply voltages ranging from.v to V. The part features an open-circuit detect () output that indicates abnormally low load current conditions. The LT6-3 also features an adjustable analog foldback current limit. If the supply remains in current limit for more than a programmable time, the N-channel MOSFET shuts off, the PWRGD output asserts low and the LT6-3 either automatically restarts after a time-out delay or latches off until the pin is cycled low (depending on the status of the RETRY pin). The PWRGD output indicates when the output voltage rises above a programmed level. An external resistor string from provides programmable undervoltage and overvoltage protection. The LT6-3 is available in a 6-lead SSOP package. Hot Board Insertion Electronic Circuit Breaker/Power Bussing Industrial High Side Switch/Circuit Breaker V/V Industrial/Alarm Systems Ideally Suited for V, V and V Distributed Power Systems, LTC and LT are registered trademarks of Linear Technology Corporation. V Telecom Systems U Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO U V, A Hot Swap Controller V IN V (SHORT PIN).µF.Ω SMATA 6.9k SENSE LT6-3 PWRGD TIMER RETRY 33nF Ω IRF nf Ω CMPZBS V = 36V = 3V PWRGD = V 36.k k 6 TA C L PWRGD V A V IN V/DIV V/DIV INRUSH CURRENT ma/div PWRGD V/DIV LT6-3 Start-Up Behavior CONTACT BOUNCE C L = µf.ms/div 63 TA

2 ABSOLUTE AXI U RATI GS W W W (Note ) Supply Voltage ( )....3 to V SENSE, PWRGD....3 to V Voltage (Note )....3V to V Maximum Current... µa... 3V to V,,....3 to V....3 to V RETRY....3 to V TIMER Voltage....3V to.3v Maximum Input Current (TIMER)... µa Operating Temperature LT6-3C... C to C LT6-3I... C to C Storage Temperature Range... 6 C to C Lead Temperature (Soldering, sec)... 3 C U U U W PACKAGE/ORDER I FOR ATIO NC PWRGD NC RETRY 3 6 TOP VIEW 6 SENSE NC 3 NC 9 TIMER GN PACKAGE 6-LEAD PLASTIC SSOP T JMAX = C, θ JA = 3 C/W ORDER PART NUMBER LT6-3CGN LT6-3IGN GN PART MARKING 63 63I Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. Note: NC is a pin that is Not Connected. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage. V I CC Operating Current. 3.9 ma V LH Undervoltage Threshold Low-to-High Transition V V HYS Hysteresis... V I IN Input Current.V. µa = V. 3 µa V RTH Fault Latch Reset Threshold Voltage... V V LH Overvoltage Threshold Low-to-High Transition V V HYS Hysteresis... V I IN Input Current V < V. µa V Open-Circuit Voltage Threshold ( V SENSE ) mv V OL Output Low Voltage I O = ma.. V I O = ma..3 V I IN Leakage Current V = V. µa V SENSETRIP SENSE Pin Trip Voltage ( V SENSE ) = V mv V 6 mv I INSNS SENSE Pin Input Current V SENSE = µa I PU Pull-Up Current Charge Pump On, V = V µa I PD Pull-Down Current Any Fault, V > 6 ma I PDL Pull-Down Current, Fault Condition Any Fault, V = V L, 3 µa = V V External N-Channel Gate Drive (Note ) V,.V V... V V V.6. V V L External N-Channel Gate Drive, Fault Condition V, = V V

3 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Voltage Threshold High-to-Low Transition V Low-to-High Transition...6 V V HYS Hysteresis Voltage.3..6 V V OLPGD PWRGD Output Low Voltage I O =.6mA.. V I O = ma.6. V I PWRGD PWRGD Pin Leakage Current V PWRGD = V. µa I IN Input Current =.V. µa I TIMERPU TIMER Pull-Up Current TIMER = 3V, During Fault 63 µa I TIMERPD TIMER Pull-Down Current TIMER = 3V. 3 µa V THTIMER TIMER Shutdown Threshold C TIMER = nf.3.6 V D TIMER Duty Cycle (RETRY Mode). 3. % V RETRYTH RETRY Threshold... V I INRTR RETRY Input Current RETRY = 3 µa t PHL Low to Low C = pf. 3 µs t PLH High to High C = pf 6 9 µs t PHL Low to PWRGD Low. µs t PLH High to PWRGD High 3. µs t PHLSENSE ( V SENSE ) High to Low V SENSE = mv 3 µs Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : An internal clamp limits the pin to a minimum of V above. Driving this pin to a voltage beyond the clamp voltage may damage the part. TYPICAL PERFOR A CE CHARACTERISTICS UW Specifications are at T A = C unless otherwise noted. SENSE Regulation Voltage vs Temperature I CC vs I CC vs Temperature SENSE REGULATION VOLTAGE (mv) 3 > V = V I CC (ma) I CC (ma)..... = V 3 6 (V) 63 G 63 G 63 G3 3

4 TYPICAL PERFOR A CE CHARACTERISTICS UW Specifications are at T A = C unless otherwise noted. Pull-Up Current vs Temperature 63 Pull-Down Current vs Temperature 6 Pull-Down Capability vs Below Minimum Operating Voltage PULL-UP CURRENT (µa) 3 3 C PULL-DOWN CURRENT (ma) I (ma ) (V) 63 G 63 G 63 G V Voltage vs Temperature. V Voltage vs Temperature. TIMER Currents vs Temperature V VOLTAGE (V) 6 = V = V =.V V VOLTAGE (V) = V = V = V I TIMER (µa). PULL-DOWN CURRENT PULL-UP CURRENT. 63 G6 63 G 63 G ITIMER (µa).. TIMER Currents vs PULL-DOWN CURRENT PULL-UP CURRENT TIMER SHUTDOWN THRESHOLD (V) TIMER Shutdown Threshold vs Temperature I (µa) Current vs Voltage 3 6 (V). 3 3 V (V) 63 G9 63 G 63 G

5 TYPICAL PERFOR A CE CHARACTERISTICS UW Specifications are at T A = C unless otherwise noted.. Thresholds vs Temperature Current vs Voltage. Thresholds vs Temperature. L-H THRESHOLD. L-H THRESHOLD THRESHOLDS (V) I (µa) THRESHOLDS (V) H-L THRESHOLD 3.6 H-L THRESHOLD 3. V (V) G 63 G9 63 G Output Voltage vs I. Threshold Voltage vs Temperature 6 PWRGD Output Voltage vs I PWRGD V (V) THRESHOLD VOLTAGE (mv) V SENSE V PWRGD (V) 3 6 I (ma) 6 I PWRGD (ma) 63 G3 63 G 63 G. Thresholds vs Temperature. Current vs Voltage. L-H THRESHOLD. THRESHOLDS (V).3.. I (µa)... H-L THRESHOLD V (V) 63 G6 63 G

6 PI FU CTIO S U U U (Pin ): Undervoltage Sense Input. is an input that enables the output voltage. When is driven above V, will start charging and the output turns on. When goes below 3.6V, discharges and the output shuts off. Pulsing to below.v for at least µs after a current limit fault cycle resets the fault latch (when RETRY pin is low, commanding latch off operation) and allows the part to turn back on. This command is only accepted after TIMER is discharged below.6v. To disable sensing, connect the pin to a voltage between V and V. (Pin ): Overvoltage Sense Input. is an input that disables the output voltage. If ever goes above V, is discharged and the output shuts off. When goes below 3.6V, starts charging and the output turns back on. To disable overvoltage sensing, connect pin to ground. NC (Pins 3, 6,, ): No Connect. Not connected to any internal circuitry. (Pin ): Open Circuit Detect Output. This pin is an open collector output that releases and is pulled high through an external resistor if the load current is less than (3mV)/R. PWRGD (Pin ): Power Good Output. PWRGD is pulled low whenever the voltage on falls below the high-to-low threshold voltage. It goes into a high impedance state when the voltage on exceeds the low-to-high threshold voltage. An external pull-up resistor can pull PWRGD to a voltage higher or lower than. RETRY (Pin ): Current Fault Retry Input. RETRY commands the operational mode of the current limit. If RETRY is floating, the LT6-3 automatically restarts after a current fault. If it is connected to a voltage below.v, it will latch off after a current fault (which requires that be cycled low in order to start normal operation again). (Pin ): Device Ground. This pin must be tied to a ground plane for best performance. TIMER (Pin 9): Timing Input. An external timing capacitor from TIMER to programs the maximum time the part is allowed to remain in current limit. When the part goes into current limit, a µa pull-up current source starts to charge the timing capacitor. When the voltage on TIMER reaches.6v (typ), is pulled low; the TIMER pullup current will be turned off and the capacitor is discharged by a 3µA pull-down current. When TIMER falls below.6v (typ), turns on again if RETRY is high (if RETRY is low, must be pulsed low to reset the internal fault latch before will turn on). If RETRY is grounded and is not cycled low, remains latched off and TIMER will be discharged to near ground. must be cycled low after TIMER has discharged below.6v (typ) to reset the part. If RETRY is floating or connected to a voltage above its.v threshold, the LT6-3 automatically restarts after a current fault. Under an output short-circuit condition, the LT6-3 cycles on and off with a 3% on-time duty cycle. (Pin ): Power Good Comparator Input. monitors the output voltage through an external resistive divider. When the voltage on is lower than the high-to-low threshold of 3.99V, PWRGD is pulled low and released when is pulled above the.v low-to-high threshold. The voltage present on affects foldback current limit (see Figure and related discussion). (Pin ): Output Voltage Sense Input. This pin should be connected to the source of the external MOSFET. It is used to sense when the MOSFET is shut off (during any fault mode) and to reduce the pull-down current on. This protects the LT6-3 from excessive power dissipation when large output capacitors are used. 6

7 PI FU CTIO S U U U (Pin 3): High Side Gate Drive for the External N-Channel MOSFET. An internal charge pump guarantees at least V of gate drive for supply voltages above V and.v of gate drive for supply voltages between.v and V. The rising slope of the voltage on is set by an external capacitor connected from to and an internal 3µA pull-up current source from the charge pump output. If the current limit is reached, the voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. If the TIMER voltage ever exceeds.6v, is pulled low. is also pulled to whenever is pulled low; the supply voltage drops below the externally programmed undervoltage threshold, above the overvoltage threshold or below the internal LO threshold (9.V). is clamped internally to a maximum voltage of.6v (typ) above under normal operating conditions. Driving this pin beyond the clamp voltage may damage the part. is also clamped to V (typ) below. When the gate is commanded off due to a fault condition, it is discharged quickly by a 6mA (typ) capable switch until is V (typ) below. When is below by V, the 6mA is reduced to 3µA to protect the LT6-3 against damage if has large capacitance. A Zener diode is needed between the gate and source of the external MOSFET to protect its gate oxide under instantaneous short-circuit conditions. See Applications Information. SENSE (Pin ): Current Limit Sense Input. A sense resistor is placed in the supply path between and SENSE. The current limit circuit regulates the voltage across the sense resistor ( SENSE) to mv while in current limit when is V or higher. If drops below V, the regulated voltage across the sense resistor decreases linearly and stops at mv when is V. The output also uses SENSE to detect when the output current is less than (3mV)/R. To defeat current limit, connect SENSE to. (Pin 6): Input Supply Voltage. The positive supply input ranges from.v to V for normal operation. I CC is typically.ma. An internal circuit disables the LT6-3 for inputs less than 9.V (typ).

8 BLOCK DIAGRA W SENSE 6 3mV CIRCUIT V P GEN V P V REF GEN 3.99V V FOLDBACK mv TO mv CURRENT LIMIT 3.99V CHARGE PUMP AND DRIVER 3 PWRGD k RETRY 9.V.6V INTERNAL V LOGIC TIMER LOW V P V µa.6v TIMER HIGH 9 TIMER 3µA 6 BD

9 TEST CIRCUIT PWRGD V SENSE 3V V pf TIMER RETRY 3V 6 F Figure TI I G DIAGRA S U W W V 3.6V t PLH t PHL V Figure. to Timing V 6 F.V 3.99V t PLH t PHL PWRGD V Figure 3. to PWRGD Timing V 6 F3 SENSE mv t PHLSENSE 6 F Figure. SENSE to Timing 9

10 APPLICATIO S I FOR Hot Circuit Insertion ATIO U W U U When circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. The transient currents can permanently damage the connector pins and glitch the system supply, causing other boards in the system to reset. The LT6-3 is designed to turn on a board s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage and overvoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. Power-Up Sequence An external N-channel MOSFET pass transistor (Q) is placed in the power path to control the power up of the supply voltage (Figure ). Resistor R provides current detection and capacitor C controls the slew rate. Resistor R compensates the current control loop while R6 prevents high frequency oscillations in Q. When the power pins first make contact, transistor Q is held off. If the voltage on is between the externally programmed undervoltage and overvoltage thresholds, is above 9.V and the voltage on TIMER is less than.6v (typ), transistor Q will be turned on (Figure 6). The voltage on rises with a slope equal to 3µA/C and the supply inrush current is set at: I INRUSH = C L 3µA/C () where C L is the total load capacitance. I OUT ma/div PWRGD V/DIV V/DIV V/DIV C L = µf ms/div Figure 6. Start-Up Waveforms 6 F6 V IN V (SHORT PIN) C3.µF R 6.9k R R3 D SMATA R.Ω 6 SENSE LT6-3 RETRY 3 Q IRF3 R6 Ω R Ω C nf D CMPZBS V R 36.k R9 R k C L V.6A 9 C 33nF TIMER PWRGD = 36V = 3V PWRGD = V 6 F PWRGD Figure..6A, V Latchoff Application

11 APPLICATIO S I FOR ATIO U W U U To reduce inrush current, increase C or decrease load capacitance. If the voltage across the current sense resistor R reaches V SENSETRIP, the inrush current will be limited by the internal current limit circuitry. The voltage on is adjusted to maintain a constant voltage across the sense resistor and TIMER begins to charge. When the voltage goes above the low-to-high V threshold, PWRGD goes high. Undervoltage and Overvoltage Detection The LT6-3 uses and to monitor the voltage to determine when it is safe to turn on the load and allow the user the greatest flexibility for setting the operational thresholds. and are internally connected to an analog window comparator. Any time that goes below 3.6V or goes above V, will be pulled low until the / voltages return to the normal operation voltage window (V and 3.6V, respectively). The threshold should never be set below the internal LO threshold (9.V typically) because the benefit of the s hysteresis will be lost, making the LT6-3 more susceptible to noise ( must be at least 9.V when is at its 3.6V threshold). is filtered with C3 to prevent noise spikes and capacitively coupled glitches from shutting down the LT6-3 output erroneously. To calculate and thresholds, use the following equations: VTHLH R= ( R R3) a V R R R3 = b VTHLH k R R R3 k 3 R VTHHL = 36. V ; R R3 R R VTHHL = 36. V R3 ( ) ( ) Ω Ω ( ) ( ) where V THULH and V THLH are the desired and threshold voltages when is rising (L H). Figure shows how the LT6-3 is commanded to shut off with a logic signal. This is accomplished by pulling the gate of the open-drain MOSFET, Q, (tied to ) high. OFF SIGNAL FROM MPU V Q VN C3.µF (SHORT PIN) R 6.9k R R3 D SMATA R.Ω 6 SENSE LT6-3 RETRY 3 Q IRF R6 Ω R Ω C nf D CMPZBS V R 36.k R9 R k V A C L 9 C 33nF TIMER PWRGD = 36V = 3V PWRGD = V 6 F Figure. How to Use a Logic Signal to Control the LT6-3 Turn On/Off

12 APPLICATIO S I FOR Short-Circuit Protection ATIO U W U U The LT6-3 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. The current limit is set by placing a sense resistor (R) between and SENSE. The current limit threshold is calculated as: I LIMIT = mv/r () To limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed internally on. If the LT6-3 goes into current limit when the voltage on is V, the current limit circuit drives to force a constant mv drop across the sense resistor. As the output at increases, the voltage across the sense resistor increases until reaches V, at which point the voltage across the sense resistor is held constant at mv (see Figure ). For a.ω sense resistor, the typical current limit is set at ma and folds back to 6mA when the output is shorted to ground. Thus, MOSFET peak power dissipation under short-circuit conditions is reduced from 6W to W. See the Layout Considerations section for important information about board layout to minimize current limit threshold error. The LT6-3 also features a variable overcurrent response time. The time required for the part to regulate the voltage is a function of the voltage across the sense resistor connected between and SENSE. This helps to eliminate sensitivity to current spikes and transients that might otherwise unnecessarily trigger a current limit response and increase MOSFET dissipation. Figure 9 shows the response time as a function of the overdrive at SENSE. V SENSE mv mv RESPONSE TIME (µs) 6 V V 6 F Figure. Current Limit Sense Voltage vs Feedback Pin Voltage 6 F9 V SENSE (mv) Figure 9. Response Time to Overcurrent

13 APPLICATIO S I FOR TIMER ATIO U W U U TIMER provides a method for programming the maximum time the part is allowed to operate in current limit. When the current limit circuitry is not active, TIMER is pulled to by a 3µA current source. When the current limit circuitry becomes active, a µa pull-up current source is connected to TIMER and the voltage will rise with a slope equal to µa/c TIMER as long as the circuitry stays active. Once the desired maximum current limit time is known, the capacitor value is: [ ] = [ ] CnF tms; C= µ A t (6).6V Whenever TIMER reaches.6v (typ), the internal fault latch is set causing to be pulled low and TIMER to be discharged to by the 3µA current source. The part is not allowed to turn on again until the voltage on TIMER falls below.6v (typ). Whenever is commanded off by any fault condition, it is discharged with a high current, turning off the external MOSFET. The waveform in Figure shows how the output latches off following a current fault. The drop across the sense resistor is held at mv as the timer ramps up. Once TIMER reaches its shutdown threshold (.6V typically), the circuit latches off. Automatic Restart If RETRY is floating, then the device automatically restarts after a current overload fault. When the voltage at TIMER ramps back down to.6v (typ), the LT6-3 turns on again. If the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. The duty cycle under short-circuit conditions is 3% which prevents Q from overheating. Figure shows representative waveforms during a short circuit. Latch Off Operation If RETRY is grounded, the LT6-3 will latch off after a current fault. After the part latches off, it may be commanded to start back up. This is accomplished by cycling to ground and then back high (this command can only be accepted after TIMER discharges below the.6v typ threshold, which prevents overheating transistor Q). I OUT ma/div I OUT ma/div TIMER V/DIV TIMER V/DIV V/DIV V/DIV V/DIV V/DIV ms/div 6 F ms/div 6 F Figure. Latch Off Waveforms Figure. RETRY Waveforms 3

14 APPLICATIO S I FOR ATIO U W U U Therefore, using RETRY only, the LT6-3 will either latch off after an overcurrent fault condition or it will go into a hiccup mode. Power Good Detection The LT6-3 includes a comparator for monitoring the output voltage. The output voltage is sensed through the pin via an external resistor string. The comparator s output (PWRGD) is an open collector capable of operating from a pull-up as high as V. PWRGD can be used to directly enable/disable a power module with an active high enable input. Figure shows how to use PWRGD to control an active low enable input power module. Signal inversion is accomplished by transistor Q and R. The thresholds for the pin are.v (low to high) and 3.99V (high to low). To calculate the PWRGD thresholds, use the following equations: R= V THPWRGD R9, high to low () 399. V kω R R9 kω (a) V =.V R THPWRGD, low to high R9 (b) Pin/Open FET Detection is an output which signals abnormally low load currents. When the voltage across the sense resistor is less than 3mV, the open collector pull-down device is shut off allowing to be externally pulled high. is always active when is above 9.V. If is below 9.V (the internal LO threshold), is pulled low. Open-circuit MOSFETs are detected with the LT6-3 by monitoring the voltage across R with while monitoring the output voltage with PWRGD. An open FET condition is signalled when is high and PWRGD is low (after the part has completed its start-up cycle). V (SHORT PIN) C3.µF R 3.k R R3 D SMATA C 33nF R mω 6 SENSE LT6-3 RETRY 9 TIMER PWRGD 3 Q IRFZ3VS R6 Ω R Ω C nf R9 = V = V PWRGD = V D CMPZBS V R k R k R k Q ZN39 6 F C L PWRGD V ma V LOGIC Figure. Active Low Enable PWRGD Application

15 APPLICATIO S I FOR This open FET condition can be falsely signalled during start-up if the load is not activated until after PWRGD goes high. To avoid this false indication, and PWRGD should not be polled for a period of time, t STARTUP, given by: t STARTUP 3 VCC C = 3µ A (9) This can be accomplished either by a microcontroller (if available) or by placing an RC filter as shown in Figure 3. Once the voltage exceeds the monitoring logic threshold, V THRESH, and PWRGD is low, an open FET condition is signalled. In order to prevent a false indication, the RC product should be set with the following equation: RC > 3 VCC C V 3µ A ln V V LOGIC LOGIC THRESH ATIO U W U U () Another condition that can cause a false indication is if the LT6-3 goes into current limit during start-up. This will cause t STARTUP to be longer than calculated. Also, if the LT6-3 stays in current limit long enough for TIMER to fully charge up to its threshold, the LT6-3 will either latch off (RETRY = ) or go into the current limit hiccup mode (RETRY = floating). In either case, an open FET condition will be falsely signalled. If the LT6-3 does go into current limit during start-up, C can be increased (see Power-Up Sequence). LT6-3 INTERNAL COLLECTOR PULL-DOWN V LOGIC R C TO MONITORING LOGIC 6 F3 Supply Transient Protection The LT6-3 is % tested and guaranteed to be safe from damage with supply voltages up to V. However, voltage transients above V may cause permanent damage. During a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed V. To minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a bypass capacitor should be placed between and. A surge suppressor (TransZorb ) at the input can also prevent damage from voltage transients. Pin A curve of gate drive vs is shown in Figure. is clamped to a maximum voltage of.v above. This clamp is designed to withstand the internal charge pump current. An external Zener diode must be used as shown in all applications. At a minimum input supply voltage of.v, the minimum gate drive voltage is.v. When the input supply voltage is higher than V, the gate drive voltage is at least V and a standard threshold MOSFET can be used. In applications from V to V range, a logic level MOSFET must be used. TransZorb is a registered trademark of General Instruments, GSI. V (V) (V) 6 F Figure 3. Delay Circuit for FET Detection Figure. V vs

16 APPLICATIO S I FOR ATIO U W U U In some applications it may be possible for to ring below ground (due to the parasitic trace inductance). Higher current applications, especially where the output load is physically far away from the LT6-3 will be more susceptible to these transients. This is normal and the LT6-3 has been designed to allow for some ringing below ground. However, if the application is such that can ring more than 3V below ground, damage may occur to the LT6-3 and an external diode, D, from ground (anode) to (cathode) will have to be added to the circuit as shown in Figure (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected voltage). A capacitor placed from ground to directly at the LT6-3 pins can help reduce the amount of ringing on but it may not be enough for some applications. During a fault condition, the LT6-3 pulls down on with a switch capable of sinking about 6mA. Once drops below the output voltage by a diode forward voltage, the external Zener will forward bias and will also be discharged to. In addition to the capacitance, the output capacitance will be discharged through the LT6-3. In applications utilizing very large external N-channel MOSFETs, the possibility exists for the MOSFET to turn on when initially inserted into a live backplane (before the LT6-3 becomes active and pulls down on ). This is due to the MOSFET intrinsic drain to gate capacitance forcing current into R and C when the drain voltage steps up from ground to with an extremely fast rise time. To alleviate this situation, a diode, D3, should be put across R with the cathode connected to C as shown in Figure 6. Whenever the LT6-3 turns the MOSFET off, pulls the MOSFET gate to ground with an open collector capable of sinking 6mA. If the output is held up by a large reservoir capacitor, the stored energy is dissipated in the pull-down transistor via a sneak path through the (now forward biased) Zener, D. The LT6-3 has a proprietary feature that reduces on-chip power dissipation by sensing when the MOSFET is off and reducing the pulldown current significantly. See V Turn-Off for more information about using this feature. V Turn-Off The LT6-3 has a proprietary feature that reduces power dissipation by sensing when the MOSFET is off and reducing the pull-down current significantly. As the pin is discharged during any fault, the LT6-3 monitors the pin and pin. When the pin is V below, the pull-down current is reduced from 6mA to about 3µA. V (SHORT PIN) C3.µF R 6.9k R D SMATA R.Ω 6 SENSE LT6-3 3 Q IRF R6 Ω R Ω C nf D CMPZBS V R 36.k C L V A D3 MRA3T3 R3 RETRY R9 R k 9 C 33nF TIMER PWRGD = 36V = 3V PWRGD = V 6 F 6 Figure. Negative Output Voltage Protection Diode Application

17 APPLICATIO S I FOR ATIO U W U U In order to use this feature as designed, a bidirectional Zener diode is needed for D. When the LT6-3 commands the MOSFET off (and a bidirectional Zener is used), the output discharges very slowly (t OFF = (C LOAD )/ 3µA). Several variations can be implemented to discharge the output faster. The recommeded method is shown in Figure and uses an external PNP transistor, diode and resistor to discharge the output quickly. The equation to set the nominal discharge current is: IDISCHG = ( 3 µ A) () RPROG where R PROG must be less than k. The maximum current equation is: I MAX = ( 3 µ A) () R PROG V (SHORT PIN) R 6.9k D SMATA R.33Ω 6 SENSE 3 Q IRF3 R6 Ω D CMPZBS V R 36.k C L V.A C3.µF R LT6-3 R Ω D3 NW R3 9 C 33nF RETRY TIMER PWRGD C nf = 36V = 3V PWRGD = V R9 6 F6 R k Figure 6. High dv/dt MOSFET Turn-On Protection Circuit V (SHORT PIN) C3.µF R 6.9k R R3 D SMATA R.Ω 6 SENSE LT6-3 RETRY 3 Q IRF R6 k R Ω C nf D CMPZBS V R D3 B k N R PROG Q N9 R 36.k R9 R k V A C L 9 C 33nF TIMER PWRGD = 36V = 3V PWRGD = V 6 F Figure. Enhanced Output Pull-Down Circuit

18 APPLICATIO S I FOR Layout Considerations ATIO U W U U To achieve accurate current sensing, a Kelvin connection to the current sense resistor (R in typical application circuit) is recommended. Note that oz copper exhibits a sheet resistance of about 3µΩ/. Small resistances can cause large errors in high current applications. Noise immunity will be improved significantly by locating resistor dividers close to the pins with short and traces. The minimum trace width for oz copper foil is." per amp to make sure the trace stays at a reasonable temperature..3" per amp or wider is recommended. Figure shows a layout that meets these requirements. Q D V IN R6 R D R R R R3 LT6-3 R9 R C 63 F Figure. Recommended Component Placement

19 PACKAGE DESCRIPTIO U GN Package 6-Lead Plastic SSOP (Narrow. Inch) (Reference LTC DWG # --6). ±..9.96* (..9) (.9) REF. MIN (. 6.9)..** (3. 3.9).6 ±.. BSC RECOMMENDED SOLDER PAD LAYOUT (..9). ±. (.3 ±.) TYP.3.6 (.3.)..9 (..9).6. (.6.) NOTE:. CONTROLLING DIMENSION: INCHES INCHES. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (.3.3) TYP. (.63) BSC GN6 (SSOP) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 9

20 APPLICATIO S I FOR ATIO U W U U Dual V Supply Sequencing Application C3.µF R.Ω Q IRF D3 CMPZBS V R SENSE C 6.9k R6 R nf Ω Ω LT6-3 R R3 PWRGD R 36.k R9 R k V A C L PWRGD V IN V/DIV 33nF TIMER RETRY = 36V = 3V PWRGD = V V/DIV V IN V (SHORT PIN) C3.µF R 6.9k R R3 D SMATA C 33nF R.Ω SENSE LT6-3 PWRGD TIMER RETRY Q IRF R6 Ω C R nf Ω D CMPZBS V = 36V = 3V PWRGD = V R 36.k R9 R k 6 TA3 V A C L PWRGD PWRGD V/DIV V/DIV C L = µf C L = µf ms/div 6 TA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT6-/LT6- Positive V Hot Swap Controller in SO- 9V to V Operation, Active Current Limit, Autoretry/Latchoff LTC Single Hot Swap Controller with Multifunction Current Control.V to 6.V, Active Inrush Limiting, Dual Level Cicuit Breaker LTC V Hot Swap Controller in SOT-3 Floating Supply from V, Active Current Limiting, Fast Circuit Breaker LTC-/LTC- V Hot Swap Controller in MSOP Floating Supply from V, Active Current Limiting, Power Good Output LTC3 V Hot Swap Controller and Supply Sequencer Floating Supply from V, Active Current Limiting, Enables Three DC/DC Converters LT Positive High Voltage Hot Swap Controller.V to 36V Operation, Open-Circuit Detection LT6-/LT6- Positive High Voltage Hot Swap Controller.V to V Operation, Active Current Limit, Autoretry/Latchoff Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA 93- () 3-9 FAX: () 3- LT/LWI/LT REV A PRINTED IN USA LINEAR TECHNOLOGY CORPORATION

21 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: LT6-3IGN#PBF LT6-3CGN#TR LT6-3IGN#TR LT6-3IGN#TRPBF LT6-3IGN LT6-3CGN LT6-3CGN#PBF LT6-3CGN#TRPBF