Linear LT4321 Diode Bridge Controller Datasheet

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1 Linear Diode Bridge Controller Datasheet The LT 43 is a dual ideal diode bridge controller that enables a Power over Ethernet (PoE) powered device (PD) to receive power in either voltage polarity from RJ-45 data pairs, spare pairs, or both. The and eight N-channel MOSFETs replace the eight diodes in a passive PoE rectifier bridge. The eases thermal design and increases delivered power. ManualLib.com collects and classifies the global product instrunction manuals to help users access anytime and anywhere, helping users make better use of products.

2 PoE Ideal Diode Bridge Controller Features n Reduces Heat, Eliminates Thermal Design Problems n Maximizes Power Efficiency n Less than 8µA Quiescent Operating Current n Fully Compatible with IEEE 8.3 Detection and Classification n IEEE 8.3 Compliant When Paired with a Powered Device (PD) Controller n Works with -Pair and 4-Pair PoE Applications n Compatible with PoE, PoE, and LTPoE n V Absolute Maximum Voltage n H-Grade Version Operates Up to 5 C n 6-Lead 4mm 4mm QFN Package Applications n PoE/PoE/ LTPoE Powered Devices n DC Polarity Correction and Ideal Diode-ORing of Telecom Supplies Description The LT 43 is a dual ideal diode bridge controller that enables a Power over Ethernet (PoE) powered device (PD) to receive power in either voltage polarity from RJ-45 data pairs, spare pairs, or both. The and eight N-channel MOSFETs replace the eight diodes in a passive PoE rectifier bridge. The eases thermal design and increases delivered power. An internal charge pump allows an all-nmos bridge eliminating larger and more costly PMOS switches. The works with -pair and 4-pair applications. High impedance input sense pins prevent reverse current on unused pairs. If the power source fails or is shorted, a fast turn-off minimizes reverse current transients. Unlike discrete ideal bridge solutions, the will operate through transients without enabling the MOSFETs on unpowered pairs. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath and LTPoE are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Powered Device for PoE (to 3W), PoE (to 5.5W), or Linear LTPoE (to 9W) Systems.µF SMAJ6A µf DATA PAIRS 3 TG BG BG36 TG36 VPORT HSGATE HSSRC 6 4 IN IN36 IN45 IN78 PWRGD LT475 V IN ISOLATED POWER SUPPLY V OUT SPARE PAIRS 5 7 BG45 TG45 TG78 BG78 RUN 43 TA 8 For more information

3 Absolute Maximum Ratings (Notes, ) V to V IN, IN36, IN45, IN78... V to V BG, BG36, BG45, BG78 Voltages....3V to V TG, TG36, TG45, TG78 Voltages....3V to V TG-IN Voltage....3V to V TG36-IN36 Voltage....3V to V TG45-IN45 Voltage....3V to V TG78-IN78 Voltage....3V to V,,....3V to V Operating Ambient Temperature Range I... 4 C to 85 C H... 4 C to 5 C Storage Temperature Range C to 5 C Pin Configuration TG36 IN36 IN45 TG TOP VIEW TG IN BG BG TG78 IN78 BG78 BG45 UF PACKAGE 6-LEAD (4mm 4mm) PLASTIC QFN T JMAX = 5 C, θ JC = 4.5 C/W EXPOSED PAD (PIN 7) IS, MUST BE SOLDERED TO PCB 9 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE IUF#PBF IUF#TRPBF 43 6-Lead 4mm 4mm Plastic QFN 4 C to 85 C HUF#PBF HUF#TRPBF 43 6-Lead 4mm 4mm Plastic QFN 4 C to 5 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: For more information

4 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 5 C, = V to 8V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Supply Range IN-IN36, IN45-IN78, l 8 V V UVLO Undervoltage Lockout - l V I S (DET) Total Supply Current in Detect Region < V l.8 5 µa I S (OFF) Total Supply Current in Shutdown > V, < V IL and > V IH l 3 6 µa I S (ON) Total Operating Supply Current > V IH or < V IL, > V l.5.8 ma Top Gate Drive INn = V SD(MAX) 5mV, µa Out of l V TGn (Note 3) V BG Bottom Gate Drive µa Out of BGn (Note 3) l.5 3 V Top Gate Pull-Up Current TGn = INn (Note 3) l 5 5 µa Top Gate Pull-Down Current INn =.5V; TGn INn = 5V l.5 ma Bottom Gate Pull-Up Current BGn < V BG (Note 3) l µa Bottom Gate Pull-Down Current BGn = 5V l 3 ma Pull-Up Resistance (Active Low) = 55V l kω Pull-Down Resistance (Active High) = 55V l kω V IH Digital Input High, l.6 V V IL Digital Input Low, l.5 V V OC Open Circuit Voltage = 55V l.5 3 V V SD Topside Forward Regulation Voltage INn - l 8 mv Bottom Comparator Turn-On Threshold INn - l 3 5 mv Bottom Comparator Turn-Off Threshold INn - l 5 3 mv Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : Referenced with respect to unless otherwise specified. Note 3: All conditions for external MOSFET turn on must be met. See Table and Table. For more information 3

5 Typical Performance Characteristics Total Supply Current in Shutdown IN = IN45 = V IN IN36 = IN78 = V Total Supply Current in Ideal Bridge Mode, -Pair IN = V IN IN36 = FLOAT IN45, IN78 = = Total Supply Current in Ideal Bridge Mode, 4-Pair IN = IN45 = V IN IN36 = IN78 = = = CURRT (µa) C 5 C C 5 C V IN (V) CURRT (µa) C 5 C C 5 C V IN (V) CURRT (µa) C 5 C C 5 C V IN (V) 43 G 43 G 43 G3 CURRT (µa) Input Pin Current Open Circuit Voltage BGn Pull-Down Strength = 8V 4 C 5 C C 5 C INn (V) V OC (V) C 5 C C 5 C (V) I BGn (ma) V BGn (V) 8 43 G4 43 G5 43 G6 I BGn (ma) BGn Pull-Up Strength TG Pull-Down Strength TG Pull-Up Strength 4 6 V BGn (V) 8 I TG (ma) = V = 8V IN45 = IN78 = FLOAT = IN = 5mV IN36 = 5mV V TGATE (V) I TG (µa) IN45 = IN78 = FLOAT = 4 6 V TGATE (V) IN IN36 = V IN IN36 = 3V IN IN36 = 8V 8 43 G7 43 G8 43 G9 4 For more information

6 Pin Functions IN: Data Pair Input. In a PoE system, IN connects to the center tap of the transformer connected to pins and on an RJ45 connector. IN36: Data Pair Input. In a PoE system, IN36 connects to the center tap of the transformer connected to pins 3 and 6 on an RJ45 connector. IN45: Spare Pair Input. In a PoE system, IN45 connects to the center tap of the transformer connected to pins 4 and 5 on an RJ45 connector. IN78: Spare Pair Input. In a PoE system, IN78 connects to the center tap of the transformer connected to pins 7 and 8 on an RJ45 connector. TG: Top-Side Gate Driver Output. TG pin pulls high with respect to IN when IN is greater than and IN36 is less than. TG36: Top-Side Gate Driver Output. TG36 pin pulls high with respect to IN36 when IN36 is greater than and IN is less than. TG45: Top-Side Gate Driver Output. TG45 pin pulls high with respect to IN45 when IN45 is greater than and IN78 is less than. TG78: Top-Side Gate Driver Output. TG78 pin pulls high with respect to IN78 when IN78 is greater than and IN45 is less than. BG: Bottom-Side Gate Driver Output. BG pin pulls high with respect to when IN36 is greater than and IN is less than. BG36: Bottom-Side Gate Driver Output. BG36 pin pulls high with respect to when IN is greater than and IN36 is less than. BG45: Bottom-Side Gate Driver Output. BG45 pin pulls high with respect to when IN78 is greater than and IN45 is less than. BG78: Bottom-Side Gate Driver Output. BG78 pin pulls high with respect to when IN45 is greater than and IN78 is less than. : Enable, Active Low. Pull down to to enable ideal diode bridge mode. is internally pulled up to V OC. Tie to if the application circuit uses the pin to enable ideal bridge mode. : Enable, Active High. Pull up to enable ideal diode bridge mode. is internally pulled down to. Tie to if the application circuit uses the pin to enable ideal bridge mode. : Positive Output Voltage. is the rectified voltage from which the draws power. : Negative Output Voltage. is the negative rectified voltage. EXPOSED PAD: The exposed pad must be electrically connected to the pin. For more information 5

7 Applications Information OVERVIEW The is a dual ideal diode bridge controller designed to rectify two independent DC channels into a single output. The senses the greater of the two input channels, IN-IN36 or IN45-IN78, and connects them to the output with the correct polarity. Smooth crossover between channels is guaranteed by the enforced dropout voltage, V SD. A very common application is an IEEE 8.3 powered device which is required to accept voltage in either polarity at its RJ-45 input. Polarity correction devices allow the PD to work equally well with standard or cross-over cables and endspan or midspan PSEs. They also prevent the PD from back feeding current into the Ethernet cable. PD polarity correction is commonly done with a traditional diode bridge, but this results in an efficiency loss due to the forward drop generated across two conducting diodes. This voltage drop reduces the available supply voltage and dissipates significant power. The uses actively driven MOSFETs to nearly eliminate the forward voltage drop. By maximizing available voltage and reducing power dissipation (Figure ), the simplifies PD design and reduces power supply cost. It can also eliminate thermal design problems, costly heat sinks, and reduce PC board area. Some designs use ideal diode bridge circuits implemented with discrete components. These bridges often suffer from a trade-off between quiescent current and tolerance to transients and leakage. With quiescent current properly tuned for PoE, stray PCB leakage between bridge components can be enough to cause accidental turn-on, latchup, and destruction of the circuit. The offers significant improvements over discrete solutions. The integrated bridge controller allows for sophisticated sensing and control of the PowerPath MOSFETs, ensuring that MOSFETs that are supposed to be off, stay off. An ideal bridge controlled by the is tolerant to hot-plugs, input short-circuits, common mode shift, and PCB leakage in the application circuit. POWER DISSIPATION (W) IN = 55V IN36 = V IN45 = FLOAT IN78 = FLOAT Figure. Power Dissipation vs Load Current OPERATING MODES (5mΩ FETs) DIODES (SB) POWER SAVED CURRT (ma) 43 F Ideal Diode Bridge Mode In ideal bridge mode the saves power by activating MOSFETs in place of power path diodes. The enters ideal bridge mode when is greater than V UVLO and either or is asserted. When the is enabled, it senses the inputs with respect to the output to decide which external MOSFETs to turn on. Inputs are grouped into pairs, IN/IN36 and IN45/IN78. Within each pair, one input voltage must be greater than and one must be less than before the external MOSFETs related to that pair are enabled. For example, if IN36 is greater than and IN is less than, TG36 and BG will turn on. Table and Table outline the conditions that activate the ideal diode bridge. Shutdown Mode Shutdown mode is intended to keep the quiescent current from interfering with detection and classification in a PoE system (Figure ). The is always in shutdown mode when < V UVLO. It can be held in shutdown mode over the full operating voltage range by deasserting both the and pins. 6 For more information

8 Applications Information Table. Conditions for Ideal Bridge Mode on IN/IN36 PoE MODE IN IN36 IN45 IN78 TG TG36 BG BG36 Detect/Class < V UVLO X X X X X OFF Class/Inrush O > < ON OFF OFF ON Power ON > V UVLO < > OFF ON ON OFF X X IN IN36 < > OFF < Table. Conditions for Ideal Bridge Mode on IN45/IN78 PoE MODE IN IN36 IN45 IN78 TG45 TG78 BG45 BG78 Detect/Class < V UVLO X Class/Inrush O Power ON > V UVLO IN45 IN78 < X X X X OFF > < ON OFF OFF ON X X < > OFF ON ON OFF > OFF < Shutting down the does not disconnect the load. The external MOSFETs are shorted gate to source and bridge current is carried by the MOSFETs body diodes. The eight body diodes will act like two traditional diode bridges. At light load, the power dissipated in the forward drop of the body diodes will be less than the power dissipated by the quiescent current. In applications with a low power sleep mode, the can optionally be shut down to save power if the load current is less than ma. CURRT (µa) SHUTDOWN MODE B SCHOTTKY BRIDGE V IN (V) EXTERNAL INTERFACE AND COMPONT SELECTION Bypass Capacitance A.μF ceramic capacitor must be placed across the and pins. In PD applications, the IEEE 8.3 standard limits the port capacitance at the PD interface (C PD ) to.μf. The and the PD interface controller both need local bypass capacitance, but they can share the same.μf capacitor. If the and the PD interface controller cannot both be positioned next to a shared bypass capacitor, split the C PD capacitance between the two chips by placing a.47μf ceramic close to the and another.47μf ceramic close to the PD interface controller. A μf or greater capacitance must be connected across and pins when the is enabled. In PoE applications it is sufficient for the C PORT capacitor to be connected by the PD interface controller s hot swap FET. In non PoE applications the C PORT capacitor may be permanently connected between and. 43 F Figure. Leakage Current at 5 C For more information 7

9 Applications Information Transient Voltage Suppressor The specifies an absolute maximum voltage of V and is designed to tolerate brief overvoltage events. However, pins that interface to Ethernet cables or remote telecom supplies can routinely see excessive peak voltages. To protect the, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ6A between and. This TVS must be mounted as close as possible to the. For extremely high cable discharge and surge protection contact Linear Technology Applications. MOSFET Selection Select external MOSFETs that have a drain-source breakdown voltage higher than the maximum input voltage. For PoE systems the drain-source breakdown should be at least V. For all applications the gate threshold must be a minimum of V. The amount of power saved by the depends on the channel resistance, R DS(ON), of the external MOSFETs. To maximize performance and power savings select R DS(ON) such that the forward voltage drop, V F, is between mv and 7mV. Given the average output load current, I AVG : R DS(ON) = V F /I AVG For example, a PoE class 4 PD s maximum average current, I AVG, is 6mA. Choosing a MOSFET forward voltage drop of 4mV reduces power consumption to /5th that of a B Schottky diode bridge. R DS(ON) = 4mV/6mA = 66mΩ Enable Pins When is greater than V UVLO, the enable pins and will control whether the is in shutdown mode or ideal bridge mode (Table and Table ). and may be driven by a 3.3V or 5V logic signal, or with an open drain or collector. The pin is pulled up to the internally generated voltage V OC by an internal 5kΩ resistor. The pin is pulled down to by an internal 5kΩ resistor. When is less than V the enable pins are high impedance to prevent these resistors from corrupting PoE detection. The enable pins tolerate V (absolute maximum) and may be tied directly to the or pins as needed. Figure 3 and Figure 4 show how to interface the enable pins to a PD interface controller. In these configurations, the PoE ideal bridge will be enabled after detection and classification are complete and before the PD is consuming a significant amount of current. 8 For more information

10 Applications Information.µF µf k VPORT HSGATE HSSRC PWRGD LT475 V IN ISOLATED POWER SUPPLY V OUT RUN 43 F3 Figure 3. PD Interface Using the Pin k.µf PWRGD PWRGD LTC465 µf k V IN ISOLATED POWER SUPPLY RUN V OUT V IN V OUT RTN 43 F4 Figure 4. PD Interface Using the Pin For more information 9

11 Typical Applications High Efficiency 5W PD Solution with VDC and 4VAC Auxiliary Input BSZN6NS3 4 TG TG PSMN75-MSE 4 V AUX 9V TO 57VDC OR 4VAC IN IN LT43 µf MMSD448 3 BG BG PSMN75-MSE DATA PAIRS TG IN IN36 IN45 IN78 BG BG36 TG36 SMAJ6A.µF.µF 58k 93k VPORT AUX PWRGD HSGATE LT475B HSSRC RCLASS IEEEUVLO 34.8Ω 3.3k 5nF 68µF k ISOLATED POWER SUPPLY RUN V IN 43 TA V OUT SPARE PAIRS 5 7 BG45 TG45 TG78 BG78 8 WÜRTH 7497 PSMN75-MSE 4 For more information

12 Package Description Please refer to for the most recent package drawings. UF Package 6-Lead Plastic QFN (4mm 4mm) (Reference LTC DWG # Rev Ø).7 ± ±.5.9 ±.5.5 ±.5 (4 SIDES) PACKAGE OUTLINE.3 ±.5.65 BSC RECOMMDED SOLDER PAD PITCH AND DIMSIONS BOTTOM VIEW EXPOSED PAD 4. ±..75 ±.5 R =.5 (4 SIDES) TYP 5 6 PIN TOP MARK (NOTE 6).5 ±. (4-SIDES) PIN NOTCH R =. TYP OR CHAMFER.55 ±.. REF..5 NOTE:. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO- VARIATION (WGGC). DRAWING NOT TO SCALE 3. ALL DIMSIONS ARE IN MILLIMETERS 4. DIMSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PREST, SHALL NOT EXCEED.5mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE (UF6) QFN -4.3 ±.5.65 BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection For more of its circuits information as described herein will not infringe on existing patent rights.

13 Typical Application LTPoE 7W Powered Device PSMN75-MSE 4 PSMN4-MSE DATA PAIRS TG IN IN36 IN45 IN78 BG BG36 TG36 SMAJ6A.µF VPORT PWRGD AUX HSGATE LT475 HSSRC RCLASS RCLASS IEEEUVLO 76.8Ω 64.9Ω 3.3k 47nF µf k ISOLATED POWER SUPPLY RUN V IN V OUT SPARE PAIRS 5 7 BG45 TG45 TG78 BG78 43 TA3 8 WÜRTH 7496 PSMN75-MSE 4 Related Parts PART NUMBER DESCRIPTION COMMTS LTC465 IEEE 8.3at PD Interface Controller Internal V, A Switch, -Event Classification Recognition LTC466/LTC466A/ Quad PoE PSE Controller IEEE 8.3at, LTPoE, IEEE 8.3af Power Levels LTC466C LTC469-/ IEEE 8.3af PD Interface with LTC469- for Flyback, LTC469- for Forward Regulator LTC469- Switching Regulator LTC47/LTC47 -Port PoE/PoE/LTPoE PSE Transformer Isolation, Supports IEEE 8.3af, IEEE 8.3at and LTPoE PDs Controller LTC474/LTC474A/ Single PoE PSE Controller IEEE 8.3at, LTPoE 9W, IEEE 8.3af Power Levels LTC474C LT475A/LT475B/ LT475C LTPoE/PoE/PoE PD Controller External Switch, LTPoE Support LTC478 LTC49/LTC47 IEEE 8.3af PD Interface with Integrated Flyback Switching Regulator 8-Port PoE/PoE/LTPoE PSE Controller Linear Technology Corporation 63 McCarthy Blvd., Milpitas, CA For more information (48) 43-9 FAX: (48) Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 5kHz to 5kHz, V Aux Support Transformer Isolation, Supports IEEE 8.3af, IEEE 8.3at and LTPoE PDs LT43 Ideal Diode Bridge Controller 9V to 7V, DC to 6Hz, N-Channel Ideal Diode Bridge LTC4354 Negative Voltage Diode-OR Controller Controls Two N-Channel MOSFETs,.µs Turn-Off, 8V Operation and Monitor LTC4355 Positive Voltage Diode-OR Controller Controls Two N-Channel MOSFETs,.4µs Turn-Off, 9V to 8V Operation and Monitor LTC4359 Ideal Diode Controller with Reverse Input Protection N-Channel, 4V to 8V, MSOP-8 and DFN-6 Packages LT 93 PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 3

LT3572 Dual Full-Bridge Piezo Driver with 900mA Boost Converter DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

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