PD70210 Front-End PD Interface Controller for AF/AT/UPOE/HDBaseT/4-pair PoE Applications

Transcription

1 Description is an advanced PD Interface Controller (Front-end IC) for Powered Devices in PoE applications. It supports IEEE802.3af, IEEE802at, HDBaseT and general 2/4-pair configurations. The includes an advanced classification block that supports 2, 3, 4 and 6 event classification. Using the SUPP_Sx pins, it also identifies which of the four pairs of the cable are actually receiving power and generates appropriate flags. The IC features an internal bleeder for discharging the input capacitor of the DC/DC converter rapidly, so as to ensure fast re-detection and port power-up in case of sudden removal and re-insertion of the Ethernet cable into the RJ-45. Features Supports IEEE802.3af/at, HDBaseT and other 2-pair/4-pair configurations. PD detection & programmable classification 2,3,4 and 6 event classification Integrated 0.3Ω isolating (series-pass) FET Inrush current limiting Less than 10µA offset current during detection Lead-free DFN-16 package Applications HDBaseT up to 95 Watts IEEE802.3af and 802.3at Indoor and outdoor PoE Figure 1: Typical Applications Diagram () Page 1

2 Pin Configuration Figure 2: Pinout Ordering Information Ambient Temperature -40 C to 85 C Type Part Marking Tape and Reel Package RoHS compliant, Pb-free ILD ILD-TR DFN-16 (5mm 4 mm, 0.5mm pitch) Page 2

3 Pin Description () Pin Number Designator 1 VPP 2 RDET 3 SUPP_S1 4 SUPP_S2 Description Upper rail of the incoming 48V PoE rail --- from the positive terminal of the two OR-ed bridge rectifiers (the corresponding lower PoE rail is VPN_IN) Internally connects to VPN_IN during detection phase, and disengages after that is over. A 25k resistor (or 24.9k), 1% resistor is connected between this pin and VPP High voltage positive input sense pin, to sense the voltage on the diode bridge connected to the data pairs. It goes high (to PoE voltage), independent of the other bridge, if the bridge it is connected to has voltage placed across it by the PSE. It can therefore be used to distinguish between 2-pair and 4-pair operation, in conjunction with the voltage on SUPP_S2 High voltage positive input sense pin, used to sense the voltage on the diode bridge connected to the spare pairs. It goes high (to PoE voltage), independent of the other bridge, if the bridge it is connected to has voltage placed across it by the PSE. It can therefore be used to distinguish between 2-pair and 4-pair operation, in conjunction with the voltage on SUPP_S1 5 RREF Bias current resistor. A 243k, 1% resistor is connected between this and IC ground (VPN_IN) 6 RCLS 7, 8 VPN_IN 9, 10 VPN_OUT Sets the Class of the PD. Connect Rclass (programming resistor) between this pin and IC ground (VPN_IN). Allowed values are 133Ω, 69.8Ω, 45.3Ω and 30.9Ω for Class 1, 2, 3 and 4 respectively. If Rclass is not present, the PD will draw up to 3mA during classification, thus indicating Class 0 (default Type 1) to the PSE Lower rail of the incoming 48V PoE rail --- from the negative terminal of the two OR-ed bridge rectifiers (the corresponding upper PoE rail is VPP) This is in effect, the switched ground for establishing continuity to the PWM section after successful detection, classification, and Power-up. It is connected to the Power ground and PWM controller IC s ground plane of the DC-DC converter section 11 AT_FLAG This flag goes high when a Type 2 PD-PSE mutually identify each other via classification 12 HD_FLAG 13 4P_AT_FLAG 14 4P_HD_FLAG 15 PGOOD 16 VAUX This flag goes high when a 2-pair HDBaseT PD-PSE mutually identify each other via classification This flag goes high when a 4-pair version of a (non-standard) Type 2 PD-PSE mutually identify each other via classification This flag goes high when a 4-pair HDBaseT PD-PSE mutually identify each other via classification Power Good output signal from the Front-End stage. Connect a pullup resistor to an available 5V/3.3V rail. This pin gets actively pulled low when power-on occurs. There is a minimum 80ms delay from the moment VPort exceeds UVLO ( ~36V), to Power Good Auxiliary voltage rail. This can be used to provide a few ma of startup current for the PWM controller (at typically 10.5V). It is gated with the power-good signal internally, so it is released to the PWM controller only when the PoE power is up (power-on phase) 17 EPAD Connected on PCB plane to VPN_IN Page 3

4 Functional Block Diagram +48V VPP 1 45mA 10.5V regulator Vdd 80ms delay timer VAUX 16 Bleeder control 4.8V regulator 1.2V Bandgap RREF RREF 5 5V RDET RDET 2 SUPP_S1 SUPP_S2 3 4 Detection control Temp Enhanced Classification Block PGOOD PGOOD 15 AT_FLAG 11 HD_FLAG 12 4P_AT_FLAG 13 4P_HD_FLAG 14 RCLASS RCLS 6 Iclass Class control Startup/ Inrush control 48VRTN VPN_IN 7 Temp VPN_OUT 9 8 Rsense 10 Figure 3: Block Diagram () Page 4

5 Absolute Maximum Ratings Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability. The voltages are with respect to IC ground (VPN_IN). Min Max Units VPP, VPN_OUT, RDET, PGOOD, AT_FLAG, V HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG SUPP_S1, SUPP_S2 0 V VPP V RREF, RCLS V VAUX V Junction Temperature C Lead Soldering Temperature (40s, reflow) 260 C Storage Temperature C ESD rating HBM ±2 kv MM ±200 V CDM ±500 V Operating Ratings Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. The voltages are with respect to IC ground (VPN_IN). Min Max Units VPP 0 57 V Ambient Temperature* C Detection Range V Mark event range V Class event range V * Corresponding Max Operating Junction Temperature is 125 C. Thermal Properties Thermal Resistance Min Typ Max Units θ JA 31 C/W θ JL TBD C/W θ JC TBD C/W Note: The θ Jx numbers assume no forced airflow. Junction Temperature is calculated using T J = T A + (P D x θ JA ). In particular, θ JA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). Page 5

6 Electrical Characteristics Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device. Typ values stated, are either by design or by production testing at 25 C ambient. The voltages are with respect to IC ground (VPN_IN). Symbol Parameter Conditions Min Typ Max Units Input Voltage I IN IC input current with I CLASS off VPP=55V 1 3 ma Detection phase V DET Detection range V R DET_TH R DET disconnect threshold V R DS_DET_ON On-resistance of internal FET during 50 Ω detection R DS_DET_OFF Off-resistance of internal FET after detection 2 MΩ I OFFSET_DET Input offset current 1.1V VPP 10.1V, T J 85 C 5 μa R DET reconnection V R_DET_ON threshold when VPP goes low V Classification phase V CLS_ON Classification sink turn-on threshold V V CLS_OFF Classification sink turn-off threshold V Hysteresis of V HYS_CLS_ON V CLS_ON threshold 1 V MARK_TH Mark detection threshold (VPP V falling) I MARK Current sink in Mark event region ma Page 6

7 Symbol Parameter Conditions Min Typ Max Units Current limit of ma class current R CLASS = not present (Class 0) 3 I CLASS_CLIM I CLASS Classification current sink R CLASS = 133 Ω (Class 1) R CLASS = 69.8 Ω (Class 2) R CLASS = 45.3 Ω (Class 3) R CLASS = 30.9 Ω (Class 4) Isolation FET R DSON On resistance T J = TBD C 0.3 Ω Inrush current I CLIM_INRUSH limit ma OCP Overcurrent protection 2.2 A Undervoltage Lockout Threshold that UVLO ON marks start of V Inrush phase UVLO OFF Threshold where pass-fet turns off as VPP collapses V DC-DC Input Cap Discharger I CAP_DIS Discharge current 7V VPP 30V ma TBD VPP UVLO OFF, t dis Discharge time C DC_DC 264 μf (by design, not tested) 500 ms timer dis Discharge timer Time for which discharge circuit is activated 430 ms References, Rails and Logic V AUX Auxiliary voltage I AUX = TBD ma V I AUX Max continuous current from V AUX 4 ma I AUX_CLIM Aux current limit ma V REF Bandgap reference (by design, not tested) voltage V Page 7 ma

8 Symbol Parameter Conditions Min Typ Max Units Power good active I low voltage PGOOD =TBD ma 0.8V Power good current capability 5 ma Delay timer between start of inrush and power 80 ms good declared High level for WA_EN pin 2.4 V Low level for WA_EN pin 0.8 V For AT_FLAG, HD_FLAG, Low level flag 4P_AT_FLAG, 4P_HD_FLAG, 0.4 V I FLAG = 4mA V PGOOD_LO I PGOOD t PGOOD V WA_EN_HI V WA_EN_LO t FLAG_LO I FLAG V SUPP_HI V POR Flag Current driving capability SUPP_Sx high voltage threshold Power-on reset threshold For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG 5 ma For SUPP_S1 and SUPP_S V VPP rising (by design, not tested) V V POR_HYS POR Hysteresis 0.65 V Page 8

9 Truth Table for Status of Flags Number of Fingers N (N-Event Classification) AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG RESERVED FOR FUTURE Thermal Protection The is protected from excessive internal temperatures that may occur during various operating procedures. Two temperature sensors are located on the chip, monitoring the temperatures of the following: Isolating Switch (pass-fet) Classification Current Sink Each of the over temperature sensor activates a protection mechanism that will disconnect the Isolation (pass) FET or the classification circuit respectively.. This protects the device from being permanently damaged or even from long-term degradation. Worst-Case Power Estimates The table below includes the minimum guaranteed available power at the PD-side (at the entrance of its RJ- 45). It takes into account expected channel resistance and imbalances in the resistance across the pairs. PSE Type Current per pair Balance between pairs PSE output Power Max load Current Min PSE voltage Channel Resistance PD input Power TYPE 1 (AF) 350mA NA 15.4W 350mA 44V W TYPE 2 (AT) 600mA NA 30W 600mA 50V W MSCC Extended AT 720mA NA 36W 720mA 50V W 4-Pair (600mA) 600mA 87.33% 60W 1123mA 50V W Page 9

10 4-pait (720mA) 720mA 87.33% 72W 1348mA 50V W 2-pair HDBaseT 950mA NA 47.5W 950mA 50V W 4-pair HDBaseT 950mA 87.33% 95W 1779mA 50V W Package Dimensions LD E 16 Pin Plastic DFN 5x6 mm E2 Top View e Pin1 ID D L MILLIMETERS INCHES Dim MIN MAX MIN MAX A A A REF REF D 5.00 BSC BSC E 4.00 BSC BSC D E e 0.50 BSC BSC K 0.20 MIN MIN L b Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006 ) on any side. Lead dimension shall not include solder coverage b D2 Bottom View A A3 A1 Page 10