V OUT. Speed control voltage (V SET. Package Code. K : SOP-8 Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel

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1 Low Dropout 6mA Linear Regulator for DC Fan Control Features Low Dropout Voltage: mv 6mA Low Quiescent Current: 4mA Selectable Adjustable/Full Speed Mode O/I Voltage Ratio in Adjustable Mode :.6 times Stable with Low ESR Ceramic Capacitors Over-Temperature Protection Current Limit Protection with Foldback Current Internal Soft-start SOP-8 Package Lead Free Available (RoHS Compliant) Simplified Application Circuit General Description The APL566 is a low quiescent current, low dropout linear regulator which is designed with a P-channel pass MOSFET to power a DC fan and delivers output current up to 6mA. In adjustable mode, the output voltage follows the.6 times of the voltage on VSET pin to dynamically adjust the DC fan speed; in full speed mode, the internal P-channel MOSFET fully turns on to drive the DC fan with maximum supply voltage for full speed operation. The APL566 with low 4µA quiescent current is ideal for battery-powered system appliances. It is also stable with a low-esr ceramic output capacitor (.µf typical) to reduce total cost and minimize the PCB area required. The APL566 features current limit (with foldback current) and over-temperature protections to protect the device against current over-loads and over temperature. The APL566 is available in a SOP-8 package. C Adjustable mode Full speed mode VIN µf APL566.µF FSM GND VOUT VSET C Speed control voltage (V SET ) Applications Notebook Fan Driver Motherboards PC Peripherals Battery-Powered System Ordering and Marking Information APL566 Lead Free Code Handling Code Temperature Range Package Code Package Code K : SOP-8 Operating Ambient Temperature Range I : -4 to 85 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device APL566 K : APL566 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and % matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-C for MSL classification at lead-free peak reflow temperature. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders.

2 Pin Configuration SOP-8 Top View FSM VIN VOUT 3 VSET 4 8 GND 7 GND 6 GND 5 GND APL566 Absolute Maximum Ratings (Note ) Symbol Parameter Rating Unit VIN to GND -.3 ~ 6.5 V V FSM FSM to GND -.3 ~ +.3 V VOUT to GND -.3 ~ +.3 V T J Maximum Junction Temperature 5 o C P D Power Dissipation Internally Limited T STG Storage Temperature Range -65 ~ 5 T L Lead Temperature (Soldering, sec) 6 o C o C Note : Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Rating Unit θ JA Junction to Ambient Thermal Resistance SOP-8 8 C/W Note : θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol Parameter Range Unit VIN to GND 4.5 ~ 6 V V FSM FSM to GND ~ V VOUT to GND ~ -V DROP V V SET VSET to GND ~ 3.3 V Output Current ~.6 A C IN Input Capacitor.8 ~ 47 µf C OUT Output Capacitor ~ 33 µf T J Junction Temperature -4 ~ 5 C T A Ambient Temperature -4 ~ 85 C

3 Electrical Characteristics Refer to the typical application circuit. = 5V, V FSM =, = ma~6ma, T J = -4 to 5 C, T A = -4 to 85 C, unless otherwise specified. Typical values are at T A = 5 C. Symbol Parameter Test Conditions Min Typ Max Unit SUPPLY CURRENT I Q Quiescent Current UNDER-VOLTAGE-LOCKOUT (UVLO) OUTPUT VOLTAGE V DROP V FSM = V - - µa V FSM = 5V, = A - 4 µa VIN UVLO Threshold rising..5.9 V VIN UVLO Hysteresis V VOUT Voltage / VSET Voltage VOUT Voltage / VSET Voltage T J = 5 C, =5.5V, =ma, V SET =3.3V T J = 4 ~ 5 C, =5.5V, =ma, V SET = ~ 3.3V V/V V/V VSET pin Current V SET =5V -.5 µa Line Regulation = + V to 6V -.3. %/V Load Regulation = ma to 6mA - 6 mv Dropout Voltage PROTECTION and SOFT-START = 6mA, =.5V mv = 6mA, =3.3V - 35 mv = 6mA, =5V - 3 mv I LIM Output Current Limit ma Thermal Shutdown Temperature C Thermal Shutdown Hysteresis C Foldback Current Limit <.6V ma T SS Soft-Start Time µs LOGIC INPUT VOUT Pull Low Resistance V FSM =V, =.5V Ω FSM Logic Input-High Level V FSM Logic Input-Low Level V FSM Pull-Low Resistance V FSM <3V - - MΩ 3

4 Typical Operating Characteristics =5V, V SET =V, =3.V, C IN =µf, C OUT =.µf, unless otherwise specified.6 FSM Voltage Threshold vs. Input Voltage 8 Quiescent Current vs. VSET Voltage FSM Voltage Threshold (V) Quiescent Current, I Q ( A) =ma Input Voltage (V) VSET Voltage (V) 6 5 VSET Voltage vs. Output Voltage =ma In Adjustable Mode 3 5 Dropout vs. Junction Temperature =5V =6mA Output Voltage (V) 4 3 Dropout Voltage (mv) 5 5 =4mA =ma Dropout Voltage (mv) VSET Voltage (V) Dropout vs. Junction Temperature =3.3V =6mA =4mA =ma C) Junction Temperature, T J ( PSRR (db) Junction Temperature, T J ( C) Power Supply Rejection Ratio (PSRR) =5, C IN =µf, C OUT =.µf, V SET =V, =3.V =5mA =4mA -5 Frequency (Hz) 4

5 Typical Operating Characteristics (Cont.) =5V, V SET =V, =3.V, C IN =µf, C OUT =.µf, unless otherwise specified Quiescent Current vs. Input Voltage Quiescent Current (µa) =ma Input Voltage, (V) Operating Waveforms =5V, V SET =V, =3.V, C IN =µf, C OUT =.µf, unless otherwise specified Power On Power Off V SET V SET CH :, V/div CH : V SET, V/div CH3 :, V/div CH4 :, 5mA/div Time : ms/div CH :, V/div CH : V SET, V/div CH3 :, V/div CH4 :, 5mA/div Time : ms/div 5

6 Operating Waveforms (Cont.) =5V, V SET =V, =3.V, C IN =µf, C OUT =.µf, unless otherwise specified Load Transient Line Transient =5V, V SET =V, =3.V C IN =µf, C OUT =.µf =5V~6V~5V, V SET =V, =3.V, C IN =µf, C OUT =.µf CH :, mv/div CH :, mv/div Time : µs/div CH :, V/div CH :, mv/div Time : ms/div Thermal Shutdown Current Limit and Short Circuit Current Limit 3 3 CH :, 5V/div CH :, V/div CH3 :, 5mA/div Time : 5ms/div CH :, 5V/div CH :, V/div CH3 :, A/div Time : ms/div 6

7 Pin Descriptions No. Pin Name FSM VIN 3 VOUT Function Descriptions Adjustable/Full Speed Mode Selection Input Pin. Output voltage follows.6 times of the voltage on VSET pin. If the FSM is at low level, the IC operates in full speed mode with the P-channel MOSFET fully turned on. The FSM pin is pulled low by an internal resistor. Supply Voltage Input Pin. Supply voltage can range from 4.5V to 6V. Bypass with a µf (typical) capacitor to GND Regulator Output. Sources up to 6mA. A small capacitor is needed and connected from this pin to ground to assure stability. 4 VSET Output Voltage-Set Input. The output voltage follows the.6 times of the VSET voltage. 5,6,7,8 GND Ground. These pins are internally connected with the internal leadframe. Connect these pins to a wide ground plane for good heat dissipation. Block Diagram VIN Current Limit and Foldback Current Limit FSM UVLO and Soft-Start VSET VOUT Thermal Shutdown.6R R GND Typical Application Circuit APL566 VIN VSET V SET Adjustable mode C IN µf FSM GND VOUT C OUT.µF V FSM Full speed mode 7

8 Function Descriptions Under-Voltage Lock-Out (UVLO) The APL566 has a built-in under-voltage lock-out circuit to keep the output off until the internal circuitry is operating properly. The UVLO function initiates a soft start process after input voltage exceeds its rising UVLO threshold during power on. Typical UVLO threshold is.5v with.5v hysteresis. Soft-Start The APL566 provides an internal soft-start circuitry to control rise rate of the output voltage and limit the current surge during start-up. Approximate µs delay time after the is over the UVLO threshold, the IC starts a soft-start. The typical soft-start interval is about 3µs. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL566. When the junction temperature exceeds +5 ο C, the thermal shutdown circuitry disables the output, allowing the device to cool down. The output circuitry is enabled again after the junction temperature cools down by 4 ο C, resulting in a pulsed output during continuous thermal overload conditions. The thermal protection is designed to protect the IC in the event of over temperature conditions. For reliable operation, the junction temperature cannot exceed T J =+5 ο C. Adjustable/Full Speed Mode Selection The APL566 features an input pin to select one of the operation modes for DC fan speed control. In adjustable mode, the output voltage follows the.6 times of the voltage on VSET pin to dynamically adjust the DC fan speed; in full speed mode, the internal P-channel MOSFET fully turns on to drive the DC fan with maximum supply voltage ( -V DROP ) for full speed operation. Driving the FSM voltage at high level(v FSM >.6V) sets the IC to operate in adjustable mode; driving the FSM at low level(v FSM <.4V) sets the IC to operate in full speed mode. The FSM is pulled low by an internal resistor. Current Limit The APL566 provides a current limit circuitry, which monitors the output current and controls P-MOS s gate voltage to limit the output current at 7mA (min.). Foldback Current Limit When the output voltage drops below.6v (typical), which is caused by over load or short circuit, the foldback current limit circuitry limits the output current to 5mA. The foldback circuit current limit is used to reduce the power dissipation during short circuit condition. The foldback current limit is disabled for.6ms (typical) after the UVLO threshold is reached, so that the IC has normal 7mA (min.) current limit level during start-up. 8

9 Application Information Input Capacitor The APL566 requires proper input capacitors to supply surge current during stepping load transients to prevent the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN limits the slew rate of the surge current, place the Input capacitors near VIN as close as possible. The input capacitors should be larger than.8µf. Output Capacitor The APL566 needs a proper output capacitor to maintain circuit stability and to improve transient response over temperature and current. In order to insure the circuit stability, the proper output capacitor value should be larger than µf. With X5R and X7R dielectrics,.µf is sufficient at all operating temperatures. PCB Layout Considerations Figure illustrates the layout. Below is a checklist for your layout:. Please place the input capacitors close to the VIN. Ceramic capacitors for load must be placed near the load as close as possible 3. To place APL566 and output capacitors near the load is good for performance. 4. Large current paths, the bold lines in figure, must have wide tracks. APL566 C IN V FSM VIN FSM VSET VOUT GND V SET C OUT Operation Region and Power dissipation The APL566 maximum power dissipation depends on the thermal resistance and temperature difference between the die junction and ambient air. The power dissipation P D across the device is: P D (TJ T = θja A ) where (T J -T A ) is the temperature difference between the junction and ambient air. JA is the thermal resistance between Junction and ambient air. Assuming the T A =5 ο C and maximum T J =5 ο C (typical thermal limit threshold), the maximum power dissipation is calculated as: P D(max) =(5-5)/8 =.56 (W) For normal operation, do not exceed the maximum junction temperature of T J = 5 ο C. The calculated power dissipation should less than: P D =(5-5)/8 =.5 (W) Figure Optimum performance can only be achieved when the device is mounted on a PC board according to the SOP-8 Board Layout diagram. For dissipating heat GND SOP-8 C IN C OUT GND Figure Recommanded Minimum Footprint Unit : Inch 9

10 Package Information SOP-8 D SEE VIEW A E E h X 45 e b c A A A VIEW A L.5 GAUGE PLANE SEATING PLANE S Y M SOP-8 B O L MIN. MAX. MIN. A.75 A..5.4 MAX..69. A.5.49 b c D 4.9 BSC.93 BSC E 6. BSC.36 BSC E 3.9 BSC.54 BSC e.7 BSC.5 BSC h L MILLIMETERS INCHES Note:. Followed JEDEC MS- AA.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension E does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed mil per side.

11 Carrier Tape & Reel Dimensions OD P P P A W F E OD B A T B K B A SECTION A-A SECTION B-B d H A T Application A H T C d D W E F MIN..5 MIN.. MIN SOP-8 P P P D D T A B K MIN Devices Per Unit (mm) Package Type Unit Quantity SOP-8 Tape & Reel 5

12 Reflow Condition (IR/Convection or VPR Reflow) T P Ramp-up tp Critical Zone T L to T P T L t L Temperature Tsmax Tsmin Ramp-down ts Preheat 5 t 5 C to Peak Reliability Test Program Test item Method Description SOLDERABILITY MIL-STD-883D-3 45 C, 5 sec HOLT MIL-STD-883D-5.7 Hrs C PCT JESD--B, A 68 Hrs, %RH, C TST MIL-STD-883D C~5 C, Cycles ESD MIL-STD-883D-35.7 VHBM > KV, VMM > V Latch-Up JESD 78 ms, tr > ma Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (T L to T P ) 3 C/second max. 3 C/second max. Preheat C 5 C - Temperature Min (Tsmin) - Temperature Max (Tsmax) 5 C C - Time (min to max) (ts) 6- seconds 6-8 seconds Time maintained above: - Temperature (T L ) - Time (t L ) Time 83 C 6-5 seconds 7 C 6-5 seconds Peak/Classification Temperature (Tp) See table See table Time within 5 C of actual Peak Temperature (tp) -3 seconds -4 seconds Ramp-down Rate 6 C/second max. 6 C/second max. Time 5 C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface.

13 Classification Reflow Profiles (Cont.) Table. SnPb Eutectic Process Package Peak Reflow Temperatures Package Thickness Volume mm 3 Volume mm 3 <35 35 <.5 mm 4 +/-5 C 5 +/-5 C.5 mm 5 +/-5 C 5 +/-5 C Table. Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume mm 3 Volume mm 3 Volume mm 3 < > <.6 mm 6 + C* 6 + C* 6 + C*.6 mm.5 mm 6 + C* 5 + C* 45 + C*.5 mm 5 + C* 45 + C* 45 + C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature + C. For example 6 C+ C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : Fax : Taipei Branch : F, No., Lane 8, Sec Jhongsing Rd., Sindian City, Taipei County 346, Taiwan Tel : Fax :