Source and Sink, 2A, Fast Transient Response Linear Regulator VIN VREF VOUT APL5339 VOSNS GND

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1 Source and Sink, A, Fast Transient Response Linear Regulator Features Provide Bi-direction Currents - Sourcing or Sinking Current Up to A Built-in Soft-Start Power-On-Reset Monitoring on VCNTL Pins Fast Transient Resoponse Stable with Ceramic Output Capacitors +0mV High System Output Accuracy Over Load and Temperature Ranges Adjustable Output Voltage by External Resistors Current-Limit Protection On-Chip Thermal Shutdown Shutdown for Standby or Suspend Mode Compact TDFN3x3-0 Package Lead Free and Green Devices Available (RoHS Compliant) Applications DDRII/III/IV SDRAM Termination Voltage Motherboard and VGA Card Power Supplies Setop Box Low Power DDRIII/IV General Description The APL5339 linear regulator is designed to provide a regulated voltage with bi-direction output current for DDR- SDRAM termination voltage. The APL5339 integrates two power transistors to source or sink load current up to A. It also features internal soft-start, current-limit, thermal shutdown and enable control functions into a single chip. The internal soft-start controls the rising rate of the output voltage to prevent inrush current during start-up. The current-limit circuit detects the output current and limits the current during short-circuit or current overload conditions. The on-chip thermal shutdown provides thermal protection against any combination of overload that would create excessive junction temperatures. The output voltage of APL5339 is regulated to track the voltage on half voltage of VREF. An internal resistor divider is used to provide a half voltage of VREF for VOUT Voltage. The VOUT output voltage is only requiring 0µF of ceramic output capacitance for stability and fast transient response. Pulling and holding the voltage on voltage of EN below the enable voltage threshold shuts off the output. The APL5339 is available in TDFN3x3-0 package. Simplified Application Circuit V CNTL VCNTL V IN VIN VREF VOUT APL5339 Enable EN EN VOSNS GND ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Rev. A. - Nov., 05

2 Pin Configuration EN VOSNS VOUT 3 VOUT 4 VOUT 5 GND TDFN3X3-0 (Top View) 0 VCNTL 9 VREF 8 VIN 7 VIN 6 VIN = Exposed Pad (connected to ground plane for better heat dissipation) Ordering and Marking Information APL5339 Assembly Material Handling Code Temperature Range Package Code Package Code QB : TDFN3x3-0 Operating Junction Temperature I : -40 to 85 o C Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5339 QB: APL 5339 XXXXX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 00% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-00D for MSL classification at lead-free peak reflow temperature. ANPEC defines Green to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 500ppm by weight). Absolute Maximum Ratings (Note ) Symbol Parameter Rating Unit V CNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V V IN VIN Supply Voltage (VIN to GND) -0.3 ~ 4 V V REF VREF Input Voltage (VREF to GND) -0.3 ~ 7 V V OSNS VOSNS Input Voltage (VOSNS to GND) -0.3 ~ 7 V VOUT Output Voltage (VOUT to GND) -0.3 ~ V IN+0.3 V V EN EN to GND Voltage -0.3 ~ V CNTL+0.3 V T J Junction Temperature 50 T STG Storage Temperature -65 ~ 50 T SDR Maximum Lead Soldering Temperature (0 Seconds) 60 Note: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. o C o C o C Rev. A. - Nov., 05

3 Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Junction-to-Ambient Resistance in Free Air (Note ) TDFN3x o C/W Note : θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. (Note 3) Recommended Operating Conditions Symbol Parameter Range Unit V CNTL VCNTL Supply Voltage (Note 4) 3.0 ~ 5.5 V V IN VIN Supply Voltage.0 ~ 3.6 V V REF VREF Input Voltage (Note 5) 0 ~ VIN V VOUT Output Voltage (VCNTL - VOUT >.3V for I OUT = A, T J=5 C) 0.5xV REF ~ VIN VDROP V I OUT VOUT Output Current (Note 6) - ~ + A C IN C OUT Capacitance of Input Capacitor 0 ~ 00 µf Equivalent Series Resistor (ESR) of Input Capacitor 0 ~ 00 mω Capacitance of Output Multi-layer Ceramic Capacitor (MLCC) 8 ~ 47 µf Total Output Capacitance (Note 7) 0 ~ 80 µf T A Ambient Temperature -40 ~ 85 T J Junction Temperature -40 ~ 5 o C o C Note 3: Refer to the typical application circuit Note 4: The voltage of VCNTL must be higher than the voltage of VOUT pin. Note 5: The voltage of VREF should not be higher than the voltage of VIN when the regulator be enabled. Note 6: The symbol + means the VOUT sources current to load; the symbol - means the VOUT sinks current from load to GND. Note 7: It is necessary to use a multi-layer ceramic capacitor 8µF at least as an output capacitor. Please place the ceramic capacitor near VOUT pin as close as possible. Besides, the other kinds of capacitors (like Electrolytic, PoSCap, tantalum capacitors) can be used as the output capacitors in parallel. Electrical Characteristics Unless otherwise specified, these specifications apply over V CNTL =5V, V IN =.8V,.5V or.35v, V REF =V IN, C IN =0µF, C OUT =0µF (MLCC) and T A = -40 to 85 o C. Typical values are at T A =5 o C. Symbol Parameter Test Conditions APL5339 Min Typ Max Unit SUPPLY CURRENT I CNTL VCNTL Supply Current V EN=V CNTL, I OUT=0A ma I SD VCNTL Supply Current at Shutdown V EN=GND µa I VIN VIN Supply Current at Shutdown V EN=GND - - µa POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL Rising V VCNTL POR Hysteresis V Rising VIN POR Threshold VIN Rising V VIN POR Hysteresis V Rev. A. - Nov., 05 3

4 Electrical Characteristics(Cont.) Unless otherwise specified, these specifications apply over V CNTL =5V, V IN =.8V,.5V or.35v, V REF =V IN, C IN =0µF, C OUT =0µF (MLCC) and T A = -40 to 85 o C. Typical values are at T A =5 o C. Symbol Parameter Test Conditions APL5339 Min Typ Max Unit OUTPUT VOLTAGE VOUT Output Voltage V REF System Accuracy Over Load, Offset and Temperature -0-0 mv VOUT Discharge Current V CNTL=5V, V EN=0V, =0.V - - µa VOSNS Input Current V OSNS=V CNTL na VREF Input Current V REF=5V µa ENABLE and INTERNAL SOFT-START V EN EN Logic Input Threshold V CNTL=3V~5.5V V EN Hysteresis V I EN EN Pull-High Current V EN =GND µa t SS Internal Soft-Start Interval V REF=.8V, =0% to 90%, T J=5 o C ms DROPOUT VOLTAGES V DROP VIN-to-VOUT Dropout Voltage V CNTL=5.0V, I OUT= A, T J=5 o C V =.V T J=-40 o C ~5 o C V PROTECTIONS I LIM Current Limit Level Sourcing Current Sinking Current T J=5 o C A T J=-40 o C~5 o C. - - A T J=5 o C A T J=-40 o C ~ 5 o C A T SD Thermal Shutdown Temperature T J rising Thermal Shutdown Hysteresis o C o C Rev. A. - Nov., 05 4

5 Pin Description NO. PIN NAME EN VOSNS 3, 4, 5 VOUT 6, 7, 8 VIN FUNCTION Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When leave this pin open, an internal pull-up current (3µA typical) pulls the EN voltage and enables the regulator. Output voltage feedback pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. Output pin of the regulator. Connect this pin to load and output capacitors (8µF at least) required for stability and improving transient response. The output voltage is regulated to track the reference voltage and capable of sourcing or sinking current up to A. During shutdown, the output voltage is discharged by an internal pull-low MOSFET. Main supply input pin for voltage conversions. A decoupling capacitor ( 0µF recommended) is usually connected near this pin to filter the voltage noise and improve transient response. The APL5339 sources current to VOUT pin by controlling the upper pass MOSFET, providing a current path from VIN pin. 9 VREF Reference voltage input for VOUT regulator. 0 VCNTL Exposed Pad GND Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V recommended). A decoupling capacitor (µf typical) is usually connected near this pin to filter the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose. Ground pin of the circuitry. Connect the exposed pad to the system ground plan with large copper area for dissipating heat into the ambient air. The APL5339 sinks current from VOUT pin by controlling the lower pass MOSFET, providing a current path to GND pin. Rev. A. - Nov., 05 5

6 Typical Operating Characteristics VCNTL Supply Current, ICNTL (ma) V CNTL = 5V VCNTL Supply Current vs. Junction Temperature VCNTL Shutdown Current, ISD (( A) VCNTL Shutdown Current vs. Junction Temperature V CNTL = 5V Junction Temperature, T J ( o C) Junction Temperature, T J ( o C) Dropout Voltage, VDROP (mv) V CNTL = 5V =.05V Dropout Voltage vs. Output Current T J = 00 C T J = 5 C T J = - 40 C T J = 5 C Current-Limit, ILIM (A) V CNTL = 5V Current-Limit vs. Junction Temperature Sinking Current Sourcing Current Output Current, I OUT (A) Junction Temperature, T J ( o C) 5 4 V CNTL = 5V = 0.75V Offset Voltage vs. Junction Temperature 5 4 V CNTL = 3.3V = 0.75V Offset Voltage vs. Junction Temperature Offset Voltage, VOFFSET (mv) I OUT=-0mA I OUT=+0mA Offset Voltage, VOFFSET (mv) I OUT=+0mA I OUT=-0mA Junction Temperature, T J ( o C) Rev. A. - Nov., Junction Temperature, T J ( o C)

7 Typical Operating Characteristics (Cont.) Offset Voltage, VOFFSET (mv) V CNTL = 5V = 0.675V Offset Voltage vs. Junction Temperature I OUT=-0mA I OUT=+0mA Offset Voltage, VOFFSET (mv) V CNTL = 3.3V = 0.675V Offset Voltage vs. Junction Temperature I OUT=-0mA I OUT=+0mA Junction Temperature, T J ( o C) Junction Temperature, T J ( o C) Rev. A. - Nov., 05 7

8 Operating Waveforms Refer to the typical application circuit. The test condition is V CNTL =5V, T A = 5 o C unless otherwise specified. Power On Power Off V CNTL V CNTL V IN V IN V REF 3 V REF V CNTL =5V, V IN =.5V, I OUT =A CH: V CNTL, V/Div, DC CH: V IN, 0.5V/Div, DC CH3: V REF, 0.5V/Div, DC CH4:, 0.V/Div, DC TIME: ms/div V CNTL =5V, V IN =.5V, I OUT =A CH: V CNTL, V/Div, DC CH: V IN, 0.5V/Div, DC CH3: V REF, 0.5V/Div, DC CH4:, 0.V/Div, DC TIME: 500µs/Div Load Transient Response Load Transient Response I OUT I OUT I OUT =4mA to A to 4mA (rise / fall time = µs) V CNTL =5V, V IN =.35V, =0.675V CH:, 0mV/Div, DC offset 0.675V CH: I OUT, A/Div, DC TIME: 0µs/Div I OUT = -4mA to -A to -4mA (rise / fall time = µs) V CNTL =5V, V IN =.35V, =0.675V CH:, 0mV/Div, DC offset 0.675V CH: I OUT, A/Div, DC TIME: 5µs/Div Rev. A. - Nov., 05 8

9 Operating Waveforms(Cont.) Refer to the typical application circuit. The test condition is V CNTL =5V, T A = 5 o C unless otherwise specified. Load Transient Response Load Transient Response I OUT I OUT I OUT =4mAto Ato 4mA(rise /falltime =µs) V CNTL =5V, V IN =.5V, =0.75V CH:, 0mV/Div, DC offset 0.75V CH: I OUT, A/Div, DC TIME: 0µs/Div V CNTL =5V, V IN =.5V, =0.75V CH:, 0mV/Div, DC offset 0.75V CH: I OUT, A/Div, DC TIME: 5µs/Div Load Transient Response Load Transient Response I OUT I OUT I OUT =Ato-Ato A V CNTL =5V, V IN =.35V, =0.675V CH:, 50mV/Div, DC offset 0.675V CH: I OUT, A/Div, DC TIME: 5µs/Div I OUT =Ato-Ato A V CNTL =5V, V IN =.5V, =0.75V CH:, 50mV/Div, DC offset 0.75V CH: I OUT, A/Div, DC TIME: 5µs/Div Rev. A. - Nov., 05 9

10 Operating Waveforms(Cont.) Refer to the typical application circuit. The test condition is V CNTL =5V, T A = 5 o C unless otherwise specified. Load Transient Response Over Current Protection V IN, I OUT I OUT 3 I OUT =Ato-Ato A V CNTL =5V, V IN =.8V, =0.9V CH:, 50mV/Div, DC offset 0.9V CH: I OUT, A/Div, DC TIME: 5µs/Div V IN =.5V, =0.75V, I OUT =Ato 3A CH: V IN, 0.5V/Div, DC CH:, 0.5V/Div, DC CH3: I OUT, A/Div, DC TIME: 0µs/Div, DC Enable Shutdown V EN V EN I OUT 3 I OUT 3 V IN =.8V, V REF =.8V, I OUT =A CH: V EN, 5V/Div, DC CH:, 0.V/Div, DC CH3: I OUT, A/Div, DC TIME: 50µs/Div V IN =.8V, V REF =.8V, I OUT =A CH: V EN, 5V/Div, DC CH:, 0.V/Div, DC CH3: I OUT, A/Div, DC TIME: 5µs/Div Rev. A. - Nov., 05 0

11 Block Diagram VCNTL VIN VCNTL EN 3µA 0.8V Enable THSD Control Logic and Soft-Start POR Power-On- Reset VREF Thermal Shutdown Soft-Start Error Amplifier VOUT R H 00kΩ R L 00kΩ Current Limit GND VOSNS Rev. A. - Nov., 05

12 Typical Application Circuit = 0.9V/0.75V/0.675V Application V CNTL +5V C µf 0 V IN +.8V/+.5V/+.35V Enable EN C 0µF 6, 7, 8 9 VCNTL VIN VREF VOUT APL5339 EN VOSNS GND 3, 4, 5 C 3 0µF (X5R/X7R) = V REF C 4 00µF (Optional) +0.9V/+0.75V/+0.65V -A ~ +A The ceramic capacitor C3 ( at least 8µF) is necessary for output stability. General Application V CNTL +5V V IN C µf V REF C 0µF 6, 7, 8 9 VIN VREF 0 VCNTL Enable EN C 3 µf EN VOUT APL5339 VOSNS GND 3, 4, 5 R R C 3 0µF (X5R/X7R) C 4 00µF (Optional) V OUT R = V + REF R The ceramic capacitor C3 ( at least 8µF) is necessary for output stability. Rev. A. - Nov., 05

13 Function Description Power-On-Reset(POR) A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR votage thresholds during powering on. Output Voltage Regulation The output voltage on VOUT pin is regulated to track the reference voltage applied on VREF pin. Two internal N- channel power MOSFETs controlled by high bandwidth error amplifiers regulate the output voltage by sourcing current from VIN pin or sinking current to GND pin. An internal output voltage sense pad is bonded to the VOUT pin with a bonding wire for perfect load regulation. For preventing the two power MOSFETs from shootthrough, a small voltage offset between the positive inputs of the two error amplifiers is designed. It results in higher output voltage while the regulator sinks light or heavy load current. Thermal Shutdown An thermal shutdown circuit limits the junction temperature of the APL5339. When the junction temperature exceeds T J = +70 o C, a thermal sensor turns off the both pass transistors, allowing the device to cool. The thermal sensor allows the regulator to regulate again after the junction temperature cools by 50 o C, resulting in a pulsed output during continuous thermal overload conditions. The thermal limit designed with a 50 o C hysteresis lowers the average T J during continuous thermal overload conditions, increasing life time of the APL5339. Enable/Shutdown The APL5339 has a dedicated enable pin (EN). A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (3µA typical) to enable normal operation. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The typical soft-start interval is about 0.5 ms. Current-Limit Protection The APL5339 monitors the output current, both sourcing and sinking current, and limits the maximum output current to prevent damages during current overload or shortcircuit (shorten from VOUT to GND or VIN) conditions. Rev. A. - Nov., 05 3

14 Application Information Power Sequencing The input sequencing of VIN and VCNTL is not necessary to be concerned. Input Capacitor Selection The APL5339 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic inductors from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the input current, more parasitic inductance needs more input capacitance. For the APL5339, the total capacitance of input capacitors value including MLCC and aluminum electrolytic capacitors should be larger than 0µF. For VCNTL pin, a capacitor of µf (MLCC) or above is recommended for noise decoupling. Output Capacitor Selection The APL5339 needs a proper output capacitor to maintain circuit stability and improve transient response. In order to insure the circuit stability, a 0µF X5R or X7R MLCC output capacitor is sufficient at all operating temperatures and it must be placed near the VOUT. The maximum distance from output capacitor to VOUT must within mm. Total output capacitors value including MLCC and aluminum electrolytic capacitors should be larger than 0µF. Table provides the suitable output capacitors for APL5339. Table : Output Capacitor Guide Vendor Description 0µF, 6.3V, X7R, 0805, GRMBR70J06K Murata 0µF, 6.3V, X5R, 0805, GRMBR60J06K Murata website: Operation Region and Power Dissipation Where (T J -T A ) is the temperature difference between the junction and ambient air. θ JA is the thermal resistance between junction and ambient air. Assuming the T A =5 o C and maximum T J =50 o C (Absolute Maximum Rating), the maximum power dissipation is calculated as: (50 5) P D(max) = =.08(W) 60 For normal operation, do not exceed the maximum junction temperature of T J = 5 o C. The calculated power dissipation should less than: (5 5) P D = =.67(W) 60 PCB Layout Considerations Figure illustrates the layout. Below is a checklist for your layout:. Please place the input capacitors close to the VIN.. Please place the output capacitors close to the VOUT, a MLCC capacitor larger than 8µF must be placed near the VOUT. The distance from VOUT to output MLCC must be less than mm. 3. To place APL5339 and output capacitors near the load is good for load transient response. 4. Large current paths, the bold lines in Figure, must have wide tracks. 5. VREF should be connected to VIN by a separate track. VREF is the reference voltage of VOUT, so avoid any noise to get into the VREF. 6. Place the R and R near the APL5339 as close as possible to avoid noise coupling. 7. Connect the ground of the R to the GND pin by using a dedicated track. 8. Connect the one pin of the R to the load for Kelvin sensing. The APL5339 maximum power dissipation depends on the thermal resistance and temperature difference between the die junction and ambient air. The power dissipation P D across the device is: (TJ TA ) PD θ JA Rev. A. - Nov., 05 4

15 Application Information (Cont.) PCB Layout Considerations (Cont.) V CNTL C CNTL C IN VCNTL VIN V IN VREF VOUT APL5339 C OUT VOSNS GND R R Load Figure. Recommanded Minimum Footprint 0.04 The via diameter = Hole size = TDFN3x3-0 Unit: Inch Rev. A. - Nov., 05 5

16 Package Information TDFN3x3-0 D A Pin E Pin Corner L K E b D A A3 NX aaa C e S Y M B O A L MIN. MAX. A A3 b D D E E e L K aaa MILLIMETERS 0.0 REF TDFN3*3-0 MIN INCHES REF MAX BSC 0.00 BSC Note:.Followed from JEDEC MO-9 VEED-5. Rev. A. - Nov., 05 6

17 Carrier Tape & Reel Dimensions A B B A SECTION A-A Note :. 0 sprocket hole pitch cumulative tolerance ±0. SECTION B-B. Material: conductive polystyrene 3. Ao and Bo measured on a plane 0.3mm above the bottom of the pocket 4 Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier Note :. Followed from EIA-48 Application A H T C d D W E F 330± MIN MIN. 0. MIN..0± ± ±0.05 TDFN3x3-0 P0 P P D0 D T A0 B0 K0 4.0± ±0.0.0± MIN ± ±0.0.00±0.0 Devices Per Unit (mm) Package Type Unit Quantity TDFN 3*3-0 Tape & Reel 3000 Rev. A. - Nov., 05 7

18 Taping Direction Information TDFN3x3-0 USER DIRECTION OF FEED Classification Profile Rev. A. - Nov., 05 8

19 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (T smin) Temperature max (T smax) Time (T smin to T smax) (t s) 00 C 50 C 60-0 seconds 50 C 00 C 60-0 seconds Average ramp-up rate (T smax to T P) 3 C/second max. 3 C/second max. Liquidous temperature (T L) Time at liquidous (t L) Peak package body Temperature (T p)* Time (t P)** within 5 C of the specified classification temperature (T c) 83 C seconds 7 C seconds See Classification Temp in table See Classification Temp in table 0** seconds 30** seconds Average ramp-down rate (T p to T smax) 6 C/second max. 6 C/second max. Time 5 C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (T p) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (t p) is defined as a supplier minimum and a user maximum. Table. SnPb Eutectic Process Classification Temperatures (Tc) Package Thickness Volume mm 3 <350 Volume mm <.5 mm 35 C 0 C.5 mm 0 C 0 C Table. Pb-free Process Classification Temperatures (Tc) Package Thickness Volume mm 3 <350 Volume mm Volume mm 3 >000 <.6 mm 60 C 60 C 60 C.6 mm.5 mm 60 C 50 C 45 C.5 mm 50 C 45 C 45 C Reliability Test Program Test item Method Description SOLDERABILITY JESD-, B0 5 Sec, 45 C HOLT JESD-, A Hrs, T j=5 C PCT JESD-, A0 68 Hrs, 00%RH, atm, C TCT JESD-, A Cycles, -65 C~50 C HBM MIL-STD VHBM KV MM JESD-, A5 VMM 00V Latch-Up JESD 78 0ms, tr 00mA Rev. A. - Nov., 05 9

20 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : Fax : Taipei Branch : F, No., Lane 8, Sec Jhongsing Rd., Sindian City, Taipei County 346, Taiwan Tel : Fax : Rev. A. - Nov., 05 0