LSP2031 is a dual input, 3A ultra low dropout linear regulator. To achieve an extremely low dropout voltage,

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1 General Description LSP2031 is a dual input, 3A ultra low dropout linear regulator. To achieve an extremely low dropout voltage, LSP2031 has a control voltage input for the circuitry and a main supply voltage for power conversion. LSP2031 also has many useful features: A Power-On-Reset (POR) circuit inside that monitors the both two input voltages to prevent wrong operations. A PG pin indicates the output status with a fixed time delay. The thermal shutdown and current limit functions protect the LDO from thermal and current over-loads. LSP2031 is available in ESOP-8L package. Features Output Current up to 3A High Accuracy ADJ Voltage +/-1.5% Dropout Voltage 3A Typically V OUT Pull Low Resistance when Disable Internal Soft-Start Current-Limit and Thermal Shutdown Protection PG Output Pin with Built-in Delay Time Green Product Meet RoHS Standards EN Pin Internal Pulled High or Pulled Low Available in ESOP-8L Package Applications Motherboard Applications Notebook PC applications Telecom Applications Monitor/ Color TV applications Please be aware that an Important Notice concerning availability, disclaimers, and use in critical applications of LSC products is at the end of this document. LSP2031 Rev of 15

2 Block Diagram EN V CNTL V IN V OUT PG FB GND LSP2031 Rev of 15

3 Ordering Information LSP2031 X XX X X XXX Voltage Option Enable Pin Function Pin Count Package Type Pin-out Version Pin-out Version Package Type Pin Count Enable Pin Function Voltage Option A 1. PG AN : ESOP-8L G: 8 A : EN / Internal Pull High ADJ : Adjustable Output (ESOP-8L) 2. EN B : EN / Internal Pull Low 3. V IN C : ENB / Internal Pull High 4. V CNTL D : ENB / Internal Pull Low 5. NC 6. VOUT 7. FB 8. GND LSP2031 Rev of 15

4 Ordering Information (Contd.) LSP2031 X XX X X XXX Voltage Option Enable Pin Function Pin Count Package Type Pin-out Version Pin-out Version Package Type Pin Count Enable Pin Function Voltage Option B 1. PG AN : ESOP-8L G: 8 A : EN / Internal Pull High 120 : 1.2V (ESOP-8L) 2. EN B : EN / Internal Pull Low 150 : 1.5V 3. V IN C : ENB / Internal Pull High 180 : 1.8V 4. V CNTL D : ENB / Internal Pull Low 250 : 2.5V 5. NC 6. VOUT 7. NC 8. GND LSP2031 Rev of 15

5 Pin Assignment ESOP-8L Top View ESOP-8L Top View LSP2031AANG 1. PG 2. EN 3. V IN 4. V CNTL 5. NC 6. V OUT 7. FB 8. GND LSP2031BANG 1. PG 2. EN 3. V IN 4. V CNTL 5. NC 6. V OUT 7. NC 8. GND Pin Descriptions Pin Name Pin Description GND Ground FB Set The Output Volatge By External Feedback Resistors. V OUT Output Voltage EN/ENB (Optional) Enable/Disable pin. There are four options of this pin: A : EN / Internal Pull High B : EN / Internal Pull Low C : ENB / Internal Pull High D : ENB / Internal Pull Low PG Power Good Open Drain Output V CNTL Control Input Voltage V IN Input Voltage NC No Internal Connection LSP2031 Rev of 15

6 Absolute Maximum Ratings (Note1, at T A =25 C) Characteristics Symbol Rating Unit V CNTL Supply Voltage V CNTL 3.0 to 6.0 V V IN Supply Voltage V IN 1.0 to 6.0 V V OUT Voltage V OUT -0.3 to V IN+0.3 V EN, PG and FB Pin Voltage V EN, V PG, V FB -0.3 to V CNTL+0.3 V Storage Temperature Range T ST -65 to +150 C Junction Temperature Range T J +150 C Lead Temperature (Soldering, 10 Seconds) T Lead 260 C ESD Withstand Voltage: -Human Body Model (HBM), Model = 2 -Machine Model (MM) Model = B V ESD V V ESOP-8L Thermal Resistance (Junction to Ambient) ESOP-8L θ JA 84 C/W Power Dissipation ESOP-8L P D 1450 mw Moisture Sensitivity MSL Please refer the MSL label on the IC package bag/carton for detail Note 1 : Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2 : Devices are ESD sensitive. Handling precaution recommended. Note 3 : The I OUT of the LDO will be limited by the thermal protection, if the PCB design can t dissipate the heat generated by the LDO. Note 4 : θ JA is measured in the natural convection at T A = 25 C on a high effective thermal conductivity test board. LSP2031 Rev of 15

7 Recommended Operating Conditions (Note5) Characteristics Symbol Rating Unit V CNTL Supply Voltage V CNTL 3 to 5.5 V V IN Supply Voltage V IN 1 to 5.5 V Operating Junction Temperature Range T J -40 to 125 C Operating Ambient Temperature Range T A -40 to 85 C Note 5. The device is not guaranteed to function outside its operating conditions Note 6 : If the IC experienced OTP, then the temperature may need to drop to < OTP recover temperature to let the IC recover. LSP2031 Rev of 15

8 Electrical Characteristics (V CNTL= V EN=5V, V IN=V OUT(NOM)+0.5V, I OUT=1mA, C IN=C OUT=10uF MLCC, T A=25 C unless otherwise specified) Characteristics Symbol Conditions Min Typ Max Unit Supply Input Voltage Power Input Voltage Range V IN V V IN POR Threshold V POR_VIN V IN Rising V V IN POR Hysteresis V POR_VIN V IN Falling V Control Input Voltage Range V CNTL V POR Threshold V POR_VCNTL V CNTL Rising V POR Hysteresis V POR_VCNTL V CNTL Falling V Quiescent Current (Note 7) I Q V CNTL=5.5V, EN On, No Load ma Shutdown Current I Q_SD V IN=5V, EN Off ua Feedback Voltage Reference Voltage V FB V Fixed Output Voltage Accuracy % Dual Power Output Voltage Range V CNTL=5V, V IN=3.3V V IN -V DROP V Power Input Line Regulation V LINE V CNTL=3.6 to 5.5V V IN = V OUT+1V to 5V I OUT = 1mA % Load Regulation (Note 9) V LOAD I OUT=1mA ~ 3A, V OUT= V OUT+1V % I OUT = 2A Dropout Voltage V DROP mv I OUT = 3A V OUT Discharge R DS(ON) EN=Low Ω LSP2031 Rev of 15

9 Electrical Characteristics (Contd.) (V CNTL= V EN=5V, V IN=V OUT(NOM)+0.5V, I OUT=1mA, C IN=C OUT=10uF MLCC, T A=25 C unless otherwise specified) Characteristics Symbol Conditions Min Typ Max Unit Enable EN Pin Logic input threshold voltage V ENH V ENL V EN Delay Time ms EN Input Current I EN V EN=5V ua Control Input Current in Shutdown I SD V EN = 0V Enable Pin : Internal Pull High Enable Pin : Internal Pull Low ua Inrush Current I nrush V OUT=1.8V, C OUT= 10uF, I Load=1A A Soft Start Time T SS ms Power Good and Delay PG Threshold Voltage for Power Good PG Threshold Voltage for Power Not Good V PG V FB Rising % V PGNOK V FB Falling % PG Sink Capability Isink=10mA V PG Delay Time ms Protection Function Current Limit (Note 8) I LIM V IN=3.6V A Short Circuit Current (Note 10) I SC V OUT <0.2V A Thermal Shutdown Temperature (Note 10) Thermal Shutdown Recovery Temperature (Note 10) T SD T SDR C Note 7. Quiescent Current is defined by I Q =I IN-I OUT (I OUT=0mA) Note 8. Current limit and short circuit current are measured at constant junction temperature by using pulsed testing with a low ON time. Note 9. Load Regulation is measured at constant junction temperature by using pulsed testing with a low ON time. Note 10. Guarantee by design. Not test when manufacture LSP2031 Rev of 15

10 Application Circuit EN PG V CNTL V OUT V IN GND FB r VOUT = 0.8 x (R1+R2)/R2 Figure 1. Adjustable Voltage Regulator EN PG V CNTL V OUT V IN GND FB Figure 2. Fixed Voltage Regulator LSP2031 Rev of 15

11 Function Descriptions Input Capacitor The LSP2031 family of positive CMOS linear regulators provides ultra low-dropout voltage, high output current with low ground current, very low input voltage and very low dropout voltage at up to 3A. It operates with a VIN as low as 1V and VCNTL voltage 3V with output voltage programmable as low as 0.8V. Enable The LSP2031 has a dedicated enable pin, when this pin is in the logic low condition, the MOS pass transistor shuts off, and all internal circuits are powered down. For LSP2031(A/C), the EN/ENB pin is pulled up by an internal resistor to enable normal operation. So the regulator will be turn on when EN pin is floating. It is not necessary to use an external pull up resistor to save cost. For LSP2031(B/D), the EN/ENB pin is pulled low by an internal resistor to enable normal operation. So the regulator will be turn off when EN pin is floating. It is not necessary to use an external pull low resistor to save cost. Soft-Start The LSP2031 features a soft start function that limits inrush current. The soft start time is typically 1.4ms. Current-Limit The LSP2031 contains an independent current limit and short circuit current protection to prevent damage during fault conditions. The current limit monitors and controls the pass transistor's gate voltage, limiting the output current to higher than 4.5A typical. Short Circuit Current-Limit The short circuit current-limit function reduces the current-limit level down to 1.5A (typical) when short circuit conditions. LSP2031 Rev of 15

12 Thermal Shutdown A thermal shutdown circuit limits the junction temperature of LSP2031. When the junction temperature exceeds 160 o C, the over-temperature protection circuit turns off the pass transistor allowing the device to cool down, The pass transistor turns on again after the junction temperature cools by 30 o C. Power Good and Delay The power good function is an open-drain output. Connects a 100kΩ pull up resistor to V OUT to obtain an output voltage. The PG pin will go high 3mS (typ) after the output voltage arrives at 90% of normal output voltage. Application Descriptions Input Capacitor The input capacitance is at least 10µF located as close as possible to the IC is recommended. Output Capacitor The LSP2031 is stable with an output capacitor to ground of 10uF or greater. The output capacitor selection is dependent on ESR (equivalent series resistance) and capacitance of the output capacitor over the desired operating temperature. The Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-esr bulk capacitors (such as solid tantalum, POS Cap, and Aluminum electrolytic capacitors) can all be used as output capacitors. For applications with large load current transitions, low-esr bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed as close as possible to the load and ground pins. The impedance of the layout must be minimized. Setting Output Voltage The output voltage is programmed by the resistor divider connected to the FB pin. The output voltage is given by the following equation: The feedback resistor of resistance value support > 100K ohm and no require forward capacitor. LSP2031 Rev of 15

13 Marking Information (1) ESOP-8L 1) = Marking Name 2031E = LSP2031AANGAADJ 2031A = LSP2031AANGBADJ 2031C = LSP2031AANGCADJ 2031D = LSP2031AANGDADJ 2031B12 = LSP2031BANGA B15 = LSP2031BANGA B18 = LSP2031BANGA B25 = LSP2031BANGA F12 = LSP2031BANGB F15 = LSP2031BANGB F18 = LSP2031BANGB F25 = LSP2031BANGB G12 = LSP2031BANGC G15 = LSP2031BANGC G18 = LSP2031BANGC G25 = LSP2031BANGC H12 = LSP2031BANGD H15 = LSP2031BANGD H18 = LSP2031BANGD H25 = LSP2031BANGD250 2) YWWSS = Date Code Y = Year WW = Week SS = Internal Code LSP2031 Rev of 15

14 Mechanical Information ESOP-8L LSP2031 Rev of 15

15 MSL (Moisture Sensitive Level) Information IPC/JEDEC J-STD-020D.1 Moisture Sensitivity Levels Table FLOOR LIFE LEVEL TIME CONDITION 1 Unlimited 30 C /85% 2 1 year 30 C /60% 2a 4 weeks 30 C /60% hours 30 C /60% 4 72 hours 30 C /60% 5 48 hours 30 C /60% a 24 hours 30 C /60% 6 Time on Label 30 C /60% (TOL) SOAK REQUIREMENTS Accelerated Equivalent 1 Standard ev ev CONDITION TIME TIME TIME CONDITION (hours) (hours) (hours) C /85% +5/-0 NA NA NA C /60% +5/-0 NA NA NA C /60% /-0-1/+0-1/+0 60 C/ 60% C /60% /-0-1/+0-1/+0 60 C/ 60% C /60% / / /-0 60 C/ 60% C /60% / / /-0 60 C/ 60% C /60% / / /-0 60 C/ 60% TOL 30 C /60% NA NA NA Note 1: CAUTION - To use the accelerated equivalent soak conditions, correlation of damage response (including electrical, after soak and reflow), should be established with the standard soak conditions. Alternatively, if the known activation energy for moisture diffusion of the package materials is in the range of ev or ev, the accelerated equivalent may be used. Accelerated soak times may vary due to material properties (e.g.mold compound, encapsulant, etc.). JEDEC document JESD22- A120 provides a method for determining the diffusion coefficient. Note 2: The standard soak time includes a default value of 24 hours for semiconductor manufacturer s exposure time (MET) between bake and bag and includes the maximum time allowed out of the bag at the distributor s facility. If the actual MET is less than 24 hours the soak time may be reduced. For soak conditions of 30 C/60%, the soak time is reduced by 1 hour for each hour the MET is less than 24 hours. For soak conditions of 60 C/60%, the soak time is reduced by 1 hour for each 5 hours the MET is less than 24 hours. If the actual MET is greater than 24 hours the soak time must be increased. If soak conditions are 30 C/60%, the soak time is increased 1 hour for each hour that the actual MET exceeds 24 hours. If soak conditions are 60 C/60%, the soak time is increased 1 hour for each 5 hours that the actual MET exceeds 24 hours. Important Notice and Disclaimer LSC reserves the right to make changes to this document and its products and specifications at any time without notice. Customers should obtain and confirm the latest product information and specifications before final design, purchase or use. LSC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does LSC assume any liability for application assistance or customer product design. LSC does not warrant or accept any liability with products which are purchased or used for any unintended or unauthorized application. No license is granted by implication or otherwise under any intellectual property rights of LSC. LSP2031 Rev of 15