Applications. Simplified Application Circuit. Pin Configuration. Power-Distribution Switches with Soft Start SOP-8P. (Top View)
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1 Power-Distribution Switches with Soft Start Features 84mW High Side MOSFET Soft Start Time Programmable by External Capacitor Wide Supply Voltage Range: 4.5V to 4V Current Limit Protections Under Voltage Lockout Protection Over- temperature Protection Logic Level Enable Input Lead Free and Green Devices Available (RoHS Compliant) Current Limit setting Applications TFT LCD Modules Notebook and Desktop Computers USB Ports High-side Power Protection Switches Simplified Application Circuit General Description The APL3547A is a power-distribution switch with some protection functions. The device incorporates a N channel MOSFET power switch that is controlled by an enable logic pin and has a SS pin dedicated to soft start ramp-up rate control that can be used in application where the inrush current is concerned. The device integrates some protection features, including current-limit protection, short-circuit protection, overtemperature protection, and UVLO. The current-limit and short-circuit protection can protect down-stream devices from catastrophic failure by limiting the output current at current-limit threshold during over-load or short-circuit events. When VOUT drops below VIN-V, the devices limit the output current to a lower and safe level. The overtemperature protection function shuts down the N-channel MOSFET power switch when the junction temperature rises beyond 50 o C and will automatically turns on the power switch when the temperature drops by 50 o C. The UVLO function keeps the power switch in off state until there is a valid input voltage present. The current limit in APL3547A can be set by connecting resistor from the current limit adjustable pin ISET to ground. The device is available in lead free SOP-8P and TDFNx- 6 packages. Pin Configuration APL3547A VIN SS 6 GND 5 VOUT ISET VIN VOUT GND 3 4 EN SS ISET TDFNx-6 (Top View) EN GND VIN SS GND 3 GND 8 VOUT 7 ISET 6 EN NC 4 5 NC SOP-8P (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders.
2 Ordering and Marking Information APL3547A Assembly Material Handling Code Temperature Range Package Code Package Code KA : SOP-8P QB: TDFNx-6 Operating Ambient Temperature Range I : -40 o C to 80 o C Handling Code TR : Tape & Real Assembly Material G : Halogen and Lead Free Device APL3547A KA: APL3547A XXXXX XXXXX - Date Code APL3547A QB : 47A X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 00% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-00D for MSL classification at lead-free peak reflow temperature. ANPEC defines Green to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 500ppm by weight). Absolute Maximum Ratings (Note ) Symbol Parameter Rating Unit V IN VIN to GND Voltage -0.3 ~ 6.5 V V OUT VOUT to GND Voltage -0.3 ~ 6.5 V V EN EN to GND Voltage -0.3 ~ 7 V V ISET ISET to GND Voltage -0.3 ~ 7 V V SS SS to GND Voltage -0.3 ~ 7 V I OUT IOUT output current Setting by R ISET A T J Maximum Junction Temperature -40 ~ 50 T STG Storage Temperature -65 ~ 50 T SDR Maximum Lead Soldering Temperature (0 Seconds) 60 Note: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. o C o C o C
3 Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Junction-to-Ambient Resistance in free air SOP-8P 50 TDFNx-6 75 o C/W Note : θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit V IN VIN Input Voltage 4.5 ~ 4 V C SS_MIN Minimum SS Pin Soft-Start Capacitor nf T A Ambient Temperature -40 ~ 85 T J Junction Temperature -40 ~ 5 o C o C Note 3: Refer to the application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over V IN =V, V EN =5V. Typical values are at T A =5 o C. Symbol Parameter Test Conditions SUPPLY CURRENT APL3547A Min Typ Max Unit VIN Supply Current No load, V EN=0V µa No load, V EN =5V µa POWER SWITCH Leakage Current V OUT=GND, V EN=0V - - µa R DS(ON) Power Switch On Resistance I OUT=A, T A= 5 o C,V IN=V mω I OUT=A, V IN =V mω UNDER-VOLTAGE LOCKOUT VIN UVLO Threshold Voltage V IN rising, V VIN UVLO Hysteresis V CURRENT LIMIT AND SHORT CIRCUIT PROTECTIONS Short Circuit Voltage Threshold - - V V ISET Current Limit Voltage V I OC Over Current Trip Threshold R ISET =8kΩ,TA=5 o C A Short Circuit Current A SOFT-START CONTROL PIN I SS SS Current V IN=V, 3 µa t SS Soft-Start Time V IN=V, No load, C OUT=uF, C SS =nf ms V IN=V, No load, C OUT=uF, C SS =open 3 ms Soft-Start Discharge Resistance V EN =0V 50 Ω 3
4 Electrical Characteristics Unless otherwise specified, these specifications apply over V IN =V, V EN =5V. Typical values are at T A =5 o C. Symbol Parameter Test Conditions EN INPUT PIN APL3547A Min Typ Max Unit V IH Input Logic High - - V V IL Input Logic Low V Input Current - - µa VOUT Discharge Resistance V EN=0V Ω t D(ON) Turn on Delay Time µs t D(OFF) Turn off Delay Time µs OVERT-TEMPERATURE PROTECTION (OTP) TOTP Over-Temperature Threshold T J rising C Over-Temperature Threshold Hysteresis T J falling C 4
5 Pin Description SOP-8P PIN TDFNx-6 NAME Description VIN Power Supply Input. Connect this pin to external DC supply. SS Soft Start Control Pin. Connect a capacitor to GND to control the soft start rate. 3, 9 3, 7 GND GND. 4 - NC No connection. 5 - NC No connection. 6 4 EN Enable Input. Pull this pin to high to enable the device and pull this pin to low to disable device. The EN pin cannot be left floating. 7 5 ISET Connect a resistor to GND to adjust OCP level. 8 6 VOUT Output Voltage Pin. The output voltage follows the input voltage. When EN is low the output voltage is discharged by an internal resistor. 5
6 Typical Operating Characteristics VIN Supply Current (µa) On Resistance (mω) EN Logic Threshold (V) VIN Supply Current vs. VIN Supply Voltage EN=high EN=low T A =5 o C VIN Supply Voltage (V) On Resistance vs. VIN Supply Voltage T A =5 o C SOP-8P TDFNx VIN Supply Voltage (V) EN Logic Threshold Voltage vs. VIN Supply Voltage T A =5 o C, sweep V EN rising VIN Supply Voltage (V) Over Current Trip Threshold, IOC (A) Over Current Trip Threshold (A) VOUT Leakage Current (ua) Over Current Trip Thrshold vs. R ISET Resistance V IN =V V IN =5V R ISET Resistance (kω) Over Current Trip Threshold vs. Junction Temperature V IN =V, R ISET=80kΩ Junction Temperature ( o C) VOUT Leakage Current vs. Junction Temperature V IN = V, EN=low, V OUT short to ground Junction Temperature ( T A=5 o C o C ) 6
7 Typical Operating Characteristics VIN Supply Current vs. Junction Temperature V IN = V 40 0 On Resistance vs. Junction Temperature VIN Supply Current (µa) EN=high EN=low On Resistance (mω) TDFNx-6, V IN = V Junction Temperature ( o C) Junction Temperature ( o C ) 7
8 Operating Waveforms The test condition T A = 5 o C unless otherwise specified. Turn On Response Turn Off Response V EN V EN V OUT V OUT V IN =V, C IN =0uF/MLCC, C OUT =33µF/Electrolytic, No R LOAD, C SS =4.7nF CH: V EN, 5V/Div, DC CH: V OUT, 5V/Div, DC TIME: ms/div V IN =V, C IN =0uF/MLCC, C OUT =33µF/Electrolytic, No R LOAD, C SS =4.7nF CH: V EN, 5V/Div, DC CH: V OUT, 5V/Div, DC TIME: ms/div UVLO at Rising UVLO at Falling V IN V IN V OUT V OUT V IN =V, C IN =0uF/MLCC, C OUT =33µF/Electrolytic, No R LOAD, C SS =47nF CH: V IN, 5V/Div, DC CH: V OUT, 5V/Div, DC TIME: 5ms/Div V IN =V, C IN =0uF/MLCC, C OUT =33µF/Electrolytic, No R LOAD, C SS =47nF CH: V IN, 5V/Div, DC CH: V OUT, 5V/Div, DC TIME: 5ms/Div 8
9 Operating Waveforms The test condition T A = 5 o C unless otherwise specified. Softstart with Different C SS Capacitor Over Current Response with Ramped Load V EN V OUT V OUT I OUT C SS=4.7nF C SS=47nF C SS=00nF V IN =V, C IN =0uF/MLCC, C OUT =33µF/Electrolytic, No R LOAD, C SS =4.7/47/00nF CH: V EN, 5V/Div, DC CH: V OUT, 5V/Div, DC TIME: 0ms/Div V IN =V, C IN =0uF/MLCC, C OUT =33µF/Electrolytic,R ISET=00kΩ CH: V OUT, 5V/Div, DC CH: I OUT, A/Div, DC TIME: ms/div Short Circuit Response Device Enabled into Short Circuit V IN V EN V OUT V OUT I OUT I VIN 3 3 V IN =V, C IN =47uF/MLCC, C OUT =µf/mlcc, R ISET=00kΩ, V EN =5V, VOUT short to ground CH: V IN, 5V/Div, DC CH: V OUT, 5V/Div, DC CH3: I OUT, 0A/Div, DC TIME: µs/div V IN =V, C IN =0uF/MLCC, VOUT short to ground then EN power on CH: V EN, 5V/Div, DC CH: V OUT, 5V/Div, DC CH3: I VIN, 00mA/Div, DC TIME: ms/div 9
10 Operating Waveforms The test condition T A = 5 o C unless otherwise specified. Short Circuit Release Load Transient V OUT V IN V OUT I OUT I OUT 3 V IN =V, C IN =0uF/MLCC, C OUT =0µF/Electrolytic, No R LOAD, C SS =47nF CH: V EN, 5V/Div, DC CH: I OUT, 00mA/Div, DC TIME: 0ms/Div V IN =V, C IN =0uF/Electrolytic, C OUT =33µF/Electrolytic, R ISET=00kΩ, I OUT=0-3-0A CH: V IN, V/Div, Offset=V CH: V OUT, V/Div, Offset=V CH3: I OUT, A/Div, DC TIME: ms/div 0
11 Block Diagram ISET VIN VOUT UVLO Charge Pump Current Limit EN Gate Driver and Control Logic Soft Start SS OTP GND
12 Typical Application Circuit APL3547A VIN VIN VOUT VOUT uf 0uF nf SS ISET controller EN GND R ISET
13 Function Description Under-voltage Lockout (UVLO) The APL3547A power switch is built-in an under-voltage lockout circuit to keep the output shuts off until internal circuitry is operating properly. The UVLO circuit has hysteresis and a de-glitch feature so that it will typically ignore undershoot transients on the input. When input voltage exceeds the UVLO threshold, the output voltage starts a soft-start to reduce the inrush current. Current Limit Protection The APL3547A power switch provides the current limit protection. During current limit, the devices limit output current at current limit threshold. For reliable operation, the device should not be operated in current limit for extended period time. Short Circuit Protection When the output voltage drops below VIN-V, which is caused by the over load or short-circuit, or at the very beginning of the softstart when VOUT<V, the devices limit the output current down to a safe level. The short circuit current-limit is used to reduce the power dissipation during short-circuit condition. If the junction temperature is over the thermal shutdown temperature, the device will enter the thermal shutdown. Soft-Start The APL3547A provides an adjustable soft-start circuitry to control rise rate of the output voltage and limit the current surge during start-up. The soft-start ramp-up rate is controlled by a capacitor from SS pin to ground. the soft start time can be calculated by this following equation: t SS = 0.(C SS X V IN )/I SS where, tss is soft start time of VOUT rising from 0 to 00%, of which unit is second. C SS is the value of the capacitor connected from SS pin to GND, of which unit is micro-farad. V IN is the amplitude of input voltage applied to this device, of which unit is volt. I SS is the SS pin charge current. If the SS pin is left floating the soft start time is ms when V IN =V. Enable/Disable Pull the EN below 0.6V to disable the device and pull EN above V to enable the device. When the IC is disabled the supply current is reduced to less than 30µA. The enable input is compatible with both TTL and CMOS logic levels. The EN pin cannot be left floating. VOUT Softstart Softstart V 0V VOUT short to GND Current Limit Iout=Ishort=00mA IOUT Iout=Ishort=00mA Iout=Iload 0A EN 0V Over load Over-Temperature Protection When the junction temperature exceeds 50 o C, the internal thermal sense circuit turns off the power FET and allows the device to cool down. When the device s junction temperature cools by 50 o C, the internal thermal sense circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of over-temperature conditions. For normal operation, the junction temperature cannot exceed T J =5 o C. time 3
14 Application Information Input Capacitor A µf or higher ceramic bypass capacitor from VIN to GND, located near the APL3547A, is strongly recommended to suppress the ringing during over-load or short-circuit fault event. Without the bypass capacitor, the over-load or output short may cause sufficient ringing on the input (from supply lead inductance) to damage internal control circuitry. Input capacitor is especially important to prevent VIN from ringing too high in some applications where the inductance between power source to VIN is large due to poor PCB layout or purposely adding an inductive component in front of VIN pin. When the VIN s supply voltage is higher, say 9V or 4V, it is required to add some adequate amount of capacitance of input capacitor into VIN pin for overshoot suppression because a slight ringing of VIN is most likely to exceed VIN s absolute maximum rating, or else the device could be burnout during over load conditions. Output Capacitor A low-esr 0µF MLCC, aluminum electrolytic or tantalum between VOUT and GND is strongly recommended to reduce the voltage droop during hot-attachment of downstream peripheral. Higher-value output capacitor is better when the output load is heavy. Additionally, bypassing the output with a 0.µF ceramic capacitor improves the immunity of the device to short-circuit transients. Layout Consideration The PCB layout should be carefully performed to maximize thermal dissipation and to minimize voltage drop, droop and EMI. The following guidelines must be considered:. Please place the input capacitors near the VIN pin as close as possible.. Output decoupling capacitors for load must be placed near the load as close as possible for decoupling high frequency ripples. 3. Locate APL3547A and output capacitors near the load to reduce parasitic resistance and inductance for excellent load transient performance. 4. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 5. Keep VIN and VOUT traces as wide and short as possible. Soft-Start Capacitor The APL3547A has a built-in adjustable soft-start control for user to set an optimum soft-start time for the application. The soft-start time can be calculated by the equation, described in the paragraph of Soft-Start in Functional Description section. Please note that there is minimum value of soft start capacitor in different VIN input voltage. Please make sure the C SS is in the recommended value. Current Limit Setting The current limit can be set by connecting resistor from the current limit adjustable pin ISET to ground. The required value of resistor RISET for current limit is calculated as follows: R ISET = / I LIM 4
15 Package Information SOP-8P D SEE VIEW A D THERMAL PAD E E h X 45 o E e b c A A NX aaa c A L θ 0.5 GAUGE PLANE SEATING PLANE VIEW A A b c D E e h L S Y M B O L A A E MIN o C MILLIMETERS.7 BSC MAX SOP-8P MIN D E INCHES BSC Note :. Followed from JEDEC MS-0 BA.. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0 mil per side. MAX o C 0 o C 8 o C aaa
16 Package Information TDFNx-6 D A b E D A A3 Pin Corner L K E S Y M MILLIMETERS B O L MIN. MAX. A A A3 b D D E E e L e 0.0 REF TDFNx-6 MIN INCHES REF MAX BSC 0.06 BSC K Note :. Followed from JEDEC MO-9 WCCC. 6
17 Carrier Tape & Reel Dimensions OD0 P0 P P A W F E OD B A T B0 K0 B A0 SECTION A-A SECTION B-B d H A T Application A H T C d D W E F TDFNx ± MIN MIN. 0. MIN. 8.0±0.0.75± ±0.05 P0 P P D0 D T A0 B0 K0 4.0± ±0.0.0± MIN ±0.0.35±0.0.00±0.0 Application A H T C d D W E F SOP-8P 330.0± MIN MIN. 0. MIN..0± ± ±0.05 P0 P P D0 D T A0 B0 K0 4.0± ±0.0.0± MIN ± ±0.0.0±0.0 (mm) Devices Per Unit Package Type Unit Quantity TDFNx Tape & Reel 3000 SOP-8P Tape & Reel 500 7
18 Taping Direction Information SOP-8P USER DIRECTION OF FEED TDFNx-6 USER DIRECTION OF FEED 8
19 Classification Profile 9
20 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (T smin) Temperature max (T smax) Time (T smin to T smax) (t s) 00 C 50 C 60-0 seconds 50 C 00 C 60-0 seconds Average ramp-up rate (T smax to T P) 3 C/second max. 3 C/second max. Liquidous temperature (T L) Time at liquidous (t L) Peak package body Temperature (T p)* Time (t P)** within 5 C of the specified classification temperature (T c) 83 C seconds 7 C seconds See Classification Temp in table See Classification Temp in table 0** seconds 30** seconds Average ramp-down rate (T p to T smax) 6 C/second max. 6 C/second max. Time 5 C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (T p) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (t p) is defined as a supplier minimum and a user maximum. Table. SnPb Eutectic Process Classification Temperatures (Tc) Package Thickness Volume mm 3 <350 Volume mm <.5 mm 35 C 0 C.5 mm 0 C 0 C Table. Pb-free Process Classification Temperatures (Tc) Package Thickness Volume mm 3 <350 Volume mm Volume mm 3 >000 <.6 mm 60 C 60 C 60 C.6 mm.5 mm 60 C 50 C 45 C.5 mm 50 C 45 C 45 C Reliability Test Program Test item Method Description SOLDERABILITY JESD-, B0 5 Sec, 45 C HOLT JESD-, A Hrs, T j=5 C PCT JESD-, A0 68 Hrs, 00%RH, atm, C TCT JESD-, A Cycles, -65 C~50 C HBM MIL-STD VHBM KV MM JESD-, A5 VMM 00V Latch-Up JESD 78 0ms, tr 00mA 0
21 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : Fax : Taipei Branch : F, No., Lane 8, Sec Jhongsing Rd., Sindian City, Taipei County 346, Taiwan Tel : Fax :
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3A 5V 1MHz Synchronous Buck Converter Features High Efficiency up to 95% - Automatic Skip/PWM Mode Operation Adjustable Output Voltage from 0.6V to VIN Integrated 110mW High side 80mW Low Side MOSFET Low
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1.5MHz, 1A Synchronous Buck Regulator Features General Description 1A Output Current Wide 2.7V~6.0V Input Voltage Fixed 1.5MHz Switching Frequency Low Dropout Operating at 100% Duty Cycle 25mA Quiescent
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N-Channel Enhancement Mode MOSFET Features Pin Description 3V/5, R DS(ON) =7.5mΩ (typ.) @ =V R DS(ON) =12mΩ (typ.) @ =4.5V Super High Dense Cell Design Reliable and Rugged valanche Rated D G S Top View
More informationPackage Code S : SOP-8. Date Code YYXXX WW
N-Channel Enhancement Mode MOSFET Features 100 V/8 A R DS(ON) = 20 m Ω (typ.) @ V GS =10V Avalanche Rated Reliable and Rugged Lead Free and Green DevicesAvailable (RoHS Compliant) Pin Description D D D
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Li+ Charger Protection IC Features Provide Input Over-Voltage Protection Programmable Input Over-Current Protection Battery Over-Voltage 4.35V/4.435V Protection Over-Temperature Protection High Immunity
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More informationP-Channel Enhancement Mode MOSFET
Features -3V/-3, =46mΩ (typ.) @ V GS =-1V =55mΩ (typ.) @ V GS =-4.5V =79mΩ (typ.) @ V GS =-2.5V Super High Dense Cell Design Reliable and Rugged Enhance ESD Cell Protection Lead Free and Green Devices
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APW765 5V to V Synchronous Buck Controller Features Wide Operation Supply Voltage from 5V to V Power-On-Reset Monitoring on VCC Excellent Reference Voltage Regulations - 0.8V Internal Reference - ±% Over
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8-PIN Synchronous Buck PWM Controller Features General Description Operating with Single 5V or 1V Input Drives N-Channel MOSFETs Simple Single-Loop Control Design - Voltage-Mode PWM Control - Full 0% to
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5V to V Synchronous Buck Controller Features Wide Operation Supply Voltage from 5V to V Power-On-Reset Monitoring on VCC Excellent Reference Voltage Regulations - 0.8V Internal Reference - ±% Over-Temperature
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8882 n General Description n Typical Application The 8882A/B family of positive CMOS linear regulators provides ultra low-dropout voltage (240mV @2A) and low quiescent current (typically 600uA), thus making
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P-Channel Enhancement Mode MOSFET Features Pin Description -2V/-4, =48mΩ(typ.) @ V GS =-4.5V =85mΩ(typ.) @ V GS =-2.5V =135mΩ(typ.) @ V GS =-1.8V Super High Dense Cell Design Reliable and Rugged Lead Free
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P-Channel Enhancement Mode MOSFET Features Pin Description -2V/-4.9A, R DS(ON) =43mΩ (Max.) @ V GS =-4.5V R DS(ON) =58mΩ (Max.) @ V GS =-2.5V R DS(ON) =88mΩ (Max.) @ V GS =-1.8V 1% UIS + R g Tested Reliable
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N-Channel Enhancement Mode MOSFET Features Pin Description 3V/5, R DS(ON) =4.8mΩ (typ.) @ V GS =V R DS(ON) =7mΩ (typ.) @ V GS =4.5V Super High Dense Cell Design Reliable and Rugged Lead Free and Green
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