APL5913. General Description. Features. 0.8V Reference Ultra Low Dropout Linear Regulator

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1 0.8V Reference Ultra Low Dropout Linear Regulator Features General Description Ultra Low Dropout - 0.5V(typical) at 3A Output Current Low ESR Output Capacitor (Multi-layer Chip Capacitors (MLCC)) Applicable 0.8V Reference Voltage High Output Accuracy - ±.5% over Line, Load and Temperature Fast Transient Response Adjustable Output Voltage by External Resistors Power-On-Reset Monitoring on Both and Pins Internal Soft-Start Current-Limit Protection Under-Voltage Protection Thermal Shutdown with Hysteresis Power-OK Output with a Delay Time Shutdown for Standby or Suspend Mode Simple SOP-8-P Package with Exposed Pad Lead Free Available (RoHS Compliant) The APL593 is a 3A ultra low dropout linear regulator. This product is specifically designed to provide well supply volatage for front-side-bus termination on motherboards and NB applications. The IC needs two supply voltages, a control voltage for the circuitry and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The APL593 integrates many functions. A Power-On- Reset (POR) circuit monitors both supply voltages to prevent wrong operations. A thermal shutdown and current limit functions protect the device against thermal and current over-loads. A POK indicates the output status with time delay which is set internally. It can control other converter for power sequence. The APL593 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL593 is available in SOP-8-P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in ~3W applications. Pin Configuration Applications Front Side Bus VTT (.V/3A) Note Book PC Applications Motherboard Applications GND FB 3 4 SOP-8-P (Top View) = Exposed Pad (connected to plane for better heat dissipation) EN POK

2 Ordering and Marking Information APL593 - APL593 KA : APL593 XXXXX Lead Free Code Handling Code Temp. Range Package Code Package Code KA : SOP-8-P Operating Ambient Temp. Range C : 0 to 70 C Handing Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 00% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-00C for MSL classification at lead-free peak reflow temperature. Block Diagram EN Power- On-Reset UV 0.4V Soft-Start and Control Logic Thermal Limit VREF 0.8V EAMP FB Current Limit 90% VREF POK Delay GND POK

3 Typical Application Circuit. Using an Output Capacitor with ESR 8mΩ C CNTL uf +5V POK R3 k 7 POK 6 5 CIN 00uF +.5V Enable EN 8 APL593 EN FB GND 3 4 R k k +.V / 3A COUT 0uF C 33nF (in the range of ~ 48nF). Using an MLCC as the Output Capacitor C CNTL uf +5V POK R3 k 7 POK 6 5 CIN uf +.5V Enable EN 8 APL593 EN FB GND 3 4 R 78k 39k COUT uf +.V / 3A C 56pF (V) (kω) R (kω) C (pf)

4 Absolute Maximum Ratings Symbol Parameter Rating Unit Supply Voltage ( to GND) -0.3 ~ 7 V Supply Voltage ( to GND) -0.3 ~ 3.3 V VI/O EN and FB to GND -0.3 ~ +0.3 V VPOK POK to GND -0.3 ~ 7 V PD Average Power Dissipation 3 W PPEAK Peak Power Dissipation (<0mS) 0 W TJ Junction Temperature 50 TSTG Storage Temperature -65 ~ 50 TSDR Soldering Temperature, 0 Seconds 300 o C o C o C VESD Minimum ESD Rating (Human Body Mode) ± kv Thermal Characteristics Symbol Parameter Value Unit θja Junction-to-Ambient Thermal Resistance in Free Air (Note) 40 o C/W Note : θja is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB. Recommended Operating Conditions Symbol Parameter Range Unit Supply Voltage 3. ~ 6 V Supply Voltage. ~ 3.3 V Output Voltage =3.3±5% 0.8 ~. V =5.0±5% 0.8 ~ -0. IOUT Output Current 0 ~ 4 A TJ Junction Temperature -5 ~ 5 o C Electrical Characteristics Refer to the typical application circuit. These specifications apply over, = 5V, =.5V, =.V and TA = 0 to 70 C, unless otherwise specified. Typical values refer to TA = 5 C. Symbol Parameter Test Conditions APL593 Min Typ Max Unit SUPPLY CURRENT ICNTL Nominal Supply Current EN = ma ISD Shuntdown Current EN = GND µa 4

5 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over, = 5V, =.5V, =.V and TA = 0 to 70 C, unless otherwise specified. Typical values refer to TA = 5 C. Symbol Parameter Test Conditions POWER-ON-RESET OUTPUT VOLTAGE APL593 Min Typ Max Unit POR Threshold Rising V POR Hysteresis 0.4 V POR Threshold Rising POR Hysteresis 0.5 V VREF Reference Voltage FB = 0.8 V Output Voltage Accuracy IOUT=0A ~ 5A, TJ= -5 ~5 o C % Line Regulation =3.3 ~ 5V % Load Regulation IOUT=0A ~ 3A % DROPOUT VOLTAGE PROTECTION ILIM Dropout Voltage Current Limit IOUT = 3A, =5V, TJ= 5 o C V IOUT = 3A, =5V, TJ= -50~5 o C 0.3 V =5V, TJ= 5 o C A =5V, TJ= -5 ~ 5 o C 4 A =3.3V, TJ= 5 o C A =3.3V, TJ= -5 ~ 5 o C 3.8 A TSD Thermal Shutdown Temperature TJ Rising 50 Thermal Shutdown Hysteresis 50 Under-Voltage Threshold VFB Falling 0.4 V ENABLE and SOFT-START EN Logic High Threshold Voltage VEN Rising V EN Hysteresis 30 mv EN Pin Pull-Up Current EN=GND 0 µa TSS Soft-Start Interval ms POWER OK and DELAY VPOK POK Threshold Voltage for Power VFB Rising OK 90% 9% 94% VREF VPNOK POK Threshold Voltage for Power VFB Falling Not OK 79% 8% 83% VREF POK Low Voltage POK sinks 5mA V TDELAY POK Delay Time 3 0 ms o C o C 5

6 Typical Operating Characteristics Supply Current vs. Junction Temperature Current-limit vs. Junction Temperature Supply Current, ICNTL (ma) =5V =3.3V Current-limit, ILIM (A) =3.3V =5V Junction Temperature ( C) Junction Temperature ( C) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current =3.3V =.V TJ=5 C 50 =5V =.V Dropout Voltage (mv) TJ=5 C TJ=75 C TJ=-5 C TJ=0 C Dropout Voltage (mv) TJ=5 C TJ=75 C TJ=5 C TJ=-5 C TJ=0 C Output Current, lout(a) Output Current, lout(a) 6

7 Typical Operating Characteristics Reference Voltage vs. Junction Temperature POK Delay Time vs. Junction Temperature Referemce Voltage, VREF (mv) POK Delay Time (ms) =5V =3.3V Junction Temperature ( C) Junction Temperature ( C) PSRR PSRR Ripple Rejection (db) = 4.5V~5.5V =.5V =.V IOUT = 3A CIN = 00µF COUT = 330uF(ESR=30mΩ) Amplitude (db) = 5V =.5V(lower bound) PK-PK = 00mV CIN = 47µF COUT = 330uF(30mΩ) IOUT = 3A =.V Frequency (Hz) Frequency (Hz) 7

8 Operating Waveforms R4 R8 8.k Shutdown C8 470pF Q3 7 6 OCSET FB VCC 5 GND 3 UGATE U APW7057 BOOT PHASE LGATE C uf 8 4 D N448 C6 0.uF R7 k. C3 uf Q APM04N L 3.3uH Q APM04N C7 0.uF R5.75k R6 0 L uh C4 470uFx C5 000uFx Enable C9 47uF +.5V EN C uf 5 CIN 00uF V POK +5V 3 U 4 APL593 EN FB GND 7 R k R3 k k C 33nF POK +.V/3A COUT 0uF. Load Transient Response :. Using an Output Capacitor with ESR 8mΩ - COUT = 0µF/6.3V (ESR = 30mΩ), CIN = 00µF/6.3V - IOUT = 0mA to 3A to 0mA, Rise time = Fall time = µs IOUT = 0mA -> 3A IOUT = 0mA -> 3A ->0mA IOUT = 3A -> 0mA =kω, R=kΩ, C=33nF IOUT IOUT IOUT Ch :, 50mV/Div Ch : IOUT, A/Div Ch :, 50mV/Div Ch : IOUT, A/Div Ch :, 50mV/Div Ch : IOUT, A/Div Time : µs/div Time : 0µS/Div Time : µs/div 8

9 Operating Waveforms (Cont.). Using an MLCC as the Output Capacitor - COUT = µf/6.3v (ESR = 3mΩ), CIN = µf/6.3v - IOUT = 0mA to 3A to 0mA, Rise time = Fall time = µs IOUT = 0mA -> 3A IOUT = 0mA -> 3A ->0mA IOUT = 3A -> 0mA =39kΩ, R=78kΩ C=56pF IOUT IOUT IOUT Ch :, 00mV/Div Ch : IOUT, A/Div Ch :, 00mV/Div Ch : IOUT, A/Div Ch :, 00mV/Div Ch : IOUT, A/Div Time : µs/div Time : 0µS/Div Time : µs/div. Power ON / Power OFF : - =.5V, = 5V, =.V - COUT = 0µF/6.3V (ESR = 30mΩ), CIN = 00µF/6.3V, RL=Ω Power ON Power OFF Ch Ch Ch Ch Ch3 VPOK Ch3 VPOK Ch4 Ch4 Ch :,V/div Ch :,V/div Ch3 : VPOK,V/div Ch4 :,V/div Time : 0ms/div Ch :,V/div Ch :,V/div Ch3 : VPOK,V/div Ch4 :,V/div Time : 0ms/div 9

10 Operating Waveforms (Cont.) 3. Shutdown and Enable : - =.5V, = 5V, =.V - COUT = 0µF/6.3V (ESR = 30mΩ), CIN = 00µF/6.3V, RL=Ω Shutdown Enable Ch VEN Ch VEN Ch Ch Ch3 IOUT Ch3 IOUT Ch4 VPOK Ch4 VPOK Ch : VEN,5V/div Ch :,V/div Ch3 : IOUT,A/div Ch4 : VPOK,V/div Time : ms/div Ch : VEN,5V/div Ch :,V/div Ch3 : IOUT,A/div Ch4 : VPOK,V/div Time : ms/div 4. POK Delay : - =.5V, = 5V, =.V - COUT = 0µF/6.3V (ESR = 30mΩ), CIN = 00µF/6.3V, RL=Ω Ch POK Delay Ch Ch3 VPOK Ch :,V/div Ch :,V/div Ch3 : VPOK,V/div Time : ms/div 0

11 Functional Pin Description GND (Pin ) Ground pin of the circuitry. All voltage levels are measured with respect to this pin. FB (Pin ) Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by: where is connected from to FB with Kelvin sensing and R is connected from FB to GND. A bypass capacitor may be connected with in parallel to improve load transient response. The recommended R and are in the range of 00~0kΩ. (Pin 3,4) = R Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improving transient responses. (Pin 5) and Exposed Pad Main supply input pins for power conversions. The Exposed Pad provide a very low impedance input path (V) for the main supply voltage. Please tie the Exposed Pad and Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power- On Reset purpose. (Pin 6) Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. POK (Pin 7) Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. EN (Pin 8) Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When re-enabled, the IC undergoes a new soft-start cycle. Left this pin open, an internal current source 0mA pulls this pin up to voltage, enabling the regulator. Functional Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both input voltages at and pins to prevent wrong logic controls. The POR function initiates a soft-start process after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output voltage when the voltage falls below it s falling POR threshold. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge at start-up. The typical soft-start interval is about ms. Output Voltage Regulation An error amplifier working with a temperaturecompensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier designed with high bandwidth and DC gain

12 Functional Description (Cont.) Output Voltage Regulation (Cont.) provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from to. Current-Limit The APL593 monitors the current via the output NMOS and limits the maximum current to prevent load and APL593 from damages during overload or shortcircuit conditions. Under-Voltage Protection (UVP) The APL593 monitors the voltage on FB pin after soft-start process is finished. Therefore the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL593 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL593. When the junction temperature exceeds +50 C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature cools by 50 C, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown designed with a 50 o C hysteresis lowers the average junction temperature during continuous thermal overload conditions, extending life time of the device. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +5 C. Enable Control The APL593 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new softstart cycle. Left open, this pin is pulled up by an internal current source (0µA typical) to enable operation. It s not necessary to use an external transistor to save cost. Power-OK and Delay The APL593 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a delay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time. Application Information Power Sequencing The power sequencing of and is not necessary to be concerned. But do not apply a voltage to for a long time when the main voltage applied at is not present. The reason is the internal parasitic diode from to conducts and dissipates power without protections due to the forward-voltage. Output Capacitor The APL593 requires a proper output capacitor to maintain stability and improve transient response over temperature and current. The output capacitor selection is to select proper ESR(equivalent series resistance) and capacitance of the output capacitor for good stability and load transient response.

13 Application Information (Cont.) Output Capacitor (Cont.) The APL593 is designed with a programmable feedback compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors), low-esr bulk capacitors (such as solid Tantalum, POSCap, and Aluminum electrolytic capacitors) all can be used as an output capacitor. The value of the output capacitors can be increased without limit. During load transients, the output capacitors, depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL593 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-esr bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL593 requires proper input capacitors to supply current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the pin limit the slew rate of the surge currents. More parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors, such as ceramic chip capacitors, are very good for the input capacitors An aluminum electrolytic capacitor (>00mF, ESR <300mW) is recommended as the input capacitor. It is not necessary to use low-esr capacitors. More capacitance reduce the variations of the input voltage of pin. Feedback Network Figure shows the feedback network between, GND and FB pins. It works with the internal error amplifier to provide proper frequency response for the linear regulator. The ESR is the equivalent series resistance of the output capacitor. The C OUT is ideal capacitance in the output capacitor. The V OUT is the setting of the output voltage. APL593 VERR EAMP VREF FB VFB R Figure C ESR C OUT The feedback network selection depends on the values of the ESR and C OUT, which has been classified into three conditions: Condition : Large ESR ( 8mΩ ) - Select the in the range of 400Ω ~.4kΩ - Calculate the R as the following : R (kω) = (kω) 0.8(V) Calculate the C as the following : V 0 OUT(V) (kω) Condition : Middle ESR V C OUT(V) (nf) (V) V 40 OUT(V)... () (kω)... () - Calculate the as the following: 57 = ESR(m (k Ω) 37.5 (V) + Ω) 5... (3) 3

14 Application Information (Cont.) Feedback Network (Cont.) Select a proper (selected) to be a little larger than the calculated. - Calculate the C as the following : C (pf) = OUT(uF) [ 0.7 ESR(mΩ) + 0]... (4) Where =(selected) Select a proper C(selected) to be a little smaller than the calculated C. - The C calculated from equation (4) must meet the following equation: C (pf) ESR (mω ) Where =(calculated) from equation (3) If the C(calculated) can not meet the equation (5), please use the Condition 3. - Use equation () to calculate the R. Condition 3 : Low ESR (eg. Ceramic Capacitors) - Calculate the as the following: Select a proper (selected) to be a little larger than the calculated. The minimum selected is equal to kw when the calculated is smaller than k or negative. - Calculate the C as the following : Where =(selected) Select a proper C(selected) to be a little smaller than the calculated C. - The C calculated from equation (7) must meet the following equation : C (kω) 37.5 V + (k OUT(V).. (5).5 (V) C (pf) ESR (m ) COUT(uF) + Ω.. (8) (kω ) Where =(calculated) from equation (6) Ω) (kω) = (. ESR(mΩ) + 300) COUT(uF) 37.5 V C (pf) = (0.4 ESR (mω) + 34.) C OUT(uF) OUT(V) 37.5 V + (k Ω)..(6) OUT(V)..(7) If the C(calculated) can not meet the equation (8), please use the Condition. - Use equation () to calculate the R. The reason to have three conditions described above is to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition, regardless of equation (5), is enough for all kinds of output capacitor. PCB Layout Considerations (See Figure ). Please solder the Exposed Pad and together on the PCB. The main current flow is through the exposed pad. Refer Figure 3 to make a proximate topology.. Please place the input capacitors for and pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible. 4. To place APL593 and output capacitors near the load is good for performance. 5. The negative pins of the input and output capacitors and the GND pin of the APL593 are connected to the ground plane of the load. 6. Please connect PIN 3 and 4 together by a wide track. 7. Large current paths must have wide tracks. 8. See the Typical Application (see next page Figure ) - Connect the one pin of the R to the GND of APL593 - Connect the one pin of to the Pin 3 of APL593 - Connect the one pin of C to the Pin 3 of APL593 4

15 Application Information (Cont.) PCB Layout Considerations (Cont.) C CNTL CIN APL593 FB GND C C OUT Load R Figure Thermal Considerations See Figure 3. The SOP-8-P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top plane. The copper of the plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance ( CA). 0 mil 8 8 mil 3 SOP-8-P Top plane Die Exposed Pad Top plane Ambient Air Figure 43 PCB 5

16 Packaging Information SOP-8-P pin ( Reference JEDEC Registration MS-0) E E H 0.05X45 D e e D A A 0.004max. L Dim Millimeters Inches Min. Max. Min. Max. A A D D 3.00REF 0.8REF E E.60REF 0.0REF H L e e.7bsc 0.50BSC φ 8 8 6

17 Physical Specifications Terminal Material Solder-Plated Copper (Solder Material : 90/0 or 63/37 SnPb), 00%Sn Lead Solderability Meets EIA Specification RSI86-9, ANSI/J-STD-00 Category 3. Reflow Condition (IR/Convection or VPR Reflow) T P Ramp-up tp Critical Zone T L to T P T L Temperature Tsmax Tsmin t L Ramp-down ts Preheat 5 t 5 C to Peak Classificatin Reflow Profiles Time Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (T L to T P ) 3 C/second max. 3 C/second max. Preheat 00 C 50 C - Temperature Min (Tsmin) - Temperature Max (Tsmax) 50 C 00 C seconds seconds Time (min to max) (ts) Time maintained above: - Temperature (T L ) - Time (t L ) 83 C seconds 7 C seconds Peak/Classificatioon Temperature (Tp) See table See table Time within 5 C of actual Peak Temperature (tp) 0-30 seconds 0-40 seconds Ramp-down Rate 6 C/second max. 6 C/second max. Time 5 C to Peak Temperature 6 minutes max. 8 minutes max. Notes: All temperatures refer to topside of the package.measured on the body surface. (mm) 7

18 Classification Reflow Profiles(Cont.) Table. SnPb Entectic Process Package Peak Reflow Temperatures Package Thickness Volume mm 3 Volume mm <350 <.5 mm 40 +0/-5 C 5 +0/-5 C.5 mm 5 +0/-5 C 5 +0/-5 C Table. Pb-free Process Package Classification Reflow Temperatures Package Thickness Volume mm 3 <350 Volume mm Volume mm 3 >000 <.6 mm C* C* C*.6 mm.5 mm C* C* C*.5 mm C* C* C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 C. For example 60 C+0 C) at the rated MSL level. Reliability Test Program Test item Method Description SOLDERABILITY MIL-STD-883D C, 5 SEC HOLT MIL-STD-883D Hrs C PCT JESD--B,A0 68 Hrs, 00%RH, C TST MIL-STD-883D C~50 C, 00 Cycles ESD MIL-STD-883D VHBM > KV, VMM > 00V Latch-Up JESD 78 0ms, tr > 00mA Carrier Tape & Reel Dimensions t E Po P P D W F Bo Ao D Ko 8

19 Carrier Tape & Reel Dimensions(Cont.) T J A C B T Application A B C J T T W P E 330 ± ± ± 0. ± 0. ± ± 0..75±0. SOP- 8/-P F D D Po P Ao Bo Ko t 5.5± ± 0..0 ± ± 0. 5.± 0..± ±0.03 (mm) Cover Tape Dimensions Application Carrier Width Cover Tape Width Devices Per Reel SOP- 8/-P Customer Service Anpec Electronics Corp. Head Office : 5F, No. Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : Fax : Taipei Branch : 7F, No. 37, Lane 35, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : Fax :