LTC6957-1/LTC6957-2/ LTC6957-3/LTC Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter APPLICATIONS TYPICAL APPLICATION

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1 FEATURES Low Phase Noise Buffer/Driver Optimized Conversion of Sine Wave Signas to Logic Leves Three Logic Output Types Avaiabe LVPECL LVDS CMOS Additive Jitter 45fs RMS (LTC6957-1) Frequency Range Up to 300MHz 3.15V to 3.45V Suppy Operation Low Skew 3ps Typica Fuy Specified from 40 C to 125 C 12-Lead MSOP and 3mm 3mm DFN Packages APPLICATIONS System Reference Frequency Distribution High Speed ADC, DAC, DDS Cock Driver Miitary and Secure Radio Low Noise Timing Trigger Broadband Wireess Transceiver High Speed Data Acquisition Medica Imaging Test and Measurement LTC6957-1/LTC6957-2/ Low Phase Noise, Dua Output Buffer/Driver/ Logic Converter DESCRIPTION The LTC /LTC6957-2/ is a famiy of very ow phase noise, dua output AC signa buffer/driver/ogic eve transators. The input signa can be a sine wave or any ogic eve ( 2V P-P ). There are four members of the famiy that differ in their output ogic signa type as foows: LTC6957-1: LVPECL Logic Outputs LTC6957-2: LVDS Logic Outputs LTC6957-3: CMOS Logic, In-Phase Outputs LTC6957-4: CMOS Logic, Compementary Outputs The LTC6957 wi buffer and distribute any ogic signa with minima additive noise, however, the part reay exces at transating sine wave signas to ogic eves. The eary ampifier stages have seectabe owpass fitering to minimize the noise whie sti ampifying the signa to increase its sew rate. This input stage fitering/noise imiting is especiay hepfu in deivering the owest possibe phase noise signa with sow sewing input signas such as a typica 10MHz sine wave system reference. A registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents and TYPICAL APPLICATION FILTA 3.3V 0.1µF V + SD1 Additive Phase Noise at MHz SINGLE-ENDED SINE WAVE INPUT AT +7dBm (500mV RMS ) FILTA = FILTB = GND OCXO MHz +7dBm SINE WAVE 50Ω 10nF 10nF FILTB IN + IN OUT1 OUT2 TO PLL CHIPS OR SYSTEM SAMPLING CLOCKS PHASE NOISE () LTC (CMOS) LTC (LVDS) LTC (CMOS) GND SD TA01a LTC (LVPECL) 1k 10k k 1M TA01b For more information 1

2 ABSOLUTE MAXIMUM RATINGS Suppy Votage (V + or V DD ) to GND...3.6V Input Current (IN +, IN, FILTA, FILTB, SD1, SD2) (Note 2)... ±10mA LTC Output Current... 1mA, 30mA LTC Output Current... ±10mA LTC6957-3, LTC Output Current (Note 3)... ±30mA (Note 1) Specified Temperature Range LTC6957I C to 85 C LTC6957H C to 125 C Junction Temperature C Storage Temperature Range C to 150 C Lead Temperature (for MSOP Sodering, 10sec) C PIN CONFIGURATION LTC6957-1, LTC LTC6957-3, LTC TOP VIEW FILTA 1 12 SD1 V + IN OUT1 + OUT1 IN GND FILTB GND OUT2 OUT2 + SD2 DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN T JMAX = 150 C, θ JA = 58 C/W, θ JC = 10 C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB FILTA V + IN + IN TOP VIEW SD1 V DD OUT1 4 GND 9 OUT2 GND 5 8 GNDOUT FILTB 6 7 SD2 DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN T JMAX = 150 C, θ JA = 58 C/W, θ JC = 10 C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB LTC6957-1, LTC LTC6957-3, LTC TOP VIEW TOP VIEW FILTA V + IN + IN GND FILTB SD1 OUT1 + OUT1 OUT2 OUT2 + SD2 FILTA V + IN + IN GND FILTB SD1 V DD OUT1 OUT2 GNDOUT SD2 MS PACKAGE 12-LEAD PLASTIC MSOP T JMAX = 150 C, θ JA = 145 C/W MS PACKAGE 12-LEAD PLASTIC MSOP T JMAX = 150 C, θ JA = 145 C/W 2 For more information

3 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6957IDD-1#PBF LTC6957IDD-1#TRPBF LFQJ 12-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LTC6957IDD-2#PBF LTC6957IDD-2#TRPBF LFQK 12-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LTC6957IDD-3#PBF LTC6957IDD-3#TRPBF LFQM 12-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LTC6957IDD-4#PBF LTC6957IDD-4#TRPBF LFQN 12-Lead (3mm 3mm) Pastic DFN 40 C to 85 C LTC6957IMS-1#PBF LTC6957IMS-1#TRPBF Lead Pastic MSOP 40 C to 85 C LTC6957HMS-1#PBF LTC6957HMS-1#TRPBF Lead Pastic MSOP 40 C to 125 C LTC6957IMS-2#PBF LTC6957IMS-2#TRPBF Lead Pastic MSOP 40 C to 85 C LTC6957HMS-2#PBF LTC6957HMS-2#TRPBF Lead Pastic MSOP 40 C to 125 C LTC6957IMS-3#PBF LTC6957IMS-3#TRPBF Lead Pastic MSOP 40 C to 85 C LTC6957HMS-3#PBF LTC6957HMS-3#TRPBF Lead Pastic MSOP 40 C to 125 C LTC6957IMS-4#PBF LTC6957IMS-4#TRPBF Lead Pastic MSOP 40 C to 85 C LTC6957HMS-4#PBF LTC6957HMS-4#TRPBF Lead Pastic MSOP 40 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: Some packages are avaiabe in 500 unit rees through designated saes chaes with #TRMPBF suffix. For more information 3

4 ELECTRICAL CHARACTERISTICS LTC The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V + = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, R LOAD = 50Ω coected to 1.3V, uness otherwise specified. A votages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Inputs (IN, IN + ) f IN Input Frequency Range 300 MHz V INSE Input Signa Leve Range, Singe-Ended V P-P V INDIFF Input Signa Leve Range, Differentia V P-P t MIN Minimum Input Puse Width High or Low 0.5 ns V INCM Sef-Bias Votage, IN +, IN V R IN Input Resistance, Differentia kω C IN Input Capacitance, Differentia 0.5 pf BW IN Input Section Sma Signa Bandwidth ( 3dB) FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H Outputs (LVPECL) V OH Output High Votage LTC6957I LTC6957H V OL Output Low Votage LTC6957I LTC6957H V V V V V V V V V V V V V OD Output Differentia Votage ±660 ±810 ±965 mv t r Output Rise Time 180 ps t f Output Fa Time 160 ps t PD Propagation Deay FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H t PD / T Propagation Deay Variation Over Temperature FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H MHz MHz MHz MHz V V V V ns ns ns ns ps/ C ps/ C ps/ C ps/ C t PD / V Propagation Deay Variation vs Suppy Votage FILTB = L, FILTA = L 4 50 ps/v t SKEW Output Skew, Differentia, CH1 to CH ps t MATCH Output Matching (OUTx + to OUTx ) See Timing Diagram ps Power V + V + Operating Suppy Votage Range R LOAD = 50Ω to (V + 2V) V I S Suppy Current Both Outputs Enabed (SD1 = SD2 = L) One Output Enabed (SD1 = L, SD2 = H or SD1 = H, SD2 = L) Both Outputs Disabed (SD1 = SD2 = H) Incuding Output Loads No Output Loads No Output Loads No Output Loads R LOAD = 50Ω to (V + 2V), ma ma ma ma t ENABLE Output Enabe Time, Other SDx = L 40 µs t WAKEUP Output Enabe Time, Other SDx = H 120 µs t DISABLE Output Disabe Time, Other SDx = L 20 µs t SLEEP Output Disabe Time, Other SDx = H 20 µs 4 For more information

5 ELECTRICAL CHARACTERISTICS LTC6957-1/LTC6957-2/ LTC The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V + = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, R LOAD = 50Ω coected to 1.3V, uness otherwise specified. A votages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digita Logic Inputs V IH High Leve SD or FILT Input Votage V V V IL Low Leve SD or FILT Input Votage 0.4 V I IN_DIG Input Current SD or FILT Pins 0.1 ±10 µa Additive Phase Noise and Jitter f IN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L) at 10Hz Offset at Hz Offset at 1kHz Offset at 10kHz Offset at khz Offset >1MHz Offset Jitter (10Hz to 150MHz) Jitter (12kHz to 20MHz) f IN = MHz Sine Wave, 0dBm (FILTA = H, FILTB = L) at 10Hz Offset at Hz Offset at 1kHz Offset at 10kHz Offset at khz Offset >1MHz Offset Jitter (10Hz to 61.44MHz) Jitter (12kHz to 20MHz) f IN = MHz Sine Wave, 10dBm (FILTA = L, FILTB = L) at 10Hz Offset at Hz Offset at 1kHz Offset at 10kHz Offset at khz Offset >1MHz Offset Jitter (10Hz to 50MHz) Jitter (12kHz to 20MHz) fs RMS fs RMS fs RMS fs RMS fs RMS fs RMS For more information 5

6 ELECTRICAL CHARACTERISTICS LTC The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V + = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, R LOAD = 110Ω differentia, uness otherwise specified. A votages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Inputs (IN, IN + ) f IN Input Frequency Range 300 MHz V INSE Input Signa Leve Range, Singe-Ended V P-P V INDIFF Input Signa Leve Range, Differentia V P-P t MIN Minimum Input Puse Width High or Low 0.5 ns V INCM Sef-Bias Votage, IN +, IN V R IN Input Resistance, Differentia kω C IN Input Capacitance, Differentia 0.5 pf BW IN Input Section Sma Signa Bandwidth FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H Outputs (LVDS) V OD Output Differentia Votage mv V OD Deta V OD mv V OS Output Offset Votage V V OS Deta V OS mv I SC Short-Circuit Current ma t r Output Rise Time 170 ps t f Output Fa Time 170 ps t PD Propagation Deay FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H t PD / T Propagation Deay Variation Over Temperature FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H MHz MHz MHz MHz ns ns ns ns ps/ C ps/ C ps/ C ps/ C t PD / V Propagation Deay Variation vs Suppy Votage FILTB = L, FILTA = L 5 60 ps/v t SKEW Output Skew, Differentia, CH1 to CH ps Power V + V + Operating Suppy Votage Range V I S Suppy Current Both Outputs Enabed (SD1 = SD2 = L) One Output Enabed (SD1 = L, SD2 = H or SD1 = H, SD2 = L) Both Outputs Disabed (SD1 = SD2 = H) ma ma ma t ENABLE Output Enabe Time, Other SDx = L 300 ns t WAKEUP Output Enabe Time, Other SDx = H 400 ns t DISABLE Output Disabe Time, Other SDx = L 40 ns t SLEEP Output Disabe Time, Other SDx = H 50 ns 6 For more information

7 ELECTRICAL CHARACTERISTICS LTC6957-1/LTC6957-2/ LTC The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V + = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, R LOAD = 110Ω differentia, uness otherwise specified. A votages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digita Logic Inputs V IH High Leve SD or FILT Input Votage V V V IL Low Leve SD or FILT Input Votage 0.4 V I IN_DIG Input Current SD or FILT Pins 0.1 ±10 µa Additive Phase Noise and Jitter f IN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L) 10Hz Offset Hz Offset 1kHz Offset 10kHz Offset khz Offset >1MHz Offset Jitter (10Hz to 150MHz) Jitter (12kHz to 20MHz) f IN = MHz Sine Wave, 0dBm (FILTA = H, FILTB = L) 10Hz Offset Hz Offset 1kHz Offset 10kHz Offset khz Offset >1MHz Offset Jitter (10Hz to 61.44MHz) Jitter (12kHz to 20MHz) f IN = MHz Sine Wave, 10dBm (FILTA = L, FILTB = L) 10Hz Offset Hz Offset 1kHz Offset 10kHz Offset khz Offset >1MHz Offset Jitter (10Hz to 50MHz) Jitter (12kHz to 20MHz) fs RMS fs RMS fs RMS fs RMS fs RMS fs RMS For more information 7

8 ELECTRICAL CHARACTERISTICS LTC6957-3/ LTC The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V + = V DD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, R LOAD = 480Ω to V DD /2, uness otherwise specified. A votages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Inputs (IN, IN + ) f IN Input Frequency Range 300 MHz V INSE Input Signa Leve Range, Singe-Ended V P-P V INDIFF Input Signa Leve Range, Differentia V P-P t MIN Minimum Input Puse Width High or Low 0.6 ns V INCM Sef-Bias Votage, IN +, IN V R IN Input Resistance, Differentia kω C IN Input Capacitance, Differentia 0.5 pf BW IN Input Section Sma Signa Bandwidth FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H Outputs (CMOS) V OH Output High Votage No Load 3mA Load V OL Output Low Votage No Load 3mA Load V DD 0.1 V DD 0.2 t r Output Rise Time 320 ps t f Output Fa Time 300 ps t PD Propagation Deay FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H t PD / T Propagation Deay Variation Over Temperature FILTB = L, FILTA = L FILTB = L, FILTA = H FILTB = H, FILTA = L FILTB = H, FILTA = H MHz MHz MHz MHz V V V V ns ns ns ns ps/ C ps/ C ps/ C ps/ C t PD / V Propagation Deay Variation vs Suppy Votage FILTB = FILTA = L, V + = V DD 200 ps/v t SKEW Output Skew, CH1 to CH2 LTC LTC ps ps Power V + V + Operating Suppy Votage Range V V DD V DD Operating Suppy Votage Range V DD Must Be V V I S Suppy Current, Pin 2 Both Outputs Enabed (SD1 = SD2 = L) One Output Enabed (SD1 = L, SD2 = H or SD1 = H, SD2 = L) Both Outputs Disabed (SD1 = SD2 = H) I DD Suppy Current, Pin 11, No Load Static Dynamic, per Output ma ma ma ma ma/mhz t ENABLE Output Enabe Time, Other SDx = L 200 ns t WAKEUP Output Enabe Time, Other SDx = H 300 ns t DISABLE Output Disabe Time, Other SDx = L 20 ns t SLEEP Output Disabe Time, Other SDx = H 20 ns 8 For more information

9 ELECTRICAL CHARACTERISTICS LTC6957-1/LTC6957-2/ LTC6957-3/ LTC The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V + = V DD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, R LOAD = 480Ω to V DD /2, uness otherwise specified. A votages are with respect to ground. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digita Logic Inputs V IH High Leve SD or Fit Input Votage V V V IL Low Leve SD or Fit Input Votage 0.4 V I IN_DIG Input Current SD or Fit Pins 0.1 ±10 µa Additive Phase Noise and Jitter f IN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L) 10Hz Offset Hz Offset 1kHz Offset 10kHz Offset khz Offset >1MHz Offset Jitter (10Hz to 150MHz) Jitter (12kHz to 20MHz) f IN = MHz Sine Wave, 0dBm (FILTA = H, FILTB = L) 10Hz Offset Hz Offset 1kHz Offset 10kHz Offset khz Offset >1MHz Offset Jitter (10Hz to 61.44MHz) Jitter (12kHz to 20MHz) f IN = MHz Sine Wave, 10dBm (FILTA = L, FILTB = L) 10Hz Offset Hz Offset 1kHz Offset 10kHz Offset khz Offset >1MHz Offset Jitter (10Hz to 50MHz) Jitter (12kHz to 20MHz) fs RMS fs RMS fs RMS fs RMS fs RMS fs RMS Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: Input pins IN +, IN, FILTA, FILTB, SD1 and SD2 are protected by steering diodes to either suppy. If the inputs go beyond either suppy rai, the input current shoud be imited to ess than 10mA. If pushing current into FILTB, the Pin 6 votage must be imited to 4V. On the ogic pins (FILTA, FILTB, SD1 and SD2) the Absoute Maximum input current appies ony at the maximum operating suppy votage of 3.45V; 10mA of input current with the absoute maximum suppy votage of 3.6V may create permanent damage from votage stress. Note 3: With 3.6V Absoute Maximum suppy votage, the LTC6957-3/ LTC CMOS outputs can sink 30mA whie ow, and source 30mA whie high without damage. However, if overdriven or subject to an inductive oad kick outside the suppy rais, 30mA can create damaging votage stress and is not guaranteed uness V DD is imited to 3.15V. For more information 9

10 TYPICAL PERFORMANCE CHARACTERISTICS LTC INPUT VOLTAGE (V) Input Sef Bias Votage vs Temperature V + = 3.45V V + = 3.3V V + = 3.15V SUPPLY CURRENT (ma) Suppy Current vs Suppy Votage NO OUTPUT LOADS T A = 25 C T A = 125 C T A = 55 C SUPPLY CURRENT (ma) Suppy Current vs Temperature NO OUTPUT LOADS V + = 3.3V V + = 3.45V V + = 3.15V TEMPERATURE ( C) SUPPLY VOLTAGE (V) TEMPERATURE ( C) G G G03 OUTPUT VOLTAGE (V) Output Votage vs Load Current V OH V OL LOAD CURRENT (ma) 0 OUTPUT VOLTAGE (V) Output Votage vs Temperature V + = 3.3V 50Ω LOADS TO 1.3V V OH V OL TEMPERATURE ( C) SUPPLY CURRENT (ma) Suppy Current vs Temperature V + = 3.45V V + = 3.3V V + = 3.15V 50Ω Y LOAD TO GROUND ON BOTH CHANNELS TEMPERATURE ( C) G G G06 2.5V 2.0V 1.5V 2.5V 2.0V 1.5V 3.0V 0V Enabe and Wakeup WAKE-UP: OUTPUTS WITH OTHER CHANNEL OFF ENABLE: OUTPUTS WITH OTHER CHANNEL ON SD G07 20ns/DIV MULTIPLE EXPOSURES, PERSISTENCE MODE CLOCK I/O = 120MHz SD DRIVE ~ 140kHz, ASYNCHRONOUS NUMBER OF UNITS Typica Distribution of Skew OUT1+ TO OUT2+ RISING EDGE TYPICAL OF ALL OUTPUT EDGES/PAIRS 2 LOTS, 400 UNITS EACH, 3 TEMPERATURES = 125 C = 25 C = 55 C t SKEW (ps) PRODUCTION DATA, 1ps RESOLUTION, ~1-2ps UNCERTAINTY G08 10 DIFFERENTIAL OUTPUT (V P-P ) Differentia Output vs Frequency C C C 0.2 0dBm INPUT FREQUENCY (MHz) G09 10 For more information

11 TYPICAL PERFORMANCE CHARACTERISTICS LTC6957-1/LTC6957-2/ LTC PHASE NOISE () Additive Phase Noise vs Input Frequency SINGLE-ENDED SINE WAVE INPUT AT 7dBm (500mV RMS ) 300MHz 153.6MHz PHASE NOISE () Additive Phase Noise vs Ampitude SINGLE-ENDED MHz SINE WAVE INPUT SEE APPLICATIONS INFORMATION 10dBm, FILTA = L, FILTB = H 0dBm, FILTA = H, FILTB = L PHASE NOISE () Additive Phase Noise vs Temperature SINGLE-ENDED SINE WAVE INPUT, MHz at 7dBm (500mV RMS ) 25 C 125 C MHz 1k 10k k 1M +10dBm, 1k 10k k 1M 55 C 1k 10k k 1M G G G12 PHASE NOISE () Additive Phase Noise vs Suppy Votage Additive Phase Noise at MHz AM to PM Conversion SINGLE-ENDED SINE WAVE INPUT, MHz at 7dBm (500mV RMS ) 3.45V 3.15V 3.3V 1k 10k k 1M PHASE NOISE () SINGLE-ENDED SINE WAVE INPUT 0dBm, FILTA = H, FILTB = L 7dBm, 1k 10k k 1M NORMALIZED PHASE (DEG) 5 4 f IN = 300MHz V + = 3.3V C C 3 25 C 4 EACH CURVE NORMALIZED TO 0 AT 0dBm INPUT AMPLITUDE (dbm) G G G t PD vs Temperature FILTA = FILTB = H t PD vs Temperature V + = 3.0V, 50Ω LOADS TO 1.3V V + = 3.6V, 50Ω LOADS TO 1.9V t PD vs Suppy Votage and Termination Votage t PD (ns) FILTA = L, FILTB = H FILTA = H, FILTB = L t PD (ns) V + = 3.3V, 50Ω LOADS TO 1.3V t PD (ns) Ω LOADS TO V + 2V 50Ω LOADS TO FIXED 1.3V TEMPERATURE ( C) TEMPERATURE ( C) SUPPLY VOLTAGE (V) G G G18 For more information 11

12 TYPICAL PERFORMANCE CHARACTERISTICS LTC INPUT VOLTAGE (V) Input Sef Bias Votage vs Temperature V + = 3.45V V + = 3.3V V + = 3.15V SUPPLY CURRENT (ma) Suppy Current vs Suppy Votage T A = 125 C 25 T 20 A = 25 C 15 T A = 55 C 10 5 SUPPLY CURRENT (ma) Suppy Current vs Temperature V + = 3.45V 40.0 V + = 3.3V V + = 3.15V TEMPERATURE ( C) SUPPLY VOLTAGE (V) TEMPERATURE ( C) G G G21 OUTPUT VOLTAGE (V) Output Votages vs Load Resistor DC DATA, IN + > (IN + 50mV) OUT OUT 1.0 V + = 3.6V V + = 3.3V V + = 3V LOAD RESISTOR (Ω) USE OF R LOAD > 150Ω NOT RECOMMENDED f IN MAY BE COMPROMISED 2.0V 1.5V 1.0V 2.0V 1.5V 1.0V 3.0V 0V Enabe and Wakeup WAKE-UP: OUTPUTS WITH OTHER CHANNEL OFF SD ENABLE: OUTPUTS WITH OTHER CHANNEL ON G G25 20ns/DIV MULTIPLE EXPOSURES, PERSISTENCE MODE CLOCK I/O = 120MHz SD DRIVE ~ 140kHz, ASYNCHRONOUS 250 V OH, V OL AND V OS (V) SHORT-CIRCUIT CURRENT (ma) Output Votages vs Temperature V OH (MEASURED) V OS (CALCULATED) V OD (CALCULATED) V OL (MEASURED) TEMPERATURE ( C) Output Short-Circuit Current vs Temperature V + = 3.3V V + = 3.15V V + = 3.45V G ANY ONE (1) OUTPUT SHORTED TO GROUND TEMPERATURE ( C) V OD (mv) OUTPUT VOLTAGE (V) DIFFERENTIAL OUTPUT (mv P-P ) Output Votages vs Loading OUT + OUT 125 C 25 C 55 C LOAD STRESS PER TIA/EIA-644-A FIGURE V TEST LOAD VOLTAGE (V) G24 Differentia Output vs Frequency 10dBm INPUT R LOAD = Ω 25 C 125 C FREQUENCY (MHz) 55 C G G27 12 For more information

13 TYPICAL PERFORMANCE CHARACTERISTICS LTC6957-1/LTC6957-2/ LTC PHASE NOISE () Additive Phase Noise vs Input Frequency SINGLE-ENDED SINE WAVE INPUT AT 7dBm (500mV RMS ) 153.6MHz MHz 300MHz 1k 10k k G28 1M PHASE NOISE () Additive Phase Noise vs Ampitude SINGLE-ENDED MHz SINE WAVE INPUT SEE APPLICATIONS INFORMATION 10dBm, FILTA = L, FILTB = H 0dBm, FILTA = H, FILTB = L 10dBm, 1k 10k k G29 1M PHASE NOISE () Additive Phase Noise vs Temperature SINGLE-ENDED SINE WAVE INPUT, MHz AT 7dBm (500mV RMS ) 25 C 1k 10k k 125 C 55 C G30 1M PHASE NOISE () Additive Phase Noise vs Suppy Votage Additive Phase Noise at MHz AM to PM Conversion SINGLE-ENDED SINE WAVE INPUT, MHz AT 7dBm (500mV RMS ) 3.45V 3.3V 3.15V 1k 10k k 1M PHASE NOISE () SINGLE-ENDED SINE WAVE INPUT 0dBm, FILTA = H, FILTB = L 7dBm, 1k 10k k 1M NORMALIZED PHASE (DEG) 5 4 f IN = 300MHz V + = 3.3V C 1 25 C C 4 EACH CURVE NORMALIZED TO 0 AT 0dBm INPUT AMPLITUDE (dbm) G G G33 t PD (ns) t PD vs Temperature t PD vs Temperature t PD vs Suppy Votage FILTA = FILTB = H FILTA = L, FILTB = H FILTA = H, FILTB = L Ω LOAD TEMPERATURE ( C) t PD (ns) V + = 3.6V V + = 3.0V V + = 3.3V Ω LOAD TEMPERATURE ( C) t PD (ns) C 25 C 55 C Ω LOAD SUPPLY VOLTAGE (V) G G G36 For more information 13

14 TYPICAL PERFORMANCE CHARACTERISTICS 2.20 Input Sef Bias Votage vs Temperature V + = 3.45V 25 Suppy Current vs Suppy Votage 21.5 Suppy Current vs Temperature INPUT VOLTAGE (V) V + = 3.3V V + = 3.15V V + SUPPLY CURRENT (ma) C 125 C 55 C V + SUPPLY CURRENT (ma) V + = 3.45V V + = 3.3V V + = 3.15V TEMPERATURE ( C) V + VOLTAGE (V) TEMPERATURE ( C) G G G39 OUTPUT VOLTAGE (V) V DD V DD 0.25 V DD 0.5 V DD Output Votages vs Load Current V DD = 3.6V V DD = 3.3V V DD = 3V V DD = 2.7V V DD = 2.4V OUTPUT HIGH, SOURCING CURRENT OUTPUT LOW, SINKING CURRENT LOAD CURRENT (ma) 20 OUTPUT VOLTAGE (V) V DD V DD 0.25 V DD 0.5 V DD Output Votages vs Load Current 0 0 OUTPUT HIGH, SOURCING CURRENT V DD = 3.3V OUTPUT LOW, SINKING CURRENT 55 C 25 C 125 C 125 C 55 C LOAD CURRENT (ma) 25 C 20 PHASE NOISE () Additive Phase Noise vs Suppy Votage SINGLE-ENDED SINE WAVE INPUT, MHz at 7dBm (500mV RMS ) V + = 3.3V, V DD AS SHOWN 3.0V 3.3V 2.4V 2.7V 1k 10k k 1M G G G42 5 Suppy Current vs Suppy Votage 21 Suppy Current vs Temperature V + = V DD = 3.3V 3.0 Output Votage Swing vs Frequency V DD CURRENT (ma) C 55 C 125 C V DD VOLTAGE (V) 3.6 V DD SUPPLY CURRENT (ma) DYNAMIC, ONE (1) OUTPUT ACTIVE AT 312.5MHz, 13pF LOAD, LEFT AXIS OTHER OUTPUT DISABLED 0.1 STATIC, NO DC LOAD, RIGHT (LOGARITHMIC) AXIS TEMPERATURE ( C) 10 1 V DD SUPPLY CURRENT (µa) OUTPUT SWING (V P-P ) 55 C 125 C C CAUTION: AT VERY HIGH FREQUENCIES, THE CMOS OUTPUTS MAY NOT TOGGLE 2.0 AT ALL DEPENDING ON INPUT FREQ- UENCY, AMPLITUDE, SUPPLY VOLTAGE, OR TEMPERATURE dBm INPUT IN DC1766A R LOAD = 133Ω AC-COUPLED FREQUENCY (MHz) G G G45 14 For more information

15 TYPICAL PERFORMANCE CHARACTERISTICS LTC6957-1/LTC6957-2/ PHASE NOISE () Additive Phase Noise vs Input Frequency MHz SINGLE-ENDED SINE WAVE INPUT AT 7dBm (500mV RMS ) 300MHz 153.6MHz 1k 10k k G46 1M PHASE NOISE () Additive Phase Noise vs Ampitude SINGLE-ENDED MHz SINE WAVE INPUT SEE APPLICATIONS INFORMATION 10dBm, FILTA = L, FILTB = H 10dBm, 0dBm, FILTA = H, FILTB = L 1k 10k k G47 1M PHASE NOISE () Additive Phase Noise vs Temperature SINGLE-ENDED SINE WAVE INPUT, MHz AT 7dBm (500mV RMS ) 25 C 1k 10k k 125 C 55 C G48 1M PHASE NOISE () Additive Phase Noise vs Suppy Votage Additive Phase Noise at MHz AM to PM Conversion SINGLE-ENDED SINE WAVE INPUT, MHz AT 7dBm (500mV RMS ) V + = V DD 3.3V 3.15V 3.45V 1k 10k k 1M PHASE NOISE () SINGLE-ENDED SINE WAVE INPUT 0dBm, FILTA = H, FILTB = L 7dBm, 1k 10k k 1M NORMALIZED PHASE (DEG) EACH CURVE NORMALIZED TO 0 AT 0dBm f IN = 300MHz V + = V DD = 3.3V 125 C 55 C 25 C INPUT AMPLITUDE (dbm) G G G t PD vs Temperature t PD vs Temperature t PD vs Suppy Votage t PD (ns) FILTA = FILTB = H FILTA = L, FILTB = H FILTA = H, FILTB = L FALLING EDGE TEMPERATURE ( C) t PD (ns) RISING EDGE FALLING EDGE TEMPERATURE ( C) t PD (ns) V + = 3.45V V + = V DD 0.96 RISING EDGE V DD SUPPLY VOLTAGE (V) G G G54 For more information 15

16 PIN FUNCTIONS FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting Contro. These CMOS ogic inputs contro the bandwidth of the eary ampifier stages. For sow sewing signas substantiay ower phase noise is achieved by using this feature. See the Appications Information section for more detais. V + (Pin 2): Suppy Votage (3.15V to 3.45V). This suppy must be kept free from noise and rippe. It shoud be bypassed directy to GND (Pin 5) with a 0.1µF capacitor. IN +, IN (Pin 3, Pin 4): Input Signa Pins. These inputs are differentia, but can aso interface with singe-ended signas. The input can be a sine wave signa or a CML, LVPECL, TTL or CMOS ogic signa. See the Appications Information section for more detais. GND (Pin 5): Ground. Coect to a ow inductance ground pane for best performance. The coection to the bypass capacitor for V + (Pin 2) shoud be through a direct, ow inductance path. SD1, SD2 (Pin 12, Pin 7): Output Enabe Contro. These CMOS ogic inputs contro the enabing and disabing of their respective OUT1 and OUT2 outputs. When both outputs are disabed, the LTC6957 is paced in a ow power shutdown state. LTC Ony OUT1, OUT1 + (Pin 10, Pin 11): LVPECL Outputs. Differentia ogic outputs typicay terminated by 50Ω coected to a suppy 2V beow the V + suppy. Refer to the Appications Information section for more detais. OUT2, OUT2 + (Pin 9, Pin 8): LVPECL Outputs. Differentia ogic outputs typicay terminated by 50Ω coected to a suppy 2V beow the V + suppy. Refer to the Appications Information section for more detais. LTC Ony OUT1, OUT1 + (Pin 10, Pin 11): LVDS Outputs, Mosty TIA/EIA-644-A Compiant. Refer to the Appications Information section for more detais. OUT2, OUT2 + (Pin 9, Pin 8): LVDS Outputs, Mosty TIA/EIA-644-A Compiant. Refer to the Appications Information section for more detais. Ony OUT1, OUT2 (Pin 10, Pin 9): CMOS Outputs. Refer to the Appications Information section for more detais. V DD (Pin 11): Output Suppy Votage (2.4V to 3.45V). For best performance coect this to the same suppy as V + (Pin 2). If the output needs to be a ower ogic rai, this suppy can be separatey coected, but this votage must be ess than or equa to that on Pin 2 for proper operation. This suppy must aso be kept free from noise and rippe. It shoud be bypassed directy to the GNDOUT pin (Pin 8) with a 0.1µF capacitor. GNDOUT (Pin 8): Output Logic Ground. Tie to a ow inductance ground pane for best performance. The coection to the bypass capacitor for V DD (Pin 11) shoud be through a direct, ow inductance path. LTC6957-xDD Ony Exposed Pad (Pin 13): Aways tie the underying DFN exposed pad to GND (Pin 5). To achieve the rated θ JA of the DD package, there shoud be good therma contact to the PCB. 16 For more information

17 BLOCK DIAGRAMS LTC6957-1/LTC6957-2/ 2 FILTA V + 12 SD1 1 6 FILTB OUT OUT1 IN IN OUT2 OUT GND 7 SD2 LTC and LTC FILTA FILTB IN + IN 2 V + 12 SD1 V DD OUT GND 5 7 SD2 OUT2 GNDOUT BD LTC and LTC For more information 17

18 TIMING DIAGRAM SD1 SD2 INPUT OUT1 + /OUT1 OUT1 * * * OUT2 + /OUT2 OUT2 * t DISABLE t SLEEP t WAKEUP t ENABLE INPUT DETAIL * SEE APPLICATIONS INFORMATION FOR LOGIC BEHAVIOR DURING SHUTDOWN SPECIFIC TO LVPECL/LVDS/CMOS OUTPUTS. LTC SHOWN HERE FOR REFERENCE. EACH OUTPUT TYPE BEHAVES DIFFERENTLY DURING SHUTDOWN. t PD OUT1 + /OUT1 OUT1 50% 50% t MATCH OUT2 + /OUT2 OUT2 90% 10% 90% 10% t RISE t FALL t SKEW 6957 TD1 18 For more information

19 APPLICATIONS INFORMATION Genera Considerations The LTC6957-1/LTC6957-2/ are ow noise, dua output cock buffers that are designed for demanding, ow phase noise appications. Propery appied, they can preserve phase noise performance in situations where aternative soutions woud degrade the phase noise significanty. They are aso usefu as ogic converters. However, no buffer device is capabe of removing or reducing phase noise present on an input signa. As with most ow phase noise circuits, improper appication of the LTC6957-1/LTC6957-2/ can resut in an increase in the phase noise through a variety of mechanisms. The information beow wi, hopefuy, aow a designer to avoid such an outcome. The LTC6957 is designed to be used with high performance cock signas destined for driving the encode inputs of ADCs or mixer inputs. Such cocks shoud not be treated as digita signas. The beauty of digita ogic is that there is noise margin both in the votage and the timing, before any deeterious effects are noticed. In contrast, high performance cock signas have no margin for error LTC6957-1/LTC6957-2/ in the timing before the system performance is degraded. Users are encouraged to keep this distinction in mind whie designing the entire cocking signa chain before, during, and after the LTC6957. Input Interfacing The input stage is the same for a versions of the LTC6957 and is designed for ow noise and ease of interfacing to sine-wave and sma ampitude signas. Other ogic types can interface directy, or with itte effort since they present a smaer chaenge for noise preservation. Figure 1 shows a simpified schematic of the LTC6957 input stage. The diodes are a for protection, both during ESD events and to protect the ow noise NPN devices from being damaged by input overdrive. The resistors are to bias the input stage at an optima DC eve, but they are too arge to eave foating without increasing the noise. Therefore, for ow noise use, aways coect both inputs to a ow AC impedance. A capacitor to ground/return is imperative on the unused input in singeended appications. 2 V + 1 FILTA 6 FILTB FILTERS 3 IN + 1.2k 1.8k 4 IN 1.2k 3.2k 2mA GND F01 Figure 1 For more information 19

20 APPLICATIONS INFORMATION Figure 2a shows how to interface singe-ended LVPECL ogic to the LTC6957, whie Figure 2b shows how to drive the LTC6957 with differentia LVPECL signas. The capacitors shown are 10nF and can be inexpensive ceramics, preferaby in sma SMT cases. For use above MHz, ower vaue capacitors may be desired to avoid series resonance, which coud increase the noise in Figure 2a even though the capacitor is just on the DC input. This comment appies to a capacitors hooked to the inputs throughout this data sheet. In Figure 2a, the R TERM impementation is up to the user and is to terminate the transmission ine. If it is coected to a V TT that is passivey generated and heaviy bypassed to ground, the 10nF to ground shown on the inverting LTC6957 input is the appropriate coection to use. However, if the termination goes to an activey generated V TT votage, ower noise may be achieved by coecting the capacitor on the inverting input to that V TT rather than ground. In Figure 2b, both inputs to the LTC6957 are driven, increasing the differentia input signa size and minimizing noise from any common mode source such as V TT, both of which improve the achievabe phase noise. A variety of termination techniques can be used, and as ong as the two sides use the same termination, the configuration used won't matter much. In Figure 2b, the R TERM s are shown in a "Y" configuration that creates a passive V TT at the common point. Most 3.3V LVPECL devices have differentia outputs and can be terminated with three 50Ω resistors as shown. Figure 3 shows a 50Ω RF signa source interface to the LTC6957. For a pure tone (sine wave) input, Figure 3 can hande up to 10dBm maximum. A broadband 50Ω match as shown shoud suffice for most appications, though for sma ampitude input signas a narrow band reactive matching network may offer incrementa improvements in performance. 3.3V 50Ω 10nF + + R TERM LTC6957 SOURCE 50Ω 10nF LTC F03 10nF 6957 F02a Figure 3. Singe-Ended 50Ω Input Source Figure 2a. Singe-Ended LVPECL Input 3.3V + LTC F02b 3 R TERM Figure 2b. Differentia LVPECL Input Figure 2 20 For more information

21 APPLICATIONS INFORMATION Figure 4 shows the interface between current mode ogic (CML) signas and the LTC6957 inputs. The specifics of terminating wi be dependent on the particuar CML driver used; Figure 4 shows terminations ony at the oad end of the ine, but the same LTC6957 interface is appropriate for appications with the source end of the ine aso terminated. In Figure 4a, a differentia signa interface to the LTC6957 is shown, which must be AC-couped due to the DC input eves required at the LTC6957. Figure 4b shows a singe-ended CML signa driving the LTC6957. This is not commony used because of noise and immunity weaknesses compared to the differentia CML case. Because the signa is created by a current pued through the termination resistor, the signa is inherenty referenced to the suppy votage to which R TERM is tied. For that reason, the other LTC6957 shoud be AC-referenced to that suppy votage as shown. The poarity change shown here is for graphic carity ony, and can be reversed by swapping the LTC6957 input terminas. R TERM R TERM 10nF + 10nF LTC F04a Figure 4a. Differentia CML Input 10nF + R TERM 10nF LTC F04b Figure 4b. Singe-Ended CML Input Figure 4 For more information 21

22 APPLICATIONS INFORMATION Figure 5 shows the LTC6957 being driven by an LVDS (EIA-644-A) signa pair. This is simpy a matter of differentiay terminating the pair and AC-couping as shown into the LTC6957 whose DC common mode votage is incompatibe with the LVDS standard. 110Ω 10nF 10nF Figure 5. LVDS Input + LTC F05 The choice of 110Ω versus Ω termination is arbitrary (the EIA-644-A standard aows 90Ω to 132Ω) and shoud be made to match the differentia impedance of the trace pair. The termination and AC-couping eements shoud be ocated as cose as possibe to the LTC6957. If DC-couping is desired, for exampe to contro the LTC6957 output phasing during times the LVDS input cocks wi be hated, a pair of 3k resistors can parae the two capacitors in Figure 5. An EIA/TIA-644-A compiant driver can drive this oad, which is ess oad stress than specification The differentia votage into the LTC6957 when cocked (>khz) wi be fu LVDS eves. When the cocks stop, the DC differentia votage created by the resistors and the 1.2k interna resistors (Figure 1) wi be mv, sti sufficient to assure the desired LTC6957 output poarity. Choosing the smaest capacitors needed for phase noise performance wi minimize the setting transients when the cocks restart. Interfacing with CMOS Logic The ogic famiies discussed and iustrated to this point are generay a better choice for routing and distributing ow phase-noise reference/cock signas than is CMOS ogic. A of the ogic types shown so far are we suited for use with ow impedance terminations. Most of the time there is a differentia signa when using LVPECL or CML, and LVDS aways has a differentia signa. Differentia signas provide ots of margin for error when it comes to picking up noise and interference that can corrupt a reference cock. CMOS on the other hand caot drive 50Ω oads, is usuay routed singe-ended, and by its nature is couped to the potentiay noisy suppy votage haf the time. The provide CMOS outputs, so it may seem surprising to read herein that CMOS is a poor choice for ow phase noise appications. However, these devices shoud prove usefu for designers that recognize the chaenges and imitations of using CMOS signas for ow phase noise appications. See the CMOS Outputs of the section for further information. The best method for driving the LTC6957 with CMOS signas woud be to provide differentia drive, but if that is not avaiabe, there are few ways to create a differentia CMOS signa without ruing the risk of corrupting the skew or creating other probems. Therefore, singe-ended CMOS signas are the norm and care must be taken when using this to drive the LTC6957. The primary concern is that a routing shoud be terminated to minimize refections. With CMOS ogic there is usuay penty of signa (more than the LTC6957 can hande without attenuation) and the ampitude of the LTC6957 input signa wi generay be of secondary importance compared to avoiding the deeterious effects of signa refections. The primary concern about terminations is that the input waveform presented to the LTC6957 shoud have fu speed sewing at the a important transitions. If a rising edge is sowed by the destructive addition of the ringing/setting of a prior edge refection, or even the start of the current edge, the phase noise performance wi suffer. This is true for a ogic types, but is particuary probematic when using CMOS because of the fast sew rates and because it does not naturay end itsef to cean terminations. Point-to-point routing is best, and care shoud be taken to avoid daisy-chain routing, because the terminated end may be the ony point aong the ine that sees cean transitions. Earier oads may even see a dwe in the transition region which wi greaty degrade phase noise performance. 22 For more information

23 APPLICATIONS INFORMATION Figure 6 shows a suggested CMOS to LTC6957 interface. The transmission ine shown is the PCB trace and the component vaues are for a characteristic impedance of 50Ω, though they coud be scaed up or down for other vaues of Z0. The R1/R2 divider at the CMOS output cuts the Thevenin votage in haf when the Z OUT of the driver is incuded. More importanty, it drives the transmission ine with a Thevenin driving resistance of 50Ω, matching the Z0 of the ine. On the other end of the ine, a 50Ω oad is presented, minimizing refections. This resuts in a second 2:1 attenuation in votage, so the LTC6957 input wi be approximatey 800mV P-P with 3V CMOS; 1.25V P-P with 5V and 600mV P-P with 2.5V. A of these eves are ess than the maximum input swing of 2V P-P yet with cean edges and fast sew rates shoud be abe to reaize the fu phase noise performance of the LTC6957. CMOS R OUT 25Ω R1 75Ω R2 Ω Z0 = 50Ω Figure 6. CMOS Input 6957 F06 + LTC6957 The various capacitors are for AC-couping and shoud have Z << 50Ω at the operating frequency. The capacitors aow the LTC6957 to set its own DC input bias eve, and reduce the DC current drain, which at 12.4mA (for the case of a driver powered from 3.3V) is significant. This current drain can be reduced (with some potentia for a noise penaty) by increasing the attenuation at the R1/ R2 network, taking care to keep the Thevenin impedance equa to the Z0 of the trace. When using CMOS ogic, it is important to consider how a of the output drivers, in the same IC, are being used. For best performance, the entire IC shoud be devoted to driving the LTC6957, or if other gates in the same package must be put to use, they shoud ony carry the same timing signa (such as for fan-out) or be mutipexed in time so that ony one timing signa is being processed at a time, such as for mutipexing seective shutdowns of different segments of a system. Otherwise performance is ikey to suffer with spurs or other interference in the 50Ω For more information LTC6957-1/LTC6957-2/ phase noise spectrum reated to the other signas processed in the driver. Input Resistors The LTC6957 input resistors, seen in Figure 1, are present at a times, incuding during shutdown. Athough they constitute a arge portion of the shutdown current, this behavior prevents the shutdown and wake-up cycing of the LTC6957 from kicking back into prior stages, which coud create arge transients that coud take a whie to sette. Particuary in the common case of AC-couping where the couping cap charge is preserved. Input Fitering The LTC6957 incudes input fitering with three narrowband settings in addition to the fu bandwidth imitation of the circuit design. Tabe 1 FILTA FILTB BANDWIDTH Low Low 1200MHz (Fu Bandwidth) High Low 500MHz ( 3dB) Low High 160MHz ( 3dB) High High 50MHz ( 3dB) For sow sewing signas (i.e., <MHz sine wave signas) substantiay ower phase noise can be achieved by using this feature. Bandwidth imiting is usefu because it imits the impact of a of the spectra energy that wi aias down to (on top of) the fundamenta frequency. The best fiter setting to use for a given appication wi depend on the cock frequency, ampitude, and waveform shape, with the singe biggest determinant being the sew rate at the input of the LTC6957. Any ampifier noise wi add phase noise inversey proportiona to its input sew rate, just from the dv/dt changing votage noise to time base noise. But a fast sew rate may not be possibe with other design constraints, such as the use of sine waves for EMI/RFI reasons, signa osses, etc. A imiting ampifier such as the LTC6957 shoud have enough bandwidth to preserve the sew rate of the input. But any additiona bandwidth wi provide no improvement in phase noise due to sew rate preservation, whie incurring a phase noise penaty from noise aiasing. 23

24 APPLICATIONS INFORMATION Tabe 2 has the sew rate ranges most suitabe for the four different fiter settings. Tabe 2 FILTA FILTB INPUT SLEW RATE (V/µs) Low Low >400 High Low 125 to 400 Low High 40 to 125 High High <40 Another way to ook at this is to consider the case of sine waves, for which the frequency ranges wi depend on input ampitudes, as iustrated in Tabe 3. Tabe 3 INPUT AMPLITUDE (dbm) FILTA = L, FILTB = L (MHz) FREQUENCY RANGE FILTA = H, FILTB = L (MHz) FILTA = L, FILTB = H (MHz) FILTA = H, FILTB = H (MHz) 10 >63 20 to to 20 <6.3 5 > to to 35 <11 0 > to to 63 <20 5 > to 112 <35 10 > to 200 <63 Figure 7 has LTC MHz additive phase noise measurements that iustrate the trade-offs between fiter settings at various input sew rates. Each of the three charts has a four fiter settings, and one input ampitude; Figure 7a has a +10dBm input, Figure 7b has a 0dBm input, and Figure 7c has a 10dBm input. The four fiter settings are shown in the same coors throughout. With +10dBm at MHz, the input sew rate is 628V/µs and Tabe 2 indicates the best fiter setting to use is FILTA = FILTB = L, which is seen to be the case in Figure 7a. The noise at the next fiter setting is ony sighty higher, but for the maximum fitering case there is a fu 10dB of additiona noise. With 0dBm at MHz, the input sew rate is 198V/µs and Tabe 2 indicates the best fiter setting to use is FILTA = H, FILTB = L. Again this is seen to be the case in Figure 7b. As the input was decreased 10dB from Figure 7a to Figure 7b, the bue trace rose 5dB whie the green trace ony rose 3dB. With 10dBm at MHz, the input sew rate is 63V/µs and Tabe 2 indicates the best fiter setting to use is FILTA = L, FILTB = H. Again this is seen to be the case in Figure 7c. As the input was decreased 10dB from Figure 7a to Figure 7b, and again to Figure 7c, the red trace rose just 3dB then another 4dB, whie the green and bue traces rose much faster. PHASE NOISE () SINGLE-ENDED SINE WAVE INPUT, MHz AT 10dBm (2V P-P ) LTC FILTA = FILTB = H FILTA = L, FILTB = H FILTA = H, FILTB = L 1k 10k k 1M PHASE NOISE () SINGLE-ENDED SINE WAVE INPUT, MHz AT 0dBm (632.5mV P-P ) LTC FILTA = FILTB = H FILTA = L, FILTB = H FILTA = H, FILTB = L 1k 10k k 1M PHASE NOISE () FILTA = FILTB = H FILTA = H, FILTB = L FILTA = L, FILTB = H SINGLE-ENDED SINE WAVE INPUT, MHz AT 10dBm (200mV P-P ) LTC k 10k k 1M F07a F07b (a) (b) (c) F07c Figure 7. MHz Additive Phase Noise with Varying Input Ampitudes 24 For more information

25 APPLICATIONS INFORMATION One important observation to take away from Figures 7a to 7c is that whie the worst fiter settings for a given set of conditions shoud certainy be avoided, it doesn't matter neary as much if the optima or next to optima fiter setting is used, because they are aways fairy comparabe in terms of phase noise. So if a design wi have an octave or two range of ampitudes or frequencies, it is sufficient to choose the fiter setting whose range most cosey matches the appication's range when using Tabes 2 or 3 and the noise penaty wi not be severe anywhere in the range. Evidenty, the input fitering wi not significanty hep with arge and fast sewing input signas to the LTC6957. As seen in Figure 1, the input has a differentia pair before the fiters, so the imiting wi aready have happened before the fiter. Fortunatey, with arge input signas, performance is typicay better than with smaer input signas because phase noise is a signa-to-noise phenomenon. Input Drive and Output Skew A versions of the LTC6957 have very good output skew; the specification imits consist amost entirey of test margins. Even aboratory verification of the skew between different outputs is a chaenging exercise, given the need to measure within ±1ps. With eectromagnetic propagation veocity in FR-4 being we known as 6" per nanosecond, the skew of the LTC6957 wi be impacted by PCB trace routing ength differences of just 6mis. The LTC6957 t PD and t SKEW are specified for a mv step with 50mV of overdrive. This is common for high speed comparators, though it may not refect the typica appication usage of parts such as the LTC6957. The propagation deay of the LTC6957 wi increase with ess overdrive and decrease with more overdrive, as woud that of a high speed comparator. To a esser extent, having the same overdrive but a arger signa (for instance a differentia input step of 200mV to 50mV) wi increase propagation deay, though this effect is smaer and can usuay be ignored. A consequence of this behavior may be a perceived mismatch between the propagation deay for rising versus faing edges when driven with an AC-couped input whose duty cyce is not exacty 50%. The LTC6957 inputs are internay DC-couped, and as shown in Figure 1, biasing is provided at ~64% of the suppy votage. AC-couped input signas with a duty cyce of exacty 50% wi see symmetric eves of overdrive for the two signa directions. If, for exampe, the input signa is a mv P-P square wave with a duty-cyce of 48%, meaning it is high 48% of the time and ow 52% of the time, the DC average wi be 48mV above the ow votage eve. This means the rising edge has 52mV of overdrive, and the faing edge has 48mV of overdrive. As a resut of this, the rising edge t PD wi be faster than the faing edge t PD. Fortunatey, this wi make the output duty cyce coser to 50% than the input duty cyce. Figure 8 is from measurements on the LTC6957-2, with a 2V to 2.1V square wave on IN, and with IN + set to various DC votages between those two eves. The X-axis is the overdrive eve for the t PD + data, and is mv minus the overdrive eve for the t PD data, to iustrate the eve of t PD changes that can unexpectedy occur with AC-couping. The ines are dashed where the measurement uncertainty becomes arge, when singe digit miivots and picoseconds are being measured 1. As can be seen, the t PD +/t PD mismatch is very good at 50mV where the two overdrive eves are the same. t PD (ps) t PD + t PD IN + OFFSETTED ±50mV DC IN DRIVEN mv P-P OVERDRIVE (mv) 6957 F08 Figure 8. LTC Propagation Deay vs Overdrive 1 Beow 2mV to 3mV, the input offset and the sma input hysteresis pay a roe too. Fortunatey, neither is arge enough to be a concern in norma operation. For more information 25

26 APPLICATIONS INFORMATION This data is shown for the LTC6957-2, but the effect is due to the input stage that is common to a versions, so any other version wi have the same genera behavior. The LTC and LTC CMOS outputs may have additiona t PD + vs t PD discrepancies due to differences between the NMOS and PMOS output devices, particuary when driving heavy oads. These are independent of input overdrive, but can change with suppy votage and temperature, and can vary part to part. The compementary outputs of the LTC wi therefore be higher skew than the ike edges of the LTC Both the LTC and LTC wi have arge (120ps typ) t + PD to t PD discrepancies compared to LVPECL or LVDS outputs. LVPECL Outputs of the LTC Figure 9 shows a simpified schematic of the LTC LVPECL output stage. As with most ECL outputs, there are no interna pu-down devices so the user must provide both termination and biasing externa to the device. Note that ony the current source is cut off during shutdown. The bases of the output NPNs are sti tied to the pu-up resistors, so both outputs wi be pued high in shutdown, and it is the user s responsibiity to discoect the externa oading if power reduction is to be reaized. The simpest way to terminate and bias the LTC outputs is to route the differentia output to the differentia receiver and terminate the ines at that point with the three resistor network shown in Figure 9. The differentia termination wi be Ω, whie the common mode termination wi be 75Ω which coud resut in additiona common mode susceptibiity. A bypass capacitor on the midpoint of the Y can be used to improve this. If the common mode termination impedance is not an issue, the three resistor Y configuration can be changed to a three resistor deta configuration, which is a simper ayout in most cases. During transitions to and from shutdown, the LTC outputs are not guaranteed to compy with the specified output eves for any ength of time after the rising edge of SD1/SD2, nor for any time before sufficient t WAKEUP / t ENABLE subsequent to the faing edge of SD1/SD2. The output common mode and differentia votage coud have a sow setting time compared to the signa frequency, and a ong string of runt puses coud be seen. The LTC shutdown capabiity shoud be used as a sow on/off contro, not a ogic gating/enabe contro. V + V + 24Ω V + 5Ω V + 24Ω 5Ω V + PCB ROUTING TRACES Z0 = 50Ω 50Ω 50Ω 50Ω F09 LTC Figure 9. LTC LVPECL Outputs For more information

27 APPLICATIONS INFORMATION Power Suppies for LVPECL Operation The LTC can operate from 3.15V to 3.45V tota suppy votage difference, irrespective of the absoute eve of those votages. The convention in LVPECL is that the negative suppy is ground, whie in ECL the positive suppy may be ground or 2.0V. The LTC can work in a of these situations provided the tota suppy votage difference is within the 3.15V to 3.45V range. No specia suppy sequencing wi be needed. With a 2V rai the output terminations go to ground, whie, with the positive suppy grounded, the outputs can toerate short circuits to ground. However, the four CMOS ogic input signas wi need to be driven with respect to whatever absoute eves of suppy votages are used. If FILTA, FILTB, SD1, and SD2 are fixed, they can be tied to the appropriate rai and this is not a probem. Interface ogic eves coud get tricky if they need to be programmed in-system. In any votage configuration, be aware that the LVPECL output stage depends on the externa oad to compete its biasing and, as such, is susceptibe to phase moduation as the suppy votage changes. The LTC is generay ess sensitive to variations in the suppy votage if the termination votage tracks the suppy rather than ground. LTC6957-1/LTC6957-2/ With a four outputs terminated or otherwise driving heavy oads, the LTC power consumption and temperature rise may be an issue. Fortunatey, the data sheet specification for suppy current with output oads does not need to be mutipied by the entire suppy votage to cacuate on-chip power dissipation because most of that current fows through the oads which wi dissipate a significant portion of the tota system power. Typicay, the interna power consumption wi be (20mA 3.3V = ) 66mW, whie the on-chip power dissipation from the output oading wi be ess than haf that number. With a tota power dissipation on-chip of 90mW, the temperature rise in the MS-12 package wi be 13 C given the θ JA of that package. For use to 125 C ambient (H-grade) designers shoud be sure to check the temperature rise using their specific output oading and suppy eves. The Absoute Maximum rating for Junction Temperature is 150 C, and must be avoided to prevent damaging the device, and as stated in Note 1: "Exposure to any Absoute Maximum Rating condition for extended periods of time may affect device reiabiity and ifetime." For more information 27

28 APPLICATIONS INFORMATION LVDS Outputs of the LTC Figure 10 shows a simpified schematic of the LTC LVDS output stage. The TIA/EIA-644-A standard specifies the generator eectrica requirements for this type of interface, and the LTC has been verified against that standard using the foowing test methods: SPECIFICATION LEVEL OF TESTING % Production Tested % Production Tested % Production Tested % Production Tested* Lab Verification of Design Ony 6a % Production Tested 6b % Production Tested 6c % Production Tested *The t RISE /t FALL of the LTC are not compiant with the standard so as to preserve fu phase noise performance. To sow the edge rates, add differentia capacitance across the outputs. 2.7pF is sufficient to meet the standard. The TIA/EIA-644-A standard does not cover driver characteristics during shutdown nor the transitions to and from shutdown. The LTC outputs are not guaranteed to compy with the standard for any ength of time after the rising edge of SD1/SD2, nor for any time before sufficient t WAKEUP /t ENABLE subsequent to the faing edge of SD1/ SD2. The output common mode votage (V OS in 644-A parance) coud have a sow setting time compared to the signa frequency, and a ong string of runt puses coud be seen. The LTC shutdown capabiity shoud be used as a sow, power-saving on/off contro, not a ogic gating/enabe contro. Power Suppies for LVDS Operation The LTC has a singe suppy that shoud be within the 3.15V to 3.45V range. The LTC power suppy votage can corrupt the spectra purity of the cock signa, though to a esser degree than with any of the other options. See the Typica Performance Characteristic chart t PD vs Suppy Votage. When using both LVDS chaes, the LTC power consumption can exceed 120mW, which resuts in a junction-to-ambient rise of 17.4 C in the MS-12 package, more when operated at 3.45V. Again, it is up to the user to aways avoid junction temperatures above the Absoute Maximum rating, and to stay comfortaby beow it for any extended periods of time. LTC mA V + 650Ω 650Ω V + PCB ROUTING TRACES Z0 = 50Ω TO 60Ω 110Ω F V Figure 10. LTC LVDS Outputs 28 For more information

29 APPLICATIONS INFORMATION CMOS Outputs of the Figure 11 shows a simpified schematic of the LTC6957-3/ LTC CMOS output stage. The LTC outputs are driven synchronousy in-phase, whie the LTC outputs are driven differentiay out-of-phase. Athough the are specified for a resistive oad, the outputs can drive capacitive oads as we. With more than a few picofarads of oad, the rise and fa times wi be degraded in direct proportion to the oad capacitance. During shutdown, the LTC outputs wi both be set to a ogic ow. During shutdown, the LTC OUT1 wi be set to a ogic ow, whie OUT2 wi be set to a ogic high. During transitions to and from shutdown, the LTC6967-3/ LTC outputs may not compy with the specified output eves for any ength of time after the rising edge of SD1/SD2, nor for any time before sufficient t WAKEUP / t ENABLE subsequent to the faing edge of SD1/SD2. The 6957 F11 V DD GND OUT Figure 11. CMOS Outputs OUT1 OUT2 For more information LTC6957-1/LTC6957-2/ outputs may have one or two errant transitions resuting in runt puses being seen. The shutdown capabiity shoud be used as a sow, powersaving on/off contro, not a ogic gating/enabe contro, and because they can not be put in a high impedance (3-state) condition, the shutdown functionaity is not usabe as a way to mutipex mutipe outputs or devices. Power Suppies for CMOS Operation The operate with V + from 3.15V to 3.45V ony. If the are used to drive CMOS ogic at a ower votage rai, the output stage can be powered (Pin 11) by a ower votage, down to 2.4V MIN. Note that significant degradation of the spectra purity coud occur if the output suppy, V DD, is not cean, either because of additiona broadband noise or discrete spectra tones. The nature of a CMOS ogic gate forms an AM moduator of ow frequency disturbances on the power/ ground that moduate the signa propagating through the CMOS gate. Numerous common phenomena can serve to convert the AM to PM/FM and, even if the conversion efficiency is ow, corrupt the phase noise to unacceptabe eves in demanding appications. If two separate suppies are used, the ony suppy sequencing issue to be aware of is that if the V DD comes up first, the OUT1/OUT2 CMOS outputs wi be high impedance unti V + > ~1V. Note that the four CMOS contro inputs are a referenced to V +, not the output suppy. Aso note that during operation the output suppy shoud be equa to or ess than V +. The wi function with V DD severa hundred miivots above the V + suppy, but depending on the oad, this margin for error can argey be consumed by transient oad steps. When driving capacitive oads at high frequencies, the V DD power consumption can jump consideraby over the quiescent power taken from V +. The Dynamic current specification is with no oad and adds directy to the current needed to repetitivey charge and discharge a capacitive oad. With 24mA drawn from V + at 3.3V, and another 20mA to 30mA drawn from V DD (easy to do with two outputs active at 300MHz), the tota power consumption can be 145mW to 178mW, resuting in a junction-to-ambient rise 29

30 APPLICATIONS INFORMATION of 21 C to 26 C in the MS-12 package. For use to 125 C ambient (H-grade) designers shoud be sure to check the temperature rise using their specific output frequency, oading, and suppy votages. The Absoute Maximum rating for Junction Temperature is 150 C, which must be avoided to prevent damaging the device, and as stated in Note 1: "Exposure to any Absoute Maximum Rating condition for extended periods of time may affect device reiabiity and ifetime." Low Phase Noise Design Considerations Phase noise is a frequency domain representation of the random variation in phase of a periodic signa. It is characterized as the power at a given offset frequency reative to the power of the fundamenta frequency. Phase noise is specified in, decibes reative to the carrier in a 1Hz bandwidth. It is essentiay a frequency dependent signa-to-noise ratio. Designing for ow phase noise is chaenging, even with a soid understanding of phase noise. Any designer attempting such a task wi find a good working understanding of what phase noise is, and how it behaves, to be the most important too to achieve success. One of the most intuitive expanations is found in Chapter 3, The Reationship Between Phase Jitter and Noise Density, of W.P. Robins 1982 text, Phase Noise in Signa Sources. With a soid base of understanding, the designer wi now see that the entire cocking chain is fu of potentia phase moduators. The noise of an ampifier is usuay thought of as an additive term, but for phase noise the bias noise, to the extent that the ampifier bandwidth is dependent on the bias eve, is not an additive term but a moduating term. The LTC6957 is a monoithic cock imiting ampifier carefuy designed so that users do not have to worry about such detais. However, users of the LTC6957 sti need to pay attention to externa considerations that can resut in corruption of the good phase noise performance avaiabe from a the components used. Timing jitter is a term used to describe the integration of phase noise over a specified bandwidth which is presented as a time domain specification. Unfortunatey, the term ow jitter has become so overused that it is rendered virtuay meaningess. High speed communication inks doing de-seriaization and the ike can require jitter on the order of 30ps to 50ps. This is ower jitter than required for a cock on a micro-controer, but for high frequency samping, even 1ps can severey impact the dynamic range achievabe. Therefore, it is best to ignore the term ow jitter and ook for measured vaues of jitter, and preferaby phase noise. To anayze and measure true ow noise components, most instruments measure phase noise (in ) rather than jitter. A second consideration when designing for ow phase noise is that any cock signa is an anaog signa and shoud be thought of and routed as such. They shoud not be run through arge FPGAs with ots of activities at mutipe frequencies, they shoud not be routed through PCB traces aongside digita data ines, and they shoud not be routed through cock fan-out devices that have features such as zero deay or programmabe skew. The specifics of the PCB traces and what surrounds them shoud be anayzed as if the cock signas were among your most sensitive anaog signas, because in demanding appications that is what your cock signas are. Note that signa integrity software intended for anayzing crosstak in digita systems may ony give yes or no answers and that cocking performance can be compromised at eves 40dB to 60dB beow what is required to get that yes answer. Common pitfas with cock signas are the same as for sensitive anaog signas: routing near or aongside digita traces of any kind, crossing digita traces on an adjacent ayer within a sandwich of ground panes, using digita power panes as part of ayer sandwiches, and assuming a of these are sufficienty mitigated by using differentia cock signaing. The way to address these issues is aso the same as for sensitive anaog signas: routing away from digita traces wherever possibe; routing with shieding of ground, either panes, adjacent traces, or both; making reaistic assumptions of common mode rejections (30dB to 40dB at most); and keeping a critica eye out for unintended coupers during the design and debug phases. 30 For more information

31 APPLICATIONS INFORMATION Even if the word s ceanest reference cock were used to feed the LTC6957, simpy routing it through a poory designed system woud resut in compromised spectra performance. This often catches designers by surprise because the mechanisms above are typicay additive and inear, which resut in fitering and additiona spectra components, but don t by themseves create phase moduation. Unfortunatey, any imiter, incuding the LTC6957, wi, through its noninear action, transform additive terms into phase moduation. When a sma tone is added to a arge pure tone, the arger tone wi appear to have its ampitude and phase moduated at a rate equa to the difference of the two frequencies. Pass this through a imiter and ony the phase moduation remains. In arge compex systems, it may be impractica to eiminate a potentia corrupting of the cock signas. In such a case, a narrow band fiter paced at the inputs of the LTC6957 can remove the unwanted spectra components that are far enough away from the fundamenta. Cose-in spectra anomaies wi ikey be impervious to such fitering. Therefore, it is douby important to keep an eye out for moduating mechanisms. If the cock is routed through CMOS ogic gates, the power suppy used for that gate wi AM moduate the signa at the very east. The moduation coud manifest itsef as sideband tones if the power suppy has repetitive disturbances, common with switching power suppies, or it coud manifest itsef as random noise if the noise of a inear reguator is too high. Another source of corruption in arge systems or aboratory measurements is the use of fexibe cabing, which can have a ow eve piezoeectric effect that moduates the eectrica ength in response to mechanica vibration. Rigid or semi-rigid cabing and PCB routing can be used to eiminate this source of signa corruption. LTC6957-1/LTC6957-2/ AM to PM Conversion at the LTC6957 Inputs The LTC6957 input stage has some AM to PM conversion, but as seen in the Typica Performance Characteristics section, even at 300MHz this is ess than 0.5 /db. One source of AM to PM conversion at the LTC6957 input is the optiona owpass fitering, because the upper sideband and the ower sideband wi be attenuated by sighty different amounts. This difference is quite sma for ow offset frequencies, but the difference grows both as the frequency of the moduation increases, and as the carrier frequency approaches the fiter cutoff frequency where the fiter has a steeper ro-off. Therefore, if sma amounts of AM are known to be present and an unacceptabe eve of PM is seen at the LTC6957 output, it may be hepfu to change the input fiter setting to a higher cutoff frequency. Cross Tak from Loading at the LTC6957 Outputs Another mechanism to be aware of in the LTC6957 is cross-moduation of the outputs. Except for the CMOS, there is minima direct AM or PM moduation of the outputs by the power suppy. In the CMOS case, the V DD power suppy wi directy AM moduate the outputs, with a sma amount of AM to PM conversion. The thing to be aware of here is that there can be oadinduced disturbances interna to the LTC6957 that can moduate the other output. For instance, hooking up one output to an ADC encode input and the second output to the FPGA that performs the first DSP on the ADC outputs, can resut in considerabe kickback of FPGA generated signas into the LTC6957. If this cross-moduates over to the other output, a kinds of deeterious effects may be seen incuding tones, images, etc. The CMOS are more susceptibe to this than the LVPECL and LVDS (LTC6957-1/LTC6957-2). To prevent this, a buffer can be paced between the LTC6957 and the FPGA, even one that compromises the fu jitter performance consideraby. Because it is the ADC that is doing the samping the FPGA cock input has enough margin for error to quaify as a digita signa. For more information 31

32 APPLICATIONS INFORMATION 50Ω TERMINATION 2V 1.3V MINI-CIRCUITS ZHL N5500A 1 DUT REF AGILENT MHz 12.5dBm MCL LFCN MCL LFCN MINI-CIRCUITS ZX MINI-CIRCUITS ZFBT-6GW-FT SIG 2 SPUR INPUT CAL TONE MONITOR 6dB ATTENUATOR 10dB ATTENUATOR 10dB ATTENUATOR 3dB ATTENUATOR 3dB ATTENUATOR COUPL OUT IN COUPL IN OUT LINE STRETCHER 6957 F12 MINI-CIRCUITS ZHL MINI-CIRCUITS ZFDC MINI-CIRCUITS ZFDC ARRA L9428A Figure 12. Setup for LTC Phase Noise Measurement Using Agient E5505 Phase Noise Measurement Additive (aso caed residua) phase noise can be particuary chaenging to measure. Figure 12 shows a typica aboratory set-up for testing the LTC phase noise. The LTC has the owest broadband phase noise of the various dash numbers (equa to that of the ) and the owest cose-in noise with a corner frequency beow 2kHz, so it presents the most chaenging case. The various components and their roe wi be discussed as this wi iustrate both the care that must be taken to reaize the fu performance of the LTC6957, and the demanding nature of making phase noise measurements. The signa starts with a MHz CW tone from the Agient 8644 synthesizer at a fairy high power eve of 12.5dBm. Two series LPFs at 150MHz cut out a the high frequency noise components that woud otherwise contribute noise because of the aiasing caused by the imiting action of the LTC6957. A signa spitter then separates the signa in two; one path wi propagate through the DUT and the other won t, a common method used for measuring residua phase noise. 32 For more information In theory, a the phase noise in the signa source wi be rejected with the reading refecting ony the difference in noise between the two paths. However, the rejection is not perfect, particuary at very high offset frequencies where the phase difference between the two paths progressivey increases, thus the successive owpass fiters on the signa source. The Agient 5505 measurement system uses the N5500A front end, which incudes a mixer to compare the signa and reference phases. For ampifier noise, it is appropriate to feed the DUT path to the signa input, but for cock buffers that create fast cock edges, it is usuay advantageous to use the reference input, which seems to be sensitive ony to the edges and not noise throughout the period. This is a reasonabe thing to do because the LTC6957 is designed to drive ADC encode inputs or mixer ports which have the same quaitative properties. Both the signa and reference inputs to the test set need to be fairy arge (15dBm to 20dBm) to reaize the best noise foor, so both signa paths incude Mini-Circuits ZHL ow noise ampifiers to boost the signa. The LTC was operated from 2V/ 1.3V suppies so it

33 APPLICATIONS INFORMATION coud drive a 50Ω oad to ground directy, but this creates a DC offset (the signa is aways positive) that the ampifier caot take, so a bias tee was incuded in the DUT signa path. Ony the MHz sine wave wi be in the path without the DUT, going to the N5500A signa port, unti the first couper. This couper aows a spur input to be injected, whie a second couper aows the size of the spur, reative to the carrier, to be measured. More on that in a minute. The three attenuators in this signa path work with the ZHL to manage the dynamic range, whie the attenuators on the couping ports keep these terminas from degrading the measured noise. Finay, an ARRA L9428A ine stretcher is used to adjust for quadrature. One ast attenuator heps with impedance matching between the N5500A input and the ine stretcher output port. The E5505A can automaticay adjust the signa source phase/frequency for quadrature when measuring VCOs or synthesizers, but for additive noise this adjustment is manua because the adjustment must be made after the signa is spit into the two paths. The ine stretcher has a range of just 166ps, but with MHz, up to 20ns of adjustment may be needed (1/4 cyce). Not shown is the various short engths of SMA cabes and barre coupers that can aso be added or subtracted to adjust the reative phase of the two signa paths. LTC6957-1/LTC6957-2/ To caibrate E5505/N5500 measurements, the gain of the mixer must be known. The surest way to measure it at the actua frequencies being used is to inject a caibration tone. For a 10kHz offset, a MHz ow eve ( 10dBm) signa is fed into the first couper port. The requirements for this signa are not demanding, so a genera purpose synthesizer that can be frequency ocked, such as the HP8657B, can be used. The E5505 measures the ampitude of the resuting 10kHz mixer output, but to put that in context (so that it can ater cacuate resuts in dbc) it needs to know the size of the injected spur reative to the carrier. Therefore, that reative difference is measured using a spectrum anayzer coected to the attenuator on the second couper. Hopefuy the above discussion conveys the meticuous effort needed to measure additive phase noise of a singe device, at a singe operating frequency. Whie the circuitry in Figure 12 can be used to measure the entire spectrum of phase noise (a offset frequencies) as we as the phase noise at other cock frequencies, every cock frequency wi require manua adjusting for quadrature. The input LPFs wi either need to be changed to match the new cock frequency, or possiby ampitudes at various paces wi have to be adjusted to account for the frequency rooff therein. For more information 33

34 TYPICAL APPLICATIONS Crysta Osciator 5V IN + 1µF 0.01µF OUT BP LT V TO ALL V + POINTS 3.3V 10µF 0.1µF V + 50MHz BANDWIDTH 30pF 2 V + 12 SD1 V + V FILTA FILTB IN + IN V DD 11 OUT1 10 2k LTC GND 7 SD2 OUT2 GNDOUT µF 450Ω OUT TO 50Ω 0.3V P-P SQUARE WAVE Ω 150Ω 75pF 10MHz AT CUT 6957 TA02a Tota Phase Noise of 10MHz Crysta Osciator PHASE NOISE () MEASURED ON AGILENT E5052A CORRELATIONS 70 1Hz Hz Hz kHz kHz khz MHz k 10k k 1M 6957 TA02b 34 For more information