LTC6102 LTC6102-1/LTC6102HV Precision Zero Drift Current Sense Amplifi er DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Suppy Range: 4 to 6, 7 Maximum (LTC62) to, Maximum (LTC62H) n ±μ Input Offset Maximum n ±n/ C Input Offset Drift Maximum n Fast Response: μs Step Response n Gain Confi gurabe with Two Resistors n Low Input Bias Current: na Maximum n PSRR db Minimum n Output Currents up to ma n Operating Temperature Range: 4 C to 2 C n Disabe Mode (LTC62- Ony): μa Maximum n Avaiabe in 8-Lead MSOP and mm mm DFN Packages APPLICATIONS n Current Shunt Measurement n Battery Monitoring n Remote Sensing n Load Protection n Motor Contro n Automotive Contros L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. LTC62 Precision Zero Drift Current Sense Ampifi er DESCRIPTION The LTC 62/LTC62H are versatie, high votage, highside current sense ampifiers. Their high suppy votage rating aows their use in many high side appications, whie the ow drift and offset ensure accuracy across a wide range of operating conditions. The LTC62- is a version of the LTC62 that incudes a ow power disabe mode to conserve system standby power. The LTC62/LTC62H monitor current via the votage across an externa sense resistor (shunt resistor). Interna circuitry converts input votage to output current, aowing a sma sense signa on a arge common mode votage to be transated to a ground-referred signa. Low DC offset aows the use of very ow shunt resistor vaues and arge gain-setting resistors. As a resut, power oss in the shunt is reduced. The wide operating suppy and high accuracy make the LTC62 idea for a arge array of appications, from automotive, to industria and power management. A maximum input sense votage of 2 aows a wide range of currents and votages to be monitored. Fast response makes the LTC62 the perfect choice for oad current warnings and shutoff protection contro. A versions of the LTC62 are avaiabe in 8-ead MSOP and mm mm DFN packages. TYPICAL APPLICATION TO SENSE mω A Current Sense with ma Resoution and mw Maximum Dissipation L O A D 2Ω IN = LTC62 R INS INF SENSE = 249. SENSE R 4.99k.μF LTC24-62 TA *PROPER SHUNT SELECTION COULD ALLOW MONITORING OF CURRENTS IN EXCESS OF A μf TO μp DYNAMIC RANGE (db) Dynamic Current Measurement Range = mω Max SENSE = μ = mω Max SENSE = DYNAMIC RANGE RELATIE TO μ OFFSET OLTAGE... MAXIMUM SENSE OLTAGE () 62 TAb

2 LTC62 ABSOLUTE MAXIMUM RATINGS Tota Suppy otage ( to ): LTC62/LTC LTC62H... Input otage Range INF, INS... ( 4 to.) IN... ( 2 to ) EN... (. to 9) Differentia (INS IN), Second...6 Output otage Range LTC62/LTC62H... (. to 9) LTC (. to ) Input Current INF, INS...±mA IN...mA EN...±mA PIN CONFIGURATION (Note ) Output Current...(mA, ma) Output Short Circuit Duration... Indefinite Operating Temperature Range: (Note 2) LTC62C/LTC62C-/LTC62HC.. 4 C to 8 C LTC62I/LTC62I-/LTC62HI... 4 C to 8 C LTC62H/LTC62H- LTC62HH... 4 C to 2 C Specified Temperature Range: (Note 2) LTC62C/LTC62C-/LTC62HC... C to 7 C LTC62I/LTC62I-/LTC62HI... 4 C to 8 C LTC62H/LTC62H- LTC62HH... 4 C to 2 C Storage Temperature Range... 6 C to C TOP IEW INS INF /EN* DD PACKAGE 8-LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = 4 C/W EXPOSED PAD (PIN 9) IS, MUST BE SOLDERED TO PCB * FOR THE LTC62/LTC62H, EN FOR THE LTC62-8 IN INS INF 2 /EN* 4 TOP IEW 8 IN 7 6 MS8 PACKAGE 8-LEAD PLASTIC MSOP T JMAX = C, θ JA = 2 C/W * FOR THE LTC62/LTC62H, EN FOR THE LTC62- ORDEFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC62CDD#PBF LTC62CDD#TRPBF LCKH 8-Lead (mm mm) Pastic DFN C to 7 C LTC62IDD#PBF LTC62IDD#TRPBF LCKH 8-Lead (mm mm) Pastic DFN 4 C to 8 C LTC62HDD#PBF LTC62HDD#TRPBF LCKH 8-Lead (mm mm) Pastic DFN 4 C to 2 C LTC62CDD-#PBF LTC62CDD-#TRPBF LDYB 8-Lead (mm mm) Pastic DFN C to 7 C LTC62IDD-#PBF LTC62IDD-#TRPBF LDYB 8-Lead (mm mm) Pastic DFN 4 C to 8 C LTC62HDD-#PBF LTC62HDD-#TRPBF LDYB 8-Lead (mm mm) Pastic DFN 4 C to 2 C LTC62HCDD#PBF LTC62HCDD#TRPBF LCC 8-Lead (mm mm) Pastic DFN C to 7 C LTC62HIDD#PBF LTC62HIDD#TRPBF LCC 8-Lead (mm mm) Pastic DFN 4 C to 8 C LTC62HHDD#PBF LTC62HHDD#TRPBF LCC 8-Lead (mm mm) Pastic DFN 4 C to 2 C LTC62CMS8#PBF LTC62CMS8#TRPBF LTCKJ 8-Lead Pastic MSOP C to 7 C LTC62IMS8#PBF LTC62IMS8#TRPBF LTCKJ 8-Lead Pastic MSOP 4 C to 8 C 2

3 LTC62 ORDEFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC62HMS8#PBF LTC62HMS8#TRPBF LTCKJ 8-Lead Pastic MSOP 4 C to 2 C LTC62CMS8-#PBF LTC62CMS8-#TRPBF LTDXZ 8-Lead Pastic MSOP C to 7 C LTC62IMS8-#PBF LTC62IMS8-#TRPBF LTDXZ 8-Lead Pastic MSOP 4 C to 8 C LTC62HMS8-#PBF LTC62HMS8-#TRPBF LTDXZ 8-Lead Pastic MSOP 4 C to 2 C LTC62HCMS8#PBF LTC62HCMS8#TRPBF LTCB 8-Lead Pastic MSOP C to 7 C LTC62HIMS8#PBF LTC62HIMS8#TRPBF LTCB 8-Lead Pastic MSOP 4 C to 8 C LTC62HHMS8#PBF LTC62HHMS8#TRPBF LTCB 8-Lead Pastic MSOP 4 C to 2 C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC62CDD LTC62CDD#TR LCKH 8-Lead (mm mm) Pastic DFN C to 7 C LTC62IDD LTC62IDD#TR LCKH 8-Lead (mm mm) Pastic DFN 4 C to 8 C LTC62HDD LTC62HDD#TR LCKH 8-Lead (mm mm) Pastic DFN 4 C to 2 C LTC62CDD- LTC62CDD-#TR LDYB 8-Lead (mm mm) Pastic DFN C to 7 C LTC62IDD- LTC62IDD-#TR LDYB 8-Lead (mm mm) Pastic DFN 4 C to 8 C LTC62HDD- LTC62HDD-#TR LDYB 8-Lead (mm mm) Pastic DFN 4 C to 2 C LTC62HCDD LTC62HCDD#TR LCC 8-Lead (mm mm) Pastic DFN C to 7 C LTC62HIDD LTC62HIDD#TR LCC 8-Lead (mm mm) Pastic DFN 4 C to 8 C LTC62HHDD LTC62HHDD#TR LCC 8-Lead (mm mm) Pastic DFN 4 C to 2 C LTC62CMS8 LTC62CMS8#TR LTCKJ 8-Lead Pastic MSOP C to 7 C LTC62IMS8 LTC62IMS8#TR LTCKJ 8-Lead Pastic MSOP 4 C to 8 C LTC62HMS8 LTC62HMS8#TR LTCKJ 8-Lead Pastic MSOP 4 C to 2 C LTC62CMS8- LTC62CMS8-#TR LTDXZ 8-Lead Pastic MSOP C to 7 C LTC62IMS8- LTC62IMS8-#TR LTDXZ 8-Lead Pastic MSOP 4 C to 8 C LTC62HMS8- LTC62HMS8-#TR LTDXZ 8-Lead Pastic MSOP 4 C to 2 C LTC62HCMS8 LTC62HCMS8#TR LTCB 8-Lead Pastic MSOP C to 7 C LTC62HIMS8 LTC62HIMS8#TR LTCB 8-Lead Pastic MSOP 4 C to 8 C LTC62HHMS8 LTC62HHMS8#TR LTCB 8-Lead Pastic MSOP 4 C to 2 C Consut LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifi cations, go to:

4 LTC62 ELECTRICAL CHARACTERISTICS (LTC62, LTC62-) The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. = Ω, R = k, SENSE = (see Figure for detais), = 2, =, EN = 2.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Suppy otage Range 4 6 OS Input Offset otage (Note ) Δ OS /ΔT Input Offset otage (Note 4) Input Offset otage Drift (Note ) SENSE = μ 6 6 = 4 SENSE = μ 6 6 = 4 SENSE = μ LTC62C, LTC62I, LTC62C-, LTC62I- LTC62H, LTC62H- I B Input Bias Current (Note ) = 4k, SENSE = 2m LTC62C, LTC62I, LTC62C-, LTC62I- LTC62H, LTC62H- PSRR Power Suppy Rejection Ratio SENSE = μ, = 6 to 6 SENSE(MAX) Input Sense otage Fu Scae ( IN ) Maximum Output otage (LTC62) Maximum Output otage (LTC62-) SENSE = μ, = 4 to 6 Error <%, = k, R = k 6 6 = 4 SENSE = 2m, R = k 2 6 = 6 = 4 SENSE = 2m, R = k = 6 = 2 = 4 I Maximum Output Current 6 6, = k, R = k, SENSE =. = 4, = Ω, R = k, SENSE = m t r Input Step Response (to 2. on a Output Step) BW Signa Bandwidth I = 2μA, = Ω, R = 4.99k I = ma, = Ω, R = 4.99k μ μ μ μ n/ C n/ C pa na na db db 4 db db Δ SENSE = m Transient, 6 6, = Ω, μs R = 4.99k, I = μa = 4. μs e N Input Noise otage.hz to Hz 2 μ P-P I S Suppy Current = 4, I =, = k, R = k 27 4 μa 47 μa = 6, I =, = k, R = k μa μa = 2, I =, = k, R = k 4 μa 2 μa = 6, I =, = k, R = k 42 7 μa LTC62C, LTC62I, LTC62C-, LTC62I- 6 μa LTC62H, LTC62H- 67 μa I DIS Suppy Current in Disabe Mode (LTC62- Ony) EN =.8, = 2 EN =.8, = 6 8 μa μa ENL Enabe Input otage Low (LTC62- Ony) ma ma khz khz 4

5 ELECTRICAL CHARACTERISTICS LTC62 (LTC62, LTC62-) The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. = Ω, R = k, SENSE = (see Figure for detais), = 2, =, EN = 2.2 uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENH Enabe Input otage High (LTC62- Ony) 2.2 I BEN Enabe Input Pin Current (LTC62- Ony) EN = to 9 8 μa t ON Turn-On Time (LTC62- Ony) EN = 2.2, SENSE = m, Output Settes to Within % of μs Fina aue t OFF Turn-Off Time (LTC62- Ony) EN =.8, SENSE = m, Suppy Current Drops to Less μs Than % of Nomina aue f S Samping Frequency khz ELECTRICAL CHARACTERISTICS (LTC62H) The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. = Ω, R = k, SENSE = (see Figure for detais), = 2, = uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Suppy otage Range OS Input Offset otage (Note ) Input Offset otage (Note 4) SENSE = μ 6 = SENSE = μ 6 = Δ OS /ΔT Input Offset otage Drift (Note ) SENSE = μ LTC62HC, LTC62HI LTC62HH I B Input Bias Current (Note ) = 4k, SENSE = 2m LTC62HC, LTC62HI LTC62HH PSRR Power Suppy Rejection Ratio SENSE = μ, = 6 to SENSE(MAX) Input Sense otage Fu Scae ( IN ) SENSE = μ, = to Error <%, = k, R = k 6 = Maximum Output otage SENSE = 2m, R = k 2 = I Maximum Output Current 6, = k, R = k, SENSE =. =, = Ω, R = k, SENSE = m t r Input Step Response (to 2. on a Output Step) BW Signa Bandwidth I = 2μA, = Ω, R = 4.99k I = ma, = Ω, R = 4.99k μ μ μ μ n/ C n/ C pa na na db db Δ SENSE = m Transient, 6, μs = Ω, R = 4.99k, I = μa =. μs e N Input Noise otage.hz to Hz 2 μ P-P 4 2 db db ma ma khz khz

6 LTC62 ELECTRICAL CHARACTERISTICS (LTC62H) The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at. = Ω, R = k, SENSE = (see Figure for detais), = 2, = uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I S Suppy Current =, I =, = k, R = k 27 4 μa 47 μa = 6, I =, = k, R = k μa μa = 2, I =, = k, R = k 29 4 μa 2 μa =, I =, = k, R = k 42 7 μa LTC62HC, LTC62HI 6 μa LTC62HH 67 μa f S Samping Frequency khz Note : Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. In addition to the Absoute Maximum Ratings, the output current of the LTC62 must be imited to ensure that the power dissipation in the LTC62 does not aow the die temperature to exceed C. See the Appications Information Output Current Limitations Due to Power Dissipation for further information. Note 2: The LTC62C/LTC62C-/LTC62HC are guaranteed to meet specified performance from C to 7 C. The LTC62C/LTC62C-/ LTC62HC are designed, characterized and expected to meet specifi ed performance from 4 C to 8 C but are not tested or QA samped at these temperatures. LTC62I/LTC62I-/LTC62HI are guaranteed to meet specifi ed performance from 4 C to 8 C. The LTC62H/ LTC62H-/LTC62HH are guaranteed to meet specifi ed performance from 4 C to 2 C. Note : These Parameters are guaranteed by design and are not % tested. Thermocoupe effects precude measurements of these votage eves during automated testing. Note 4: Limits are fuy tested. Limit is determined by high speed automated test capabiity. Note : I B specifi cation is imited by practica automated test resoution. Pease refer to the Typica Performance Characteristics section for more information regarding actua typica performance. For tighter specifi cations, pease contact LTC Marketing. 6

7 LTC62 TYPICAL PERFORMANCE CHARACTERISTICS INPUT OFFSET (μ) 2 Input OS vs Temperature Input OS vs Suppy otage Input Sense Range S = 4 S = TEMPERATURE ( C) 62 G INPUT OFFSET (μ) 2 T A = 4 C T A = C T A = 7 C T A = 8 C T A = 2 C SUPPLY OLTAGE () 62 G2 MAXIMUM SENSE () SUPPLY () 62 G MAXIMUM () LTC62: Maximum vs Temperature 4 2 S = 6 S = S = S = 4 2 S = TEMPERATURE ( C) 62 G4 MAXIMUM () LTC62H: Maximum vs Temperature 4 2 S = S = S = S = TEMPERATURE ( C) 62 G MAXIMUM I (ma) LTC62/LTC62-: I Maximum vs Temperature S = S = S = S =. S = TEMPERATURE ( C) 62 G6 MAXIMUM I (ma) LTC62H: I Maximum vs Temperature S = S = 4.. S = S = TEMPERATURE ( C) 62 G7 GAIN (db) Gain vs Frequency I = 2μA DC I = ma DC = 2 = Ω R = 4.99k k k k M M FREQUENCY (Hz) 62 G9 BIAS CURRENT (pa) Input Bias Current vs Temperature S = S = 6 S = 2 S = 6 S = TEMPERATURE ( C) 62 G 7

8 LTC62 TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT (μa) LTC62: Suppy Current vs Suppy otage T A = 2 C T A = 4 C T A = 8 C T A = 7 C T A = C SUPPLY CURRENT (μa) LTC62H: Suppy Current vs Suppy otage T A = 2 C T A = 4 C T A = 8 C T A = 7 C T A = C m. Step Response m to m SENSE = 2 = Ω R = 4.99k SENSE = SUPPLY OLTAGE () IN = = 2M 62 G SUPPLY OLTAGE () IN = = 2M 62 G2 TIME (μs/di) 62 G Step Response m to 2m Step Response m Step Response Rising Edge m 2m SENSE = 2 = Ω R = 4.99k SENSE = m SENSE C LOAD = pf C LOAD = pf = 2 = Ω R = 4.99k SENSE =. SENSE = m I = = 2 = Ω R = 4.99k SENSE =.. I = μa TIME (μs/di) 62 G4 TIME (μs/di) 62 G TIME (ns/di) 62 G7.. Step Response Faing Edge SENSE = m I = I = μa TIME (ns/di) = 2 = Ω R = 4.99k SENSE = 62 G8 PSRR (db) PSRR vs Frequency 6 = 2 = Ω 4 R = 4.99k A = 49.9 I = μa 2. k k k M FREQUENCY (Hz) 62 G9 NOISE (μ) Input Referred Noise.Hz to Hz = 2 = Ω R = k SENSE = 2m TIME (s) 62 G2 8

9 LTC62 TYPICAL PERFORMANCE CHARACTERISTICS OLTAGE NOISE DENSITY (n/ Hz) 2 Noise Spectra Density GAIN = SUPPLY CURRENT (μa) LTC62-: Suppy Current vs Suppy otage EN = 2 SENSE =. T A = 2 C T A = 4 C T A = 8 C SUPPLY CURRENT (μa) LTC62-: Suppy Current vs Suppy otage when Disabed EN =.8 T A = 2 C T A = 4 C T A = 8 C k k k M FREQUENCY (Hz) 62 G OLTAGE SUPPLY () SUPPLY OLTAGE () 62 G22 62 G2 SUPPLY CURRENT (μa) LTC62-: Suppy Current vs Enabe otage TURN OFF (2) = 6 = ENABLE OLTAGE () SENSE = 62 G24 ENABLE PIN CURRENT (μa) LTC62-: Enabe Pin Current vs Enabe otage = ENABLE OLTAGE () 62 G LTC62-: Turn-On Time = 2 SENSE = m 4... LTC62-: Turn-Off Time = 2 SENSE = m OLTAGE () 4 2 EN OLTAGE () EN TIME (μs) 62 G TIME (μs) 62 G27 9

10 LTC62 PIN FUNCTIONS INS (Pin ): Ampifi er Inverting Input. When tied to INF, the interna sense ampifier wi drive INS to the same potentia as IN. INF (Pin 2): Force Input. This pin carries the input current from and must be tied to INS near. A resistor ( ) tied from to INF sets the output current I = SENSE /. SENSE is the votage across the externa. (Pin, LTC62/LTC62H Ony): Negative Suppy. EN (Pin, LTC62- Ony): Enabe Pin, Referenced to the Negative Suppy. When the enabe pin is pued high, the LTC62- is active. When the enabe pin is pued ow or eft f oating, the LTC62- is disabed. (Pin 4): Open-Drain Current output. wi source a current that is proportiona to the sense votage into an externa resistor. I is the same current that enters INF. (Pin ): Negative Suppy. (Pin 6): Interna Reguated Suppy. A.μF (or arger) capacitor shoud be tied from to. is not designed to drive externa circuits. (Pin 7): Positive Suppy. Suppy current is drawn through this pin. IN (Pin 8): Ampifier Noninverting Input. Must be tied to the system oad end of the sense resistor. The IN pin has an interna k series resistor designed to aow arge input votage transients or accidenta disconnection of the sense resistor. This pin can be hed up to 2 beow the INS pin indefi nitey, or up to 6 beow the INS pin for up to one second (see Absoute Maximum Ratings). Exposed Pad (Pin 9, DFN Ony):. The Exposed Pad must be sodered to PCB.

11 LTC62 BLOCK DIAGRAM BATTERY.μF SENSE INF I LOAD L O A D INS IN k k I = SENSE R R EN* *LTC62- ONLY 62 BD ENABLE Figure. Bock Diagram and Typica Connection

12 LTC62 APPLICATIONS INFORMATION The LTC62 high side current sense ampifier (Figure ) provides accurate monitoring of current through a userseected sense resistor. The sense votage is ampifi ed by a user-seected gain and eve shifted from the positive power suppy to a ground-referred output. The output signa is anaog and may be used as is or processed with an output fi ter. Theory of Operation An interna sense ampifier oop forces INS to have the same potentia as IN. Connecting an externa resistor,, between INS and forces a potentia across that is the same as the sense votage across. A corresponding current, SENSE /, wi f ow through. The high impedance inputs of the sense ampifier wi not conduct this input current, so it wi fow through the INF pin and an interna MOSFET to the output pin. The output current can be transformed into a votage by adding a resistor from to. The output votage is then O = I R. Usefu Gain Confi gurations GAIN R SENSE AT = Ω k 2m 2Ω k m Ω k m 499 Ω 4.99k m Seection of Externa Current Sense Resistor The externa sense resistor,, has a significant effect on the function of a current sensing system and must be chosen with care. First, the power dissipation in the resistor shoud be considered. The system oad current wi cause both heat dissipation and votage oss in. As a resut, the sense resistor shoud be as sma as possibe whie sti providing the input dynamic range required by the measurement. Note that input dynamic range is the difference between the maximum input signa and the minimum accuratey reproduced signa, and is imited primariy by input DC offset of the interna ampifier of the LTC62. In addition, must be sma enough that SENSE does not exceed 2 the maximum sense votage specified by the LTC62 or the sense resistor, even under peak oad conditions. As an exampe, an appication may require that the maximum sense votage be m. If this appication is expected to draw 2A at peak oad, shoud be no more than mω. Once the maximum vaue is determined, the minimum sense resistor vaue wi be set by the resoution or dynamic range required. The minimum signa that can be accuratey represented by this sense amp is imited by the input offset. As an exampe, the LTC62 has a typica input offset of μ. If the minimum current is ma, a sense resistor of mω wi set SENSE to μ. This is the same vaue as the input offset. A arger sense resistor wi reduce the error due to offset by increasing the sense votage for a given oad current. For this exampe, choosing a mω wi maximize the dynamic range and provide a system that has m across the sense resistor at peak oad (2A), whie input offset causes an error equivaent to ony.6ma of oad current. Peak dissipation is 2W. If a.mω sense resistor is empoyed, then the effective current error is 6mA (.% of fu-scae), whie the peak sense votage is reduced to m at 2A, dissipating ony 2mW. The ow offset and corresponding arge dynamic range of the LTC62 make it more fexibe than other soutions in this respect. The μ typica offset gives db of dynamic range for a sense votage that is imited to m max, and over 6dB of dynamic range if a maximum of 2 is aowed. The previous exampe assumes that a arge output dynamic range is required. For circuits that do not require arge dynamic range, the wide input range of the LTC62 may be used to reduce the size of the sense resistor, reducing power oss and increasing reiabiity. For exampe, in a A circuit requiring 6dB of dynamic range, the input offset and drift of most current-sense soutions wi require that the shunt be chosen so that the sense votage is at east m at fu scae so that the minimum input is greater than μ. This wi cause power dissipation in excess of W at fu scae! That much power oss can put

13 LTC62 APPLICATIONS INFORMATION a significant oad on the power suppy and create therma design headaches. In addition, heating in the sense resistor can reduce its accuracy and reiabiity. In contrast, the arge dynamic range of the LTC62 aows the use of a much smaer sense resistor. The LTC62 aows the minimum sense votage to be reduced to ess than μ. The peak sense votage woud then be m, dissipating ony W at A in a μω sense resistor! With a speciaized sense resistor, the same system woud aow peak currents of more than A without exceeding the input range of the LTC62 or damaging the shunt. DYNAMIC RANGE (db) Dynamic Range vs Maximum Power Dissipation in = mω = Ω db: MAX SENSE = 6 4dB: MAX SENSE = m 4 = μω = μω = mω 2... MAXIMUM POWER DISSIPATION (W) DYNAMIC RANGE RELATIE TO μ, MINIMUM SENSE MAX I SENSE = A MAX I SENSE = A MAX I SENSE = A = mω 62 AI Sense Resistor Connection Kevin connection of IN and INS to the sense resistor shoud be used in a but the owest power appications. Soder connections and PC board interconnections that carry high current can cause significant error in measurement due to their reativey arge resistances. One mm mm square trace of one-ounce copper is approximatey.mω. A m error can be caused by as itte as 2A fowing through this sma interconnect. This wi cause a % error in a m signa. A A oad current in the same interconnect wi cause a % error for the same m signa. An additiona error is caused by the change in copper resistance over temperature, which is in excess of.4%/ C. By isoating the sense traces from the high-current paths, this error can be reduced by orders of magnitude. A sense resistor with integrated Kevin sense terminas wi give the best resuts. Figure 2 iustrates the recommended method. Note that the LTC62 has a Kevin input structure such that current fows into INF. The INS and INF pins shoud be tied as cose as possibe to. This reduces the parasitic series resistance so that may be as ow as Ω, aowing high gain settings to be used with very itte gain error. R IN R IN IN LOAD PUT R LTC62 TIE AS CLOSE TO AS POSSIBLE R 62 F2 Figure 2. Kevin Input Connection Preserves Accuracy with Large Load Current and Large Output Current LTC62 * INS INF LOAD C REG *ISHAY CS62 SERIES WITH 4 PAD KELIN CONNECTION Seection of Externa Input Resistor,.μF The externa input resistor,, contros the transconductance of the current sense circuit, I = SENSE /. For exampe, if =, then I = SENSE / or I = ma for SENSE = m. shoud be chosen to provide the required resoution whie imiting the output current. At ow suppy votage, I may be as much as ma. By setting such that

14 LTC62 APPLICATIONS INFORMATION the argest expected sense votage gives I = ma, then the maximum output dynamic range is avaiabe. Output dynamic range is imited by both the maximum aowed output current (Note ) and the maximum aowed output votage, as we as the minimum practica output signa. If ess dynamic range is required, then can be increased accordingy, reducing the output current and power dissipation. If sma sense currents must be resoved accuratey in a system that has very wide dynamic range, a smaer may be used if the max current is imited in another way, such as with a Schottky diode across (Figure ). This wi reduce the high current measurement accuracy by imiting the resut, whie increasing the ow current measurement resoution. This approach can be hepfu in cases where occasiona arge burst currents may be ignored. LOAD 62 F D SENSE Figure. Shunt Diode Limits Maximum Input otage to Aow Better Low Input Resoution Without Overranging Care shoud be taken when designing the PC board ayout for, especiay for sma vaues. A trace and interconnect impedances wi increase the effective vaue, causing a gain error. It is important to note that the arge temperature drift of copper resistance wi cause a change in gain over temperature if proper care is not taken to reduce this effect. To further imit the effect of trace resistance on gain, maximizing the accuracy of these circuits, the LTC62 has been designed with a Kevin input. The inverting termina (INS) is separate from the feedback path (INF). During operation, these two pins must be connected together. The design of the LTC62 is such that current into INS is input bias current ony, which is typicay 6pA at 2 C. Amost a of the current from f ows into INF, through the LTC62, and into R via the pin. In order to minimize gain error, INS shoud be routed in a separate path from INF to a point as cose to as possibe. In addition, the higher potentia termina of shoud be connected directy to the positive termina of (or any input votage source). For the highest accuracy, shoud be a four-termina resistor if it is ess than Ω. Seection of Externa Output Resistor, R The output resistor, R, determines how the output current is converted to votage. is simpy I R. In choosing an output resistor, the max output votage must fi rst be considered. If the circuit that is driven by the output does not have a imited input votage, then R must be chosen such that the max output votage does not exceed the LTC62 max output votage rating. If the foowing circuit is a buffer or ADC with imited input range, then R must be chosen so that I (MAX) R is ess than the aowed maximum input range of this circuit. In addition, the output impedance is determined by R. If the circuit to be driven has high enough input impedance, then amost any output impedance wi be acceptabe. However, if the driven circuit has reativey ow input impedance, or draws spikes of current, such as an ADC might do, then a ower R vaue may be required in order to preserve the accuracy of the output. As an exampe, if the input impedance of the driven circuit is times R, then the accuracy of wi be reduced by % since: R RIN( DRIEN) = I R RIN( DRIEN) = I R. I R = 99 Error Sources The current sense system uses an ampifier and resistors to appy gain and eve shift the resut. The output is then dependent on the characteristics of the ampifier, such as gain and input offset, as we as resistor matching. 4

15 LTC62 APPLICATIONS INFORMATION Ideay, the circuit output is: R = SENSE ; = R I R IN SENSE SENSE SENSE In this case, the ony error is due to resistor mismatch, which provides an error in gain ony. Output Error, E, Due to the Ampifi er DC Offset otage, OS E (OS) = OS (R / ) The DC offset votage of the ampifi er adds directy to the vaue of the sense votage, SENSE. This error is very sma (μ typ) and may be ignored for reasonabe vaues of. See Figure 4. For very high dynamic range, this offset can be caibrated in the system due to its extremey ow drift. For instance if I BIAS is na and R is k, the output error is μ. Note that in appications where, I B () causes a votage offset in that cances the error due to I B () and E (IBIAS). In appications where <, the bias current error can be simiary reduced if an externa resistor () = ( ) is connected as shown in Figure. Under both conditions: E (IBIAS) = ± R I OS ; I OS = I B () I B () Adding R IN as described wi maximize the dynamic range of the circuit. For ess sensitive designs, R IN is not necessary. PUT ERROR (%)... IN = FOR A SHUNT IN = m, I SHUNT = 2A ERROR DUE TO OS IS 6mA INPUT OLTAGE () 62 F4 Figure 4. LTC62 Output Error Due to Typica Input Offset vs Input otage LOAD IN LTC62 = RIN RSENSE INS INF 62 F Figure. Second Input R Minimizes Error Due to Input Bias Current R.μF Output Error, E, Due to the Bias Currents, I B () and I B () The input bias current of the LTC62 is vanishingy sma. However, for very high resoution, or at high temperatures where I B increases due to eakage, the current may be signifi cant. The bias current I B () f ows into the positive input of the interna op amp. I B () f ows into the negative input. E (IBIAS) = R ((I B () ( / ) I B ()) Since I B () I B () = I BIAS, if << then, E (IBIAS) R I BIAS Cock Feedthrough, Input Bias Current The LTC62 uses auto-zeroing circuitry to achieve an amost zero DC offset over temperature, sense votage, and power suppy votage. The frequency of the cock used for auto-zeroing is typicay khz. The term cock feedthrough is broady used to indicate visibiity of this cock frequency in the op amp output spectrum. There are typicay two types of cock feedthrough in auto zeroed amps ike the LTC62. The first form of cock feedthrough is caused by the setting of the interna samping capacitor and is input referred; that is, it is mutipied by the interna oop gain

16 LTC62 APPLICATIONS INFORMATION of the amp. This form of cock feedthrough is independent of the magnitude of the input source resistance or the magnitude of the gain setting resistors. The LTC62 has a residue cock feedthrough of ess then μ RMS input referred at khz. The second form of cock feedthrough is caused by the sma amount of charge injection occurring during the samping and hoding of the amp s input offset votage. The current spikes are mutipied by the impedance seen at the input terminas of the amp, appearing at the output mutipied by the interna oop gain of the interna op amp. To reduce this form of cock feedthrough, use smaer vaued gain setting resistors and minimize the source resistance at the input. Input bias current is defined as the DC current into the input pins of the op amp. The same current spikes that cause the second form of cock feedthrough described above, when averaged, dominate the DC input bias current of the op amp beow 7 C. As temperature increases, the eakage of the ESD protection diodes on the inputs increases the input bias currents of both inputs in the positive direction, whie the current caused by the charge injection stays reativey constant. At temperatures above 7 C, the eakage current dominates and both the negative and positive pins input bias currents are in the positive direction (into the pins). Output Current Limitations Due to Power Dissipation The LTC62 can deiver more than ma continuous current to the output pin. This current f ows through and enters the current sense amp via the INF pin. The power dissipated in the LTC62 due to the output current is: P = ( INF ) I Since INF, P ( ) I There is aso power dissipated due to the quiescent suppy current: P Q = I S The tota power dissipated is the output current dissipation pus the quiescent dissipation: At maximum suppy and maximum output current, the tota power dissipation can exceed mw. This wi cause significant heating of the LTC62 die. In order to prevent damage to the LTC62, the maximum expected dissipation in each appication shoud be cacuated. This number can be mutipied by the θ JA vaue isted in the package section on page 2 to find the maximum expected die temperature. This must not be aowed to exceed C or performance may be degraded. As an exampe, if an LTC62 in the MSOP package is to be biased at ± suppy with ma output current at 8 C: P Q(MAX) = I DD(MAX) (MAX) = 9mW P (MAX) = I (MAX) = 6mW T RISE = θ JA P TOTAL(MAX) T MAX = T AMBIENT T RISE T MAX must be < 2 C P TOTAL(MAX) 99mW and the max die temp wi be C If this same circuit must run at 2 C, the max die temp wi increase to 4 C. (Note that suppy current, and therefore P Q, is proportiona to temperature. Refer to Typica Performance Characteristics section.) Note that the DD package has a smaer θ JA than the MSOP package, which wi substantiay reduce the die temperature at simiar power eves. The LTC62H can be used at votages up to. This additiona votage requires that more power be dissipated for a given eve of current. This wi further imit the aowed output current at high ambient temperatures. It is important to note that the LTC62 has been designed to provide at east ma to the output when required, and can deiver more depending on the conditions. Care must be taken to imit the maximum output current by proper choice of sense and input resistors and, if input faut conditions are ikey, an externa camp. P TOTAL = P P Q 6

17 LTC62 APPLICATIONS INFORMATION Output Fitering The output votage,, is simpy I Z. This makes fitering straightforward. Any circuit may be used which generates the required Z to get the desired fiter response. For exampe, a capacitor in parae with R wi give a ow pass response. This wi reduce unwanted noise from the output, and may aso be usefu as a charge reservoir to keep the output steady whie driving a switching circuit such as a mux or ADC. This output capacitor in parae with an output resistor wi create a poe in the output response at: f db = 2 π R C BAT IN LOAD ( 2) TO LTC62 INS INF 62 F6 R Figure 6. Powered Separatey from Load Suppy ( BAT ).μf Usefu Equations BAT Input otage: otage Gain: Current Gain: SENSE =I SENSE I I SENSE SENSE Transconductance: Transimpedance: I I = R RIN R = SENSE SENSE SENSE R SENSE RIN = RIN R = RSENSE R IN LOAD IN LTC62 INS INF. F R 62 F7 Input Sense Range The inputs of the LTC62 can function from to ( 2). Not ony does this aow a wide SENSE range, it aso aows the input reference to be separate from the positive suppy (Figure 6). Note that the difference between BAT and must be no more than the input sense votage range isted in the Eectrica Characteristics tabe. Monitoring otages Above and Leve Transation The LTC62 may be configured to monitor votages that are higher than its suppy, provided that the negative termina of the input votage is within the input sense range of the LTC62. Figure 7 iustrates a circuit in which the LTC62 has its suppy pin tied to the ower potentia termina of the sense resistor instead of the higher potentia termina. The Figure 7. LTC62 Suppy Current Monitored with Load operation of the LTC62 is such that the INS and INF pins wi servo to within a few microvots of IN, which is shorted to. Since the input sense range of the LTC62 incudes, the circuit wi operate propery. The votage across wi be hed across by the LTC62, causing current SENSE / to fow to R. In this case, the suppy current of the LTC62 is aso monitored, as it fows through. Because the votage across is not restricted to the sense range of the LTC62 in this circuit, SENSE can be arge compared to the aowed sense votage. This faciitates the sensing of very arge votages, provided that is chosen so that SENSE / does not exceed 7

18 LTC62 APPLICATIONS INFORMATION the aowed output current. The gain is sti controed by R /, so either gain or attenuation may be appied to the input signa as it is transated to the output. Finay, the input may be a votage source rather than a sense resistor, as shown in Figure 8. This circuit aows the transation of a wide variety of input signas across the entire suppy range of the LTC62 with ony a tiny offset error whie retaining simpe gain contro set by R /. Again, very arge votages may be sensed as ong as is chosen so that I does not exceed the aowed output current. For exampe, IN may be as arge as with = k, or as arge as with = k. For a maximum input and a maximum output, = k and R = k wi aow the LTC62H to transate IN to with a common mode votage of up to. For the case where a arge input resistor is used, a simiar resistor in series with IN wi reduce error due to input bias current. IN CM IN INS INF LTC62 by effectivey reducing the suppy votage to the part by D. In addition, if the output of the LTC62 is wired to a device that wi effectivey short it to high votage (such as through an ESD protection camp) during a reverse suppy condition, the LTC62 s output shoud be connected through a resistor or Schottky diode (Figure ). Response Time The LTC62 is designed to exhibit fast response to inputs for the purpose of circuit protection or signa transmission. This response time wi be affected by the externa circuit in two ways, deay and speed. BATT L O A D IN D LTC62 INS INF R Ω.μF R2 4.99k.μF 62 F9 LTC62 R BATT Figure 9. Schottky Prevents Damage During Suppy Reversa = IN R Figure 8. otage Leve-Shift Circuit 62 F8 Reverse Suppy Current Some appications may be tested with reverse-poarity suppies due to an expectation of this type of faut during operation. The LTC62 is not protected internay from externa reversa of suppy poarity. To prevent damage that may occur during this condition, a Schottky diode shoud be added in series with (Figure 9). This wi imit the reverse current through the LTC62. Note that this diode wi imit the ow votage performance of the L O A D IN D LTC62 INS INF R Ω.μF R k R2 4.99k 62 F Figure. Additiona Resistor R Protects Output During Suppy Reversa ADC 8

19 LTC62 APPLICATIONS INFORMATION If the output current is very ow and an input transient occurs, there may be a deay before the output votage begins changing. This can be reduced by increasing the minimum output current, either by increasing or decreasing. The effect of increased output current is iustrated in the step response curves in the Typica Performance Characteristics section of this datasheet. Note that the curves are abeed with respect to the initia output currents. The speed is aso affected by the externa circuit. In this case, if the input changes very quicky, the interna ampifier wi sew the gate of the interna output FET (Figure ) in order to cose the interna oop. This resuts in current fowing through and the interna FET. This current sew rate wi be determined by the ampifier and FET characteristics as we as the input resistor,. Using a smaer wi aow the output current to increase more quicky, decreasing the response time at the output. This wi aso have the effect of increasing the maximum output current. Using a arger R wi aso decrease the response time, since = I R. Reducing and increasing R wi both have the effect of increasing the votage gain of the circuit. Bandwidth For appications that require higher bandwidth from the LTC62, care must be taken in choosing. For a genera-purpose op-amp, the gain-bandwidth product is used to determine the speed at a given gain. Gain is determined by externa resistors, and the gain-bandwidth product is an intrinsic property of the ampifier. The same is true for the LTC62, except that the feedback resistance is determined by an interna FET characteristic. The feedback impedance is approximatey /g m of the interna MOSFET. The impedance is reduced as current into INF is increased. At ma, the impedance of the MOSFET is on the order of kω. sets the cosed-oop gain of the interna oop as /( g m ). The bandwidth is then imited to GBW ( g m ), with a maximum bandwidth of around 2MHz. This is iustrated in the characteristic curves, where gain vs frequency for two input conditions is shown. The exact impedance of the MOSFET is difficut to determine, as it is a function of input current, process, and capacitance, and has a very different characteristic for ow currents vs high currents. However, it is cear that smaer vaues of and smaer vaues of I wi generay resut in ower cosed-oop bandwidth. SENSE and shoud be chosen to maximize both I and cosed-oop gain for highest speed. Theoreticay, maximum bandwidth woud be achieved for the case where IN = DC and = k, giving I = ma and a cosed-oop gain near. However, this may not be possibe in a practica appication. Note that the MOSFET g m is determined by the average or DC vaue of I, not the peak vaue. Adding DC current to a sma AC input wi hep increase the bandwidth. Bypassing The LTC62 has an internay reguated suppy near for interna bias. It is not intended for use as a suppy or bias pin for externa circuitry. A.μF capacitor shoud be connected between the and pins. This capacitor shoud be ocated very near to the LTC62 for the best performance. In appications which have arge suppy transients, a 6.8 zener diode may be used in parae with this bypass capacitor for additiona transient suppression. Enabe Pin Operation The LTC62- incudes an enabe pin which can pace the part into a ow power disabe state. The enabe pin is a ogic input pin referenced to and accepts standard TTL ogic eves regardess of the votage. When the enabe pin is driven high, the part is active. When the enabe pin is foating or pued ow, then the part is disabed and draws very itte suppy current. When driven high, the enabe pin draws a few microamps of input bias current. If there is no externa ogic suppy avaiabe, the enabe pin can be pued to the suppy through a arge vaue resistor. The votage at the enabe pin wi be camped by the buit-in ESD protection structure (which acts ike a zener diode). The resistor shoud be sized so that the current through the resistor is a few miiamps or ess to prevent any reduction in ong-term reiabiity. For practica purposes, the current through the resistor shoud be minimized to save power. The resistor vaue is imited by the input bias current requirements of the enabe 9

20 LTC62 APPLICATIONS INFORMATION LOAD R BIAS 2.7M IN EN LTC62- = RIN RSENSE Figure INS INF 62 F R.μF pin. Figure shows the LTC62- with a 2.7M pu-up resistor to imit the current to ess than 2μA with a 6 suppy, which is enough to satisfy the input bias current requirement. Start-Up Current The start-up current of the LTC62 when the part is powered on or enabed (LTC62-) consists of three parts: the first is the current necessary to charge the bypass capacitor, which is nominay.μf. Since the votage charges to approximatey 4. beow the votage, this can require a significant amount of start-up current. The second source is the active suppy current of the LTC62 ampifi er, which is not signifi canty greater during start-up than during norma operation. The third source is the output current of the LTC62, which upon start-up may temporariy drive the output high. This coud cause miiamps of output current (imited mosty by the input resistor ) to fow into the output resistor and/or the output imiting ESD structure in the LTC62. This is a temporary condition which wi cease when the LTC62 ampifier settes into norma cosed-oop operation. When the LTC62- is disabed, the interna ampifier is aso shut down, which means that the discharge rate of the.μf capacitor is very ow. This is significant when the LTC62- is disabed to save power, because the recharging of the.μf capacitor is a significant portion of the overa power consumed in startup. Figure 2 shows the discharge rate of the.μf capacitor after the LTC62- is shut down at room temperature. In a system where the LTC62- is disabed for short periods, the start-up power (and therefore the average power) can be reduced since the bypass capacitor is never significanty discharged. The time required to charge the capacitor wi aso be reduced, aowing the LTC62- to start-up more quicky. ENABLE OLTAGE () TIME (ms) 62 F2 Figure 2. LTC62- otage During Bypass Capacitor Discharge when Disabed EN = OLTAGE () 2

21 TYPICAL APPLICATIONS Bidirectiona Current Sense Circuit with Separate Charge/Discharge Output LTC62 I CHARGE RSENSE I DISCHARGE CHARGER C Ω IN INS C Ω D Ω INS IN D Ω BATT INF.μF.μF INF L O A D LTC62 R C 4.99k C D R D 4.99k LTC62 62 TA2 DISCHARGING: CHARGING: R D D D = I DISCHARGE ( ) WHEN I DISCHARGE R C C C = I CHARGE ( ) WHEN I CHARGE LTC62 Monitors Its Own Suppy Current IN INS R I SUPPLY BATT L O A D I LOAD INF.μF LTC62 = 49.9 (I LOAD I SUPPLY ) R2 4.99k 62 TA 2

22 LTC62 TYPICAL APPLICATIONS 6-Bit Resoution Unidirectiona Output into LTC24 ADC 4 TO 6 SENSE IN INS Ω I LOAD POWER ENABLE L O A D EN LTC62- INF R 4.99k.μF 2 4 REF CC IN 9 SCK 8 LTC24- SDD 7 IN C C REF GND F O 6 μf TO μp R = SENSE = 49.9 ADC FULL-SCALE = 2. IN 62 TA Inteigent High-Side Switch with Current Monitor LOGIC μf 6 4.μF FAULT 47k 8 Ω % INS OFF ON μf 4 2 LT9 6 RS Ω SUB8N6- INF IN LTC62 O 4.99k L O A D I L O = 49.9 R S I L FOR R S = mω, O = 2. AT I L = A (FULL SCALE) 62 TA6 22

23 LTC62 TYPICAL APPLICATIONS Input Overvotage Protection k W D Z IN k INS LOAD INF.μF LTC62 DZ: CENTRAL SEMICONDUCTOR CMZ9B 8.W ZENER DIODE R 62 TA7 Simpe Current Monitor DANGER! Letha Potentias Present Use Caution SENSE IN INS Ω I SENSE L O A D INF.μF DANGER!! HIGH OLTAGE!! LTC62 BZX884-C M BAT46 M AND M2 ARE FQDP TM R = SENSE = 49.9 IN M2 R 4.99k 62 TA8 2M 2

24 LTC62 PACKAGE DESCRIPTION DD Package 8-Lead Pastic DFN (mm mm) (Reference LTC DWG # Rev C).7 ±. R =.2 TYP 8.4 ±.. ±. 2. ±..6 ±. (2 SIDES) PACKAGE LINE.2 ±.. BSC 2.8 ±. RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN TOP MARK (NOTE 6).2 REF NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE LINE M-229 ARIATION OF (WEED-) 2. DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON TOP AND BOTTOM OF PACKAGE. ±. (4 SIDES).7 ±....6 ±. (2 SIDES) 4.2 ±.. BSC 2.8 ±. BOTTOM IEW EXPOSED PAD (DD8) DFN 9 RE C MS8 Package 8-Lead Pastic MSOP (Reference LTC DWG # Rev F)..2 (.8.4) (NOTE ) (.2) REF 24.2 (.26) MIN.42.8 (.6.) TYP (..).2.4 (.26.6).6 (.26) BSC RECOMMENDED SOLDER PAD LAY GAUGE PLANE.8 (.7).24 (.) DETAIL A DETAIL A 6 TYP..2 (.2.6) NOTE:. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.2mm (.6") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.2mm (.6") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.2mm (.4") MAX SEATING PLANE (.9.6). (.4) MAX.22.8 (.9.) TYP.6 (.26) BSC (.8.4) (NOTE 4).86 (.4) REF.6.8 (.4.2) MSOP (MS8) 7 RE F

25 LTC62 REISION HISTORY (Revision history begins at Rev D) RE DATE DESCRIPTION PAGE NUMBER D 8/ Updated graph 2 8 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 2

26 LTC62 TYPICAL APPLICATION Remote Current Sense with Simpe Noise Fiter TIE AS CLOSE TO AS POSSIBLE IN INS f C = 2 R C LOAD INF.μF LTC62 LONG WIRE ADC 62 TA9 R C REMOTE ADC RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT 66 Rai-to-Rai Input/Output, Micropower Op Amp CM Extends 44 above EE, μa Suppy Current, Shutdown Function LT67/LT68/ LT69 LT787/LT787H Singe/Dua/Quad, Rai-to-Rai, Micropower Op Amp Precision, Bidirectiona, High Side Current Sense Ampifi er CM Extends 44 above EE,.4/μs Sew Rate, >MHz Bandwidth, <2μA Suppy Current per Ampifi er 2.7 to 6 Operation, 7μ Offset, 6μA Current Draw LTC92 Dua 48 Suppy and Fuse Monitor ±2 Transient Protection, Drives Three Optoisoators for Status LT99 High otage, Gain Seectabe Difference Ampifi er ±2 Common Mode, Micropower, Pin Seectabe Gain =, LT99 Precision, Gain Seectabe Difference Ampifi er 2.7 to ±8, Micropower, Pin Seectabe Gain = to 4 LTC2/LTC2/ LTC22 Singe/Dua/Quad Zero-Drift Op Amp μ Offset, n/ C Drift, Input Extends Down to LTC4 Couomb Counter/Battery Gas Gauge Indicates Charge Quantity and Poarity LT6 Gain-Seectabe High Side Current Sense Ampifi er 4. to 48 Operation, Pin-Seectabe Gain:, 2., 2, 2, 4, / LTC6/ LTC6H High otage High Side Current Sense Ampifi er in SOT-2 4 to 6/ to Operation, Externa Resistor Set Gain LTC6 Dua High Side Precision Current Sense Ampifi er 4 to 6, Gain Confi gurabe, 8-Pin MSOP LTC64 Bidirectiona High Side Precision Current Sense 4 to 6, Gain Confi gurabe, 8-Pin MSOP Ampifi er LT6 Precision Rai-to-Rai Input Current Sense Ampifi er Input CM Extends 44 Above and. Beow, 2.8 to 6 Operation LT66 Low Cost, High Side Precision Current Sense 2.7 to 6, Gain Confi gurabe, SOT2 Ampifi er LT67 High Temperature High Side Current Sense Ampifi er in SOT to 6, Fuy Tested at C and C 26 LT 8 RE D PRINTED IN USA Linear Technoogy Corporation 6 McCarthy Bvd., Mipitas, CA (48) 42-9 FAX: (48) LINEAR TECHNOLOGY CORPORATION 27