Lectura del conversor A/D serie ADS1286 de Burr-Brown.

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1 Lab. de Diseño de Circuitos y Sistemas Electrónicos. Ing. Electrónica. Descripción. Lectura del conversor A/D serie de Burr-Brown. Implementar el enlace serie con el conversor A/D serie de Burr-Brown de bits. El valor de la conversión se muestra se muestra en los dos visualizadores 7 segmentos en formato hexadecimal para los 8 bits más significativos, y los cuatro bits menos significativos se muestran en los LED existentes en la placa. La lectura se hace automáticamente a una frecuencia de reloj aproximada de 5 khz. Consultar las hojas de especificación para conocer el funcionamiento e interface con el circuito. Profesores: Alfredo Rosado. Manuel Bataller.

2 -Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES SERIAL INTERFACE GUARANTEED NO MISSING CODES khz SAMPLING RATE LOW SUPPLY CURRENT: 5µA APPLICATIONS REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION TRANSDUCER INTERFACE BATTERY OPERATED SYSTEMS DESCRIPTION The is a -bit, khz analog-to-digital converter with a differential input and sample and hold amplifier and consumes only 5µA of supply current. The offers an SPI and SSI compatible serial interface for communications over a two or three wire interface. The combination of a serial two wire interface and micropower consumption makes the ideal for remote applications and for those requiring isolation. The is available in a 8-pin plastic mini DIP and a 8-lead SOIC. SAR Control V REF +In In CDAC Serial Interface S/H Amp Comparator International Airport Industrial Park Mailing Address: PO Box 4, Tucson, AZ 8574 Street Address: 67 S. Tucson Blvd., Tucson, AZ 8576 Tel: (5) 746- Twx: Internet: Cable: BBRCORP Telex: FAX: (5) Immediate Product Info: (8) Burr-Brown Corporation PDS-5B Printed in U.S.A. October, 998 SBAS5

3 SPECIFICATIONS At T A = T MIN to T MAX, +V CC = +5V, V REF = +5V, f SAMPLE =.5kHz,, f CLK = 6 f SAMPLE, unless otherwise specified., A K, B C, L PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Range +In ( In) V REF V Absolute Input Voltage +In. V CC +. V In. +. V Capacitance 5 pf Leakage Current ± µa SYSTEM PERFORMANCE Resolution Bits No Missing Codes Bits Integral Linearity ± ± ±.5 ± LSB Differential Linearity ±.5 ±. ±.75 ±.5 ±.75 LSB Offset Error.75 ± LSB Gain Error ± ±8 LSB Noise 5 µvrms Power Supply Rejection 8 db SAMPLING DYNAMICS Conversion Time Clk Cycles Acquisition Time.5 Clk Cycles Small Signal Bandwidth 5 khz DYNAMIC CHARACTERISTICS Total Harmonic Distortion V IN = 5.Vp-p at khz 85 db V IN = 5.Vp-p at 5kHz 8 db SINAD V IN = 5.Vp-p at khz 7 db Spurious Free Dynamic Range V IN = 5.Vp-p at khz 9 db REFERENCE INPUT REF Input Range.5.5 V CC +.5V V Input Resistance CS = V CC 5 MΩ CS = GND, f CLK = Hz 5 MΩ Current Drain CS = V CC..5 µa t CYC 64µs, f CLK 5kHz.4 µa t CYC = 8µs, f CLK = khz.4 µa DIGITAL INPUT/OUTPUT Logic Family CMOS Logic Levels: V IH I IH = +5µA +V CC V V IL I IL = +5µA..8 V V OH I OH = 5µA +V CC V V OL I OL = 5µA..4 V Data Format Straight Binary POWER SUPPLY REQUIREMENTS Power Supply Voltage V CC V Quiescent Current, V ANA t CYC 64µS, f CLK 5kHz 4 µa t CYC = 9µS, f CLK = khz 5 5 µa Power Down CS = V CC µa TEMPERATURE RANGE Specified Performance, K, L +7 C A, B, C C Specifications same as grade to the left. TIMING CHARACTERISTICS f CLK = khz, T A = T MIN to T MAX. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t SMPL Analog Input Sample Time See Operating Sequence.5. Clk Cycles t SMPL (MAX) Maximum Sampling Frequency khz t CONV Conversion Time See Operating Sequence Clk Cycles t ddo Delay TIme, to Data Valid See Test Circuits 85 5 ns t dis Delay TIme, CS to Hi-Z See Test Circuits 5 5 ns t en Delay TIme, to Enable See Test Circuits 5 ns t hdo Output Data Remains Valid After C LOAD = pf 5 ns t f Fall Time See Test Circuits 7 ns t r Rise Time See Test Circuits 6 ns t CSD Delay Time, CS to See Operating Sequence ns t SUCS Delay Time, CS to See Operating Sequence ns

4 ABSOLUTE MAXIMUM RATINGS () +V CC... +6V Analog Input....V to (+V CC + mv) Logic Input....V to (+V CC + mv) Case Temperature... + C Junction Temperature C Storage Temperature C External Reference Voltage V NOTE: () Stresses above these ratings may permanently damage the device. PIN CONFIGURATION V REF 8 +V CC ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr- Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. +In In 7 6 GND Pin Mini PDIP 8-Lead SOIC PIN ASSIGNMENTS PIN NAME DESCRIPTION V REF Reference Input. +In Non Inverting Input. In Inverting Input. Connect to ground or remote ground sense point. 4 GND Ground. 5 Chip Select when low, Shutdown Mode when high. 6 The serial output data word is comprised of bits of data. In operation the data is valid on the falling edge of. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next edges. 7 Data Clock synchronizes the serial data transfer and determines conversion speed. 8 +V CC Power Supply. PACKAGE/ORDERING INFORMATION PACKAGE INTEGRAL TEMPERATURE DRAWING PRODUCT LINEARITY RANGE PACKAGE NUMBER () P ± C to +7 C Plastic DIP 6 PK ± C to +7 C Plastic DIP 6 PL ± C to +7 C Plastic DIP 6 U ± C to +7 C SOIC 8 UK ± C to +7 C SOIC 8 UL ± C to +7 C SOIC 8 PA ± 4 C to +85 C Plastic DIP 6 PB ± 4 C to +85 C Plastic DIP 6 PC ± 4 C to +85 C Plastic DIP 6 UA ± 4 C to +85 C SOIC 8 UB ± 4 C to +85 C SOIC 8 UC ± 4 C to +85 C SOIC 8 NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

5 TYPICAL PERFORMANCE CURVES At T A = +5, V CC = +5V, V REF = +5V, f SAMPLE =.5kHz, f CLK = 6 f SAMPLE, unless otherwise specified..5 REFERENCE CURRENT vs SAMPLE RATE 4. REFERENCE CURRENT vs TEMPERATURE Reference Current (µa) Reference Current (µa) Sample Rate (khz) Temperature ( C) Change in Offset (LSB) CHANGE IN OFFSET vs REFERENCE VOLTAGE Reference Voltage (V) Delta from 5 C (LSB) CHANGE IN OFFSET vs TEMPERATURE Temperature ( C). CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE 4 CHANGE IN GAIN vs REFERENCE VOLTAGE Delta from +5V Reference (LSB) Change in Differential Linearity (LSB) Change in Integral Linearity (LSB) Change in Gain (LSB) Reference Voltage (V) 4 5 Reference Voltage (V) 4

6 TYPICAL PERFORMANCE CURVES (CONT) At T A = +5, V CC = +5V, V REF = +5V, f SAMPLE =.5kHz, f CLK = 6 f SAMPLE, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE. DIFFERENTIAL LINEARITY ERROR vs CODE Effective Number of Bits (rms) Differential Linearity Error (LSB)..... Reference Voltage (V) Code Signal-to-(Noise + Distortion) (db) SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY Frequency (khz) Spurious Free Dynamic Range and Signal-to-Noise Ratio (db) SPURIOUS FREE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO vs FREQUENCY 9 Spurious Free Dynamic Range Signal-to-Noise Ratio 5 4. Frequency (khz) Signal-to-(Noise + Distortion) (db) SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL Input Level (db) Total Harmonic Distortion (db) TOTAL HARMONIC DISTORTION vs FREQUENCY Frequency (khz) 5

7 TYPICAL PERFORMANCE CURVES (CONT) At T A = +5, V CC = +5V, V REF = +5V, f SAMPLE =.5kHz, f CLK = 6 f SAMPLE, unless otherwise specified. 496 POINT FFT PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 9 Magnitude (db) Peak-to-Peak Noise (LSB) Frequency (khz). Reference Voltage (V) POWER SUPPLY REJECTION vs RIPPLE FREQUENCY.5 CHANGE GAIN vs TEMPERATURE Power Supply Rejection (db) V RIPPLE = mv Delta from 5 C (LSB) Ripple Frequency (khz) Temperature ( C) POWER DOWN SUPPLY CURRENT vs TEMPERATURE 4 SUPPLY CURRENT vs TEMPERATURE.5 5 Supply Current (µa).5 Supply Current (µa) 5 f SAMPLE =.5kHz f SAMPLE =.6kHz Temperature ( C) Temperature ( C) 6

8 TYPICAL PERFORMANCE CURVES (CONT) At T A = +5, V CC = +5V, V REF = +5V, f SAMPLE =.5kHz, f CLK = 6 f SAMPLE, unless otherwise specified.. INTEGRAL LINEARITY ERROR vs CODE DIGITAL INPUT LINE THRESHOLD vs SUPPLY VOLTAGE Integral Linearity Error (LSB).... Digital Input Threshold Voltage (V) Code Supply Voltage (V) INPUT LEAKAGE CURRENT vs TEMPERATURE Leakage Current (na) Temperature ( C) 7

9 TIMING DIAGRAMS AND TEST CIRCUITS.4V kω V OH Test Point V OL pf C LOAD t r t f Load Circuit for t ddo, t r, and t f Voltage Waveforms for Rise and Fall Times t r, and t f V IL Test Point V CC t ddo kω t dis Waveform, t en V OH V OL pf C LOAD t dis Waveform t hdo Voltage Waveforms for Delay Times, t ddo Load Circuit for t dis and t den V IH Waveform () 9% t dis Waveform () % DOUT V OL B Voltage Waveforms for t dis t en NOTES: () Waveform is for an output with internal conditions such that the output is HIGH unless disabled by the output control. () Waveform is for an output with internal conditions such that the output is LOW unless disabled by the output control. Voltage Waveforms for t en 8

10 t CYC t SUCS POWER DOWN t CSD NULL HI-Z BIT B B B9 B8 B7 B6 B5 B4 B B B B () t (MSB) SMPL t CONV t DATA HI-Z NULL BIT B B B9 B8 Note: () After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output LSB-First data then followed with zeroes indefinitely. t CYC t SUCS POWER DOWN t CSD NULL HI-Z BIT B B B9 B8 B7 B6 B5 B4 B B B B B B B B4 t (MSB) SMPL t CONV B5 B6 B7 B8 B9 B B () t DATA HI-Z Note: () After completing the data transfer, if further clocks are applied with CS LOW, the ADC will output zeroes indefinitely. t DATA : During this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes. FIGURE. Operating Sequence. SERIAL INTERFACE The communicates with microprocessors and other external digital systems via a synchronous -wire serial interface. synchronizes the data transfer with each bit being transmitted on the falling edge and captured on the rising edge in the receiving system. A falling CS initiates data transfer as shown in Figure. After CS falls, the second pulse enables. After one null bit, the A/D conversion result is output on the line. Bringing CS high resets the for the next data exchange. MICROPOWER OPERATION With typical operating currents of 5µA and automatic shutdown between conversions, the achieves extremely low power consumption over a wide range of sample rates (see Figure ). The auto-shutdown allows the supply current to drop with sample rate. SHUTDOWN The is equipped with automatic shutdown features. The device draws power when the CS pin is LOW and shuts down completely when the pin is HIGH. The bias circuit and comparator powers down and the reference input becomes high impedance at the end of each conversion leaving the running to clock out the LSB first data or zeroes. If the CS input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high. Supply Current (µa) T A = 5 C V CC = 5V V REF = 5V f CLK = 6 f SAMPLE.k k k k Sample Rate (khz) FIGURE. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate. 9

11 MINIMIZING POWER DISSIPATION In systems that have significant time between conversions, the lowest power drain will occur with the minimum CS LOW time. Bringing CS LOW, transferring data as quickly as possible, and then bringing it back HIGH will result in the lowest current drain. This minimizes the amount of time the device draws power. After a conversion the A/D automatically shuts down even if CS is held LOW. If the clock is left running to clock out LSB-data or zero, the logic will draw a small amount of current (see Figure ). Supply Current (µa) FIGURE. Shutdown Current with CS HIGH is Lower than with CS LOW. RC INPUT FILTERING It is possible to filter the inputs with an RC network as shown in Figure 4. For large values of C FILTER (e.g., µf), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately I DC = pf x V IN /t CYC and is roughly proportional to V IN. When running at the minimum cycle time of 64µs, the input current equals.56µa at V IN = 5V. In this case, a filter resistor of 75Ω will cause.lsb of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. V IN T A = 5 C V CC = +5V V REF = +5V f CLK = 6 f SAMPLE R FILTER I DC C FILTER CS = LOW (GND) CS HIGH (V CC ).. Sample Rate (khz) REDUCED REFERENCE OPERATION The effective resolution of the can be increased by reducing the input span of the converter. The exhibits good linearity and gain over a wide range of reference voltages (see Typical Performance Curves Change in Linearity vs Reference Voltage and Change in Gain vs Reference Voltage ). However, care must be taken when operating at low values of V REF because of the reduced LSB size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low V REF values:. Offset. Noise OFFSET WITH REDUCED V REF The offset of the has a larger effect on the output code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The Typical Performance Curve Change in Offset vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of V OS. For example, a V OS of µv which is. LSB with a 5V reference becomes.5lsb with a V reference and.5lsbs with a.v reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the negative input of the. NOISE WITH REDUCED V REF The total input referred noise of the can be reduced to approximately µv peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 5V reference, the µv noise is only.5lsb peak-to-peak. In this case, the noise will contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a.5v reference this same µv noise is.lsb peak-to-peak. If the reference is further reduced to V, the µv noise becomes equal to.8lsbs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary. FIGURE 4. RC Input Filtering.

12 +5V +5V +5V R 8 46kΩ D R 5kΩ R 59kΩ R 6 MΩ R 5kΩ V REF C.µF R 7 Ω OPA7 U C µf MUX R 9 kω R kω.4v.v.v TC TC Thermocouple TC ISO Thermal Block R 4 kω C.µF C 4 µf R 5 C 5 5Ω.µF U µp A A U R kω R kω.v -Wire Interface U 4 FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the. +V CC REF (µa).µf V REF 8 RTD 4 µp FIGURE 6. with RTD Sensor.

13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright, Texas Instruments Incorporated

12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER

12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER -Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES SERIAL INTERFACE GUARANTEED NO MISSING CODES khz SAMPLING RATE LOW SUPPLY CURRENT: 5µA APPLICATIONS REMOTE DATA ACQUISITION ISOLATED DATA