Performance Comparison of Three-Step and Six-Step PWM in Average-Current-Controlled Three-Phase Six-Switch Boost PFC Rectifier

Transcription

1 Perfrmance Cmparisn f Three-Step and Six-Step PWM in Average-Current-Cntrlled Three-Phase Six-Switch Bst PFC Rectifier Laszl Huber, Misha Kumar, and Milan M. Jvanvić Delta Prducts Crpratin P.O. Bx 73 5 Davis Drive Research Triangle Park, NC 779, USA Abstract In this paper, a three-step PWM methd fr the average-current-cntrlled three-phase six-switch bst PFC rectifier is prpsed. It is shwn that the three-step PWM cmpared t the cnventinal six-step PWM exhibits a lwer ttal harmnic distrtin f input currents and higher pwer factr. Hwever, the three-step PWM, unlike the six-step PWM, is adversely affected by duty-cycle limitatins and has unbalanced cnductin lsses f the upper and lwer switches f the three-phase rectifier bridge. The average-current cntrl with three-step and six-step PWM is illustrated with Matlab/Simulink simulatin wavefrms and experimentally verified n a 3-kW prttype. I. INTRODUCTION Tday, active three-phase PFC rectifiers need t meet very challenging perfrmance requirements. In the majrity f applicatins, the input current f active three-phase PFC rectifiers is required t have a ttal harmnic distrtin (THD) less than 5% and a pwer factr (PF) greater than.99 []. One f the mst cst-effective tplgies that can meet these requirements is the three-phase six-switch bst PFC rectifier [], which is usually implemented withut neutralpint cnnectin. A number f cntrl methds that can achieve a high quality f input currents in the three-phase six-switch bst PFC rectifier are available [3], [4]. Generally, appraches using direct cntrl f input current versus, fr example, direct pwer cntrl, result in better quality f the input currents [5]. Tday, the cntrl circuit is usually implemented with digital technlgy. One direct current cntrl methd, well suited fr digital implementatin, is the average current cntrl [6], [7]. In three-wire, three-phase applicatins, because the sum f the phase currents is zer, the cntrl can be implemented by having nly tw ut f three current cntrllers actively shaping the current at a given time. The desired current in the inactive-cntrller phase is btained by the sum f currents f the actively cntrlled phases. One implementatin f this cntrl methd is based n dividing the line cycle f the input phase vltages int six 6 segments (six-step PWM) as shwn in Fig. [8], [9]. In each 6 segment, the cntrller in the phase with the highest abslute value vltage is disabled, i.e., switches in the crrespnding leg are turned ff, which results in reduced switching lsses. DISABLED PHASE p S ap S bp S cp v a v b v c v a v b La L b i a> i b < ar br C p V ω t v c L c i c < cr C n I II III IV V VI S an S bn S cn p n i = i + i a ab ac D ap S bp S cp v ac > iac a i ab b i bc c v ab > v bc La i a> L b i b < i b = i ab i L c i c < i = i + i c ac bc bc ar v arbr v arcr S bn br S cn cr C p C n V n (c) Fig. Six-step PWM: 6 segments, circuit diagram in segment I, (c) simplified circuit diagram in segment I /5/$3. 5 IEEE 86

2 v a v b v c I II III I v envp ω t v c v a v b v envn 4 36 I II III Fig. Three-step PWM with segments referenced t: psitive envelpe, negative envelpe f input phase vltages. In this paper, anther implementatin f this cntrl methd is prpsed. It is based n dividing the line cycle f the input phase vltages int three segments (three-step PWM) as shwn in Fig.. In each segment, the cntrller in the phase with the mst psitive (r mst negative) phase vltage is disabled, i.e., the switches in the crrespnding leg are turned ff. The three-step PWM is equivalent t the discntinuus space-vectr mdulatin (SVM) with unbalanced cnductin lsses between the upper and lwer switches []. A detailed perfrmance cmparisn f the three-step and six-step PWM in the average-current cntrlled three-phase six-switch bst PFC rectifier is als prvided in the paper. It is shwn that the three-step PWM cmpared t the six-step PWM exhibits lwer THD f input currents and higher PF. The peratin f the three-step and six-step PWM is illustrated with Matlab/Simulink simulatin wavefrms and experimentally verified n a 3-kW prttype. TABLE I - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR SIX-STEP PWM 6 Segment dap dan dbp dbn dcp dcn I -dab dab +dca -dca II -dca +dca dbc -dbc III +dab -dab -dbc dbc IV -dab +dab dca -dca V -dca dca +dbc -dbc VI dab -dab -dbc +dbc TABLE II - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR THREE-STEP PWM REFERENCED TO POSITIVE ENVELOPE OF PHASE VOLTAGES Segment dap dan dbp dbn dcp dcn I -dab dab +dca -dca II +dab -dab -dbc dbc III - dca dca +dbc -dbc TABLE III - STEADY-STATE DUTY-CYCLE OF SWITCHES FOR THREE-STEP PWM REFERENCED TO NEGATIVE ENVELOPE OF PHASE VOLTAGES Segment dap dan dbp dbn dcp dcn I -dca + dca dbc -dbc II -dab +dab dca - dca III dab -dab -dbc +dbc ω t II. AVERAGE CURRENT CONTROL WITH THREE-STEP AND SIX-STEP PWM In the six-step PWM, a line cycle f input phase vltages is divided int six 6 segments such that within a 6 segment nne f the three phase vltages changes sign, as shwn in Fig.. In each 6 segment, the cntrller in the phase with the highest abslute value vltage is disabled, i.e., switches in the crrespnding leg are turned ff. Fr example, in segment I, the cntrller in phase a is disabled, i.e., switches S ap and S an are turned ff, as shwn in Fig.. The simplified circuit diagram f the three-phase six-switch bst PFC rectifier with six-step PWM in segment I is shwn in Fig. (c). Since in segment I, the leg in phase a is disabled and phase current i a is psitive, rectifier input ar is cnnected t the psitive utput rail (thrugh dide D ap). By sinusidal mdulatin f switches in legs b and c, desired sinusidal average phase-t-phase vltages v arbr and v arcr can be generated between the rectifier inputs, respectively. As the sum f the phase-phase vltages at the rectifier inputs must be zer, desired vltage v brcr is autmatically generated. T generate sinusidal average phase-t-phase vltages between rectifier inputs, the current cntrllers are designed t cntrl phase-phase currents. The utput f the phase-phase-current cntrllers determines the phase-phase duty cycles d ab, d bc, and d ca s that in steady-state peratin v arbr=d abv, v brcr=d bcv, and v crar=d cav. Switch duty cycles d ap, d bp and d cp are btained frm phase-phase duty cycles s that d ab=d ap-d bp, d bc=d bp-d cp, and d ca=d cp-d ap. Fr example, in segment I, d ap= and, therefre, d bp=-d ab and d cp=+d ca. It shuld be nted that d ap= means that rectifier input ar is cnnected t the psitive utput rail due t the cnductin f dide D ap. The steady-state duty cycle f all switches is summarized in Table I, whereas, the variatin f duty cycle d ap during the whle line cycle is shwn in Fig. 3 d ap d ca d ab d ca d ab.65.5 D min ω t I II III IV V VI D max Fig. 3 Duty cycle f upper switch in phase a fr six-step PWM at Vrms input vltage..95 d ap d ap.5 d ab d ca ω t I II III d ca d ab I D max D min ω t I II III Fig. 4 Duty cycle f upper switch in phase a fr three-step PWM referenced t: psitive envelpe, negative envelpe f input phase vltages (Vrms). 86

3 as an example. As can be seen in Fig. 3, duty cycle d ap exhibits abrupt changes at 6 -segment transitins, which induces input-current transients at the segment transitins. These transients, which can be seen as ntches and glitches in the input current wavefrms and can be regarded as segmenttransitin nise, may cause false segment detectin in the sixstep PWM. In the prpsed three-step PWM, a line cycle f input phase vltages is divided int three segments such that within a segment ne phase vltage is always greater r smaller than the ther tw phase vltages, as shwn in Figs. and, respectively. Accrdingly, the three-step PWM is either referenced t the psitive r t the negative envelpe f the phase vltages. In each segment, the cntrller in the phase with the mst psitive (r mst negative) phase vltage is disabled, i.e., the switches in the crrespnding leg are turned ff. Similarly t the six-step PWM, the cntrl gal is t generate sinusidal average phase-t-phase vltages between the rectifier inputs ar, br and cr, and, therefre, the current cntrllers are designed t cntrl the phase-phase currents. The steady-state duty cycles f the switches perating with three-step PWM referenced t the psitive and negative envelpe f the phase vltages are summarized in Tables Ind III, respectively, whereas, the variatin f the crrespnding duty cycle d ap during the whle line cycle is shwn in Figs. 4 and 4. As can be seen in Fig. 4, duty cycle d ap des nt exhibit abrupt changes at -segment transitins. As a result, the three-step PWM exhibits much reduced ntches and glitches at the segment transitins s that segment detectin is much less sensitive t segment-transitin nise cmpared t that in the six-step PWM. Cmparing duty cycle d ap in Figs. 3 and 4, it can be cncluded that practical duty-cycle limitatins nly affect the three-step PWM. As can be seen frm Fig. 3, fr a minimum duty cycle D min=.5 and maximum duty cycle D max=.95, as an example, the duty-cycle limitatins d nt have effect n the six-step PWM circuit peratin because the duty-cycles f the switches in the tw active phases are in the range. In Fig. 3, when the switches in leg a are turned ff, d ap= in segment nd d ap= in segment IV is achieved thrugh the cnductin f dides D ap and D an, respectively. Hwever, fr the three-step PWM implementatin, the limited duty-cycle range affects circuit peratin and its perfrmance. As can be seen in Fig. 4, at the beginning f segment II duty cycle d ap is required t cntinuusly decrease frm unity, whereas at the end f segment III d ap is required t cntinuusly increase t unity. Hwever, if the maximum duty cycle is limited t D max=.95, the phase current will be distrted at the I-t-Ind III-t-I segment transitins. Similarly, as can be seen in Fig. 4, at the end f segment I duty cycle d ap is required t decrease t zer, whereas at the beginning f segment III d ap is required t increase frm zer. Hwever, if the minimum duty cycle is limited t D min=.5, the phase current will be distrted at the I-t-Ind II-t-III segment transitins. It shuld be nted that fr bth six-step and three-step PWM, identical peratin can be achieved if instead f phase-t-phase-current cntrllers, phase-current cntrllers are used with apprpriate zer-sequence-signal (ZSS) injectin. The implementatin with phase-current cntrllers and ZSS injectin is described in the next sectin. III. POWER STAGE AND CONTROL CIRCUIT The simplified circuit diagram f the three-phase sixswitch bst PFC rectifier is shwn in Fig. 5. The switches are implemented with IGBTs in a six-pack mdule []. The switching frequency is selected as f sw = khz, which is the p v a v b v c i a i b i c L a L b L c S ap S bp S cp S an S bn S cn C p C n + v - OUTPUT VOLTAGE SENSING ANTIALIASING FILTER.5V Offset LINE VOLTAGE SENSING ANTIALIASING FILTER.5V Offset PHASE CURRENT SENSING LOW-PASS FILTER S an DUTY-CYCLE FEEDFORWARD v ab v ref i ash i bsh CURRENT CONTROLLER v absh v cash 3 i ab 3 v a S ap n DPWM SEG STEP LOGIC d ab d ca VOLTAGE FEEDFORWARD i abref K AB B m C C A v ab AVG v ab v EA v VOLTAGE CONTROLLER SEG SEGMENT DETECTION Fig. 5 Simplified circuit diagram f pwer stage (L a=l b=l c=mh, C p=c n=4µf) and blck diagram f cntrl circuit. v ref Phase-Phase AB v Phase-Phase BC b v Nte: i Phase-Phase CA c DSP ash = i ashifted - ntatin fr digital values 863

4 maximum recmmended f sw fr the IGBT mdule. The input phase vltage range is ± 5% Vrms, 455 Hz, the nminal utput vltage is 4 V, and the maximum utput pwer is 3 kw. The blck diagram f the cntrl circuit cmmn fr bth six-step and three-step PWM implemented with phase-phase current cntrllers is als shwn in Fig. 5. Average-current cntrl is implemented using digital signal prcessr (DSP) TMS3F88 frm TI []. Fr average-current cntrl, the input phase-phase vltages, phase currents, and the utput vltage are sensed and cnverted t digital signals thrugh the -bit analg-digital cnverter () f the DSP. The input vltage range f the is -3 V, i.e., the full-scale range = 3 V. As nly psitive vltages can be applied t the input f the, the biplar phase-phase vltages and phase currents are scaled t ±/ and level shifted by /. The utput signals f the DSP are the digital PWM (DPWM) gate signals fr the bttm switches S xn, xϵ{a,b,c}. The DPWM perates with a triangular carrier. As the clck frequency f the DSP is f sysclck = MHz, the peak value f the triangular carrier is C pk = / f sysclck/f sw = 5. All the sensed signals are sampled at the peak f the triangular carrier. The crner frequency f the input- and utputvltage antialiasing filters is f AAFin = 3 khz and f AAFut = 55 Hz, respectively, whereas the crner frequency f the lw-pass filter f the sensed inductr-currents is f LPF = 9.5 khz. The vltage cntrller is implemented with PI cmpensatin (fr better regulatin f the utput vltage), whereas, the current cntrller is implemented with P cmpensatin which exhibits better perfrmance cmpared t that with PI cmpensatin. Namely, as it was shwn in [3] fr the three-phase six-switch bst PFC rectifier with average-current cntrl and with mismatched input-vltage and input-current sensing gains, the current cntrller with P cmpensatin exhibits lwer THD f input currents and higher PF cmpared t that f PI cmpensatin. The average-current cntrl implementatin als includes vltage feedfrward (VFF) [6] and duty-cycle feedfrward (DFF) [4]. Generally, VFF can make the utput vltage practically insensitive t line-vltage variatins. Hwever, VFF with P- v a DUTY-CYCLE FEEDFORWARD + ZSS INJECTION v a + v ref v ab CURRENT CONTROLLER v ca i a 3 i aref Phase A Phase B Phase C v a AVG S an D an D CCa v a n S ap DPWM K AB B m C C A v b VOLTAGE CONTROLLER Fig. 6 Blck diagram f cntrl circuit fr implementatin f six-step and three-step PWM with phase-current cntrllers and ZSS injectin. v c v EA v ZERO-SEQUENCE SIGNAL (ZSS) GENERATOR v ref cmpensated current cntrller is effective nly if DFF is als implemented, as shwn in [3]. The 6 -segments fr six-step PWM are detected by using cmparatrs t determine the sign f the phase vltages, whereas, the -segments fr three-step PWM are detected by cmparing the phase vltages. Because in the six-step PWM strng transient input-current nise is generated at 6 - segment transitins, additinal measures are taken t imprve the reliability f the 6 -segment detectin. First, the segment detectin is disabled if the abslute value f the sum f phase vltages is significantly greater than zer, i.e., if v a+v b+v c > V zer. Secnd, after a new segment is detected, the segment detectin is disabled fr a specified blanking time T blank t prevent nise-induced segment change due t false segment detectin. In the experimental circuit, the segment detectin is implemented with V zer = 3V and T blank = 9T sw = 45 μs. It shuld be nted that in rder t meet the dead-time requirements fr the IGBT mdule [] and taking int accunt the prpagatin delay times f the ptcuplers in the interface circuit between the DSP and IGBT mdule [5], the duty cycle range is limited frm D min=.5 t D max =.95. The blck diagram f the cntrl circuit cmmn fr bth six-step and three-step PWM implemented with phase-current cntrllers and ZSS injectin is shwn in Fig. 6. ZSS signal fr the six-step PWM, shwn in Fig. 7, is btained frm the input phase vltages and the utput reference vltage as Vref venvp if venvp venvn v =, () ZSS V ref v < envn if venvp venvn while ZSS signals fr the three-step PWM referenced t the psitive and negative envelpe f input phase vltages, shwn in Figs. 8 and, respectively, are defined as and Vref vzss = venvp Vref vzss = venvn, (). (3) It can be bserved in Figs. 7 and 8 that the sum f phase vltage v a and ZSS vltage, when divided by V ref and level shifted by ½ will result in the same duty cycle d ap as / V ref V m V m V ref / V a + V a π π [ωt] Fig. 7 ZSS signal fr six-step PWM. 864

5 V ref / V m V m V a V a + π π [ωt] are distrted at segment transitins. Hwever, these distrtins are mre prnunced fr the six-step PWM. Cnsequently, the six-step PWM has higher THD f phase currents and lwer PF cmpared t the three-step PWM, as shwn by respective THD and PF measurements in Figs. 9 and. The phase-current distrtins at segment transitins are primarily caused by the lw-pass filtering and sampling f the inductr currents. In the three-step PWM, they are als affected by duty-cycle limitatins. V m V a V a V m V ref / V a + π π [ωt] Fig. 8 ZSS signal fr three-step PWM referenced t: psitive envelpe, negative envelpe. Ia Ia Fig. 9 Experimental wavefrms during steady-state peratin (Vrms, kw): phase currents, I b, I c [A] with six-step PWM, three-step PWM referenced t negative envelpe f input phase vltages. btained with the phase-phase-current cntrllers shwn in Figs. 3 and 4, respectively. IV. PERFORMANCE COMPARISON OF THREE-STEP AND SIX- STEP PWM Figures 9 and shw the measured steady-state wavefrms f phase currents i a, i b, and i c at nminal phase vltage f Vrms and fr -kw lad fr the six-step and three-step PWM referenced t the negative envelpe f the phase vltages, respectively. As can be seen in Figs. 9 and, fr bth six-step and three-step PWM, the phase currents I x I x I xfs LPF S/H S/H Ib Ib I x Ic Ic xϵ{a,b,c} THDa=8.5% PFa=.996 THDb=6.83% PFb=.996 THDc=8.9% PFc=.993 THDa=3.79% PFa=.998 THDb=3.9% PFb=.9976 THDc=3.56% PFc=.9976 Fig. Definitin f sampled filtered and sampled unfiltered currents. V b V c f s 5 fs I bs I bfs I cs I cfs - - f s fs I bs I bfs I cs I cfs 5-5 Iafs>Ias Ibfs<Ibs T Icfs>Ics (e) T4 T3 Fig. Key simulated wavefrms during steady-state peratin (Vrms, kw) fr crner frequency f lw-pass filter f khz and withut dutycycle limitatins: input phase vltages [V]; inductr current [A], filtered inductr current f [A], (c) sampled filtered and sampled unfiltered inductr currents [A] fr six-step PWM; (d), f [A], (e) sampled filtered and sampled unfiltered inductr currents [A] fr three-step PWM (referenced t v envn). (c) (d) T THD=7.63% THD=4.5% 865

6 T explain the distrtins in the phase currents caused by the lw-pass filtering and sampling, Simulink simulatins are emplyed. Specifically, simulatins fr the six-step and three-step PWM were perfrmed fr a decreased lw-pass crner frequency f khz, instead f 9.5 khz used in the experimental circuit, t amplify the effect f the lw-pass filtering fr the sake f a mre clear explanatin. The simulatins were dne withut limiting the duty cycle, i.e., by allwing the full duty-cycle range frm zer t unity. The effect f a limited duty-cycle range is addressed by a separate set f simulatins. The results f the simulatins are presented in Fig., which shws the sampled inductr-current wavefrms befre and after the filtering. Specifically, in Figs. (c) and (e), the wavefrms f the sampled filtered and unfiltered inductr current fr the six-step and three-step PWM are cmpared, respectively. The definitin f sampled filter inductr current I xfs, xϵ{a,b,c}, and sampled unfiltered inductr current I xs, xϵ{a,b,c}, are given in Fig.. As it can be bserved in Fig. (c) fr the six-step PWM, in every 6 -segment, the sampled filtered inductr currents in tw actively cntrlled phases are greater than the crrespnding sampled unfiltered inductr currents. Fr example, in the highlighted 6 -segment in Fig. (c), fs>s and I cfs>i cs. T facilitate the understanding f this effect, the wavefrms f input phase vltages v x, xϵ{a,b,c}, and inductr currents f phase a, i.e., i a, i af, i afs, and i as in Figs. -(c) are zmed in arund instant T, where sampled currents i as and i afs have a negative slpe, and instant T, where sampled currents i as and i afs have a psitive slpe, as shwn in Figs. and, respectively. As can be seen in Fig., filtered inductr current i af lags behind inductr current i a. At the sampling instant (at the middle f a switching perid, i.e., at the middle f the turn-n time f the upper switches), i af > i a, and, therefre, the sampled filtered inductr current is greater than the sampled unfiltered inductr current, i.e., i afs>i as. V a V b V - c - f I as I.5 afs V a V b - V c - - I - a -3 f I - as -.5 fs Fig. Key simulated wavefrms in Figs. -(c) fr six-step PWM zmed in arund instants: T, T. V a V b V - c - - f I -3 as -3.5 I afs.5.5 V a V b V - c - - f I -3 as -3.5 I afs Fig. 3 Key simulated wavefrms in Figs., (d), (c) fr three-step PWM zmed in arund instants: T 3, T

7 The current cntrllers shape the sampled filtered-inductr currents t fllw the reference currents s that i afs+i bfs+i cfs=. At the same time, the sum f the three phase currents flwing in the circuit must be zer, i.e., the sum f the sampled unfiltered-inductr currents is als zer i af+i bf+i cf=. Therefre, if i afs>i as and i cfs>i cs, it fllws that i bfs < i bs, as shwn in Fig. (c). Since the current in the phase f nnactive (passive) cntrller is greater than the activelycntrlled phase currents, at the 6 -segment transitins when the rle f actively and nn-actively cntrlled currents changes, the current f the phase transitining t passive cntrl and the phase transitining t active cntrl exhibit step changes. These current changes at the 6 -segment transitins are primarily respnsible fr increased current THD. At -segment transitins f the three-step PWM, the difference between sampled filtered and sampled unfiltered inductr currents is significantly smaller than that at 6 - segment transitins f the six-step PWM, as it can be bserved in Fig. (e). This effect can be explained by the reduced ripple in the inductr currents at the -segment transitins, as shwn by the zmed in wavefrms in Fig. 3. Cnsequently, the phase-current distrtins at segment transitins due t the effect f lw-pass filtering and sampling are less prnunced fr three-step PWM than fr six-step PWM. Simulatin wavefrms in Fig. 4 illustrate the effect f the duty-cycle limitatins n the phase-current distrtins at segment transitins fr the three-step PWM. At - segment transitins, withut duty-cycle limitatins, duty cycles d xn, xϵ{a,b,c}, and inductr currents i x change withut scillatins, as shwn in Figs. 4(c) and 4, respectively. Hwever, limitatin f the maximum duty cycle belw V a V b V c I b I c - D 5 an D 5 bn D 5 cn I a 5 I b I c - D 5 an 5 D bn D cn (e).95.3 Fig. 4 Key simulated wavefrms during steady-state peratin (Vrms, kw) with three-step PWM (referenced t negative envelpe f input phase vltages) fr crner frequency f lw-pass filter f 9.5- khz: input phase vltages [V]; inductr currents [A], and (c) duty cycle f bttm switches [digital values with respect t C pk=5] withut duty-cycle limits; (d) inductr currents [A], and (e) duty cycle f bttm switches [digital values with respect t C pk=5] at 5-95% duty-cycle limits. (c) (d) THD=.8% THD=3.76% TABLE IV THD OF INDUCTOR CURRENTS AT DIFFERENT DUTY- CYCLE LIMITS Duty-cycle limits [%] THD i [%] causes a perturbatin and results in duty-cycle scillatins at -segment transitins, as shwn in Fig. 4(e). Six-step PWM Three-step PWM Six-step PWM Fig. 5 Measured perfrmance f three-step and six-step PWM as functin f lad current: THD i; PF. Three-step PWM 867

8 Cnsequently, inductr currents als exhibit scillatins at -segment transitins as shwn in Fig. 4(d), which results in increased THD. Specifically, with 5-95% dutycycle limits, the THD f inductr currents increases by.48% cmpared t that withut duty-cycle limits. The THD f inductr currents at different duty-cycle limits is presented in Table IV. It can be cncluded frm Table IV that in rder t meet the THD < 5% requirement, the duty-cycle limits shuld be equal r less than 6-94%. Finally, the measured THD f phase currents and pwer factr (PF) in the %-% lad range, are presented in Figs. 5 and, respectively. It shuld be nted that the THD and PF values in Fig. 5 are btained as average values f the measured THD and PF f individual phases. As can be seen frm Fig. 5, in the entire measured lad range the three-step PWM exhibits lwer THD and crrespndingly higher PF cmpared t the six-step PWM. The perfrmance f the three-step is significantly better than that f the six-step PWM at lighter lads. Fr the experimental circuit with the three-step PWM the measured THD f the input current was belw 5% in the 5-% lad range. V. SUMMARY In this paper, a three-step PWM methd fr average current cntrlled three-phase six-switch bst PFC rectifier is prpsed and its perfrmance is cmpared t the cnventinal six-step PWM methd. The steady-state duty cycles f the switches in the threestep PWM d nt exhibit abrupt changes at the -segment transitins, unlike the steady-state duty cycles f the switches in the six-step PWM which change abruptly at the 6 - segment transitins. As a result, the three-step PWM induces smaller input-current transients at the segment transitins, which imprves its THD and PF perfrmance and reduces its sensitivity t false segment detectin. Hwever, the threestep PWM, unlike the six-step PWM, is adversely affected by duty cycle limitatins. Bth the six-step and three-step PWM can be implemented either with phase-current cntrllers and an apprpriate ZSS injectin r with phase-phase current cntrllers, which inherently include ZSS injectin. Perfrmance cmparisn f the three-step and six-step PWM is dne n a 3-kW prttype f the three-phase sixswitch bst PFC rectifier. In the entire measured lad range the three-step PWM exhibits lwer THD and crrespndingly higher PF cmpared t the six-step PWM. The perfrmance f the three-step is significantly better than that f the six-step PWM at lighter lads. REFERENCES [] J.W. Klar and T. Friedli, The essence f three-phase PFC rectifier systems Part I, IEEE Trans. Pwer Electrnics, vl. 8, n, pp , Jan. 3. [] T. Friedli, M. Hartmann, and J.W. Klar, The essence f three-phase PFC rectifier systems Part II, IEEE Trans. Pwer Electrnics, vl. 9, n, pp. 5436, Jan. 4. [3] M.P. Kazmierkwski and L. Malesani, Current cntrl techniques fr three-phase vltage-surce PWM cnverters; A survey, IEEE Trans. Ind. Electrnics, vl. 45, n 5, pp , Oct [4] M. Malinwski and M.P. Kazmierkwski, Cntrl f three-phase PWM rectifiers, Cntrl in Pwer Electrnics Selected Prblems, Academic Press, San Dieg, CA,. [5] M. Hartmann, H. Ertl, and J.W. Klar, Current cntrl f three-phase rectifier systems using three independent current cntrllers, IEEE Trans. Pwer Electrnics, vl. 8, n 8, pp. 3988, Aug. 3. [6] P.C. Tdd, UC3854 cntrlled pwer factr crrectin circuit design, Unitrde Applicatin Nte, U-34, pp [7] M. Fu and Q. Chen, A DSP based cntrller fr pwer factr crrectin (PFC) in a rectifier circuit, Prc. Applied Pwer Electrnics Cnf. (APEC), pp. 449, Mar.. [8] C. Qia and K.M. Smedley, A general three-phase PFC cntrller fr rectifiers with a parallel-cnnected dual bst tplgy, IEEE Trans. Pwer Electrnics, vl. 7, n 6, pp , Nv.. [9] S. Hiti, D. Brjević, R. Ambatipudi, R. Zhang, and Y. Jiang, Average current cntrl f three-phase PWM bst rectifier, Rec. IEEE Pwer Electrnics Specialists Cnf. (PESC), pp. 3-37, Jun [] K. Zhu and D. Wang, Relatinship between space-vectr mdulatin and three-phase carrier-based PWM: a cmprehensive analysis, IEEE Trans. Ind. Electrnics, vl. 49, n, pp , Feb.. [] Pwerex: PM5CLA Intelligent Pwer Mdules, Data Sheets, 9. [] Texas Instruments: TMS3F88 Digital Signal Prcessr, Data Manual,. [3] L. Huber, M. Kumar, and M.M. Jvanvić, Perfrmance cmparisn f Pnd P cmpensatin in average-current-cntrlled three-phase sixswitch bst PFC rectifier, Prc. Applied Pwer Electrnics Cnf. (APEC), pp , Mar. 4. [4] D.M. Van de Sype, K. De Gusseme, A.P.M. Van den Bssche, and J.A. Melkebeek, Duty-rati feedfrward fr digitally cntrlled bst PFC cnverters, IEEE Trans. Ind. Electrnics, vl. 5, n, pp. 8, Feb. 5. [5] Pwerex: BP7B - L-Series IPM Interface Circuit Reference Design, Applicatin Ntes, 9 868