Robust Voltage Commutation of Conventional Matrix Converter

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2 Rbust Vltage Cmmutatin f Cnventinal Matrix Cnverter Lixiang Wei, Thmas A.Lip, H Chan Department f Electrical and Cmputer Engineering The University f WiscnsinMadisn, Madisn, WI, 575, USA Abstract The threephase acac cnverter termed the matrix cnverter can prvide high quality input/utput wavefrms and adjustable input pwer factr withut any large energy strage cmpnent. Hwever, it has nt yet fund much acceptance in industry. The main reasn is that it requires a cmplicated cmmutatin scheme t prevent input side shrt circuits and utput side pen circuits. This paper develps a new vltage cmmutatin scheme fr the cnventinal matrix cnverter. One advantage f this scheme is that it prvides rbust vltage cmmutatins fr the cnverter withut sacrificing the quality f the line side current wavefrms. The secnd advantage is that it needs the least infrmatin frm the system than any algrithm yet reprted. It nly detects the line side synchrnizatin angle which can have detectin errrs within p/6 radians under unity input pwer factr t prvide accurate cmmutatin. The last advantage f this scheme is that it can prvide easier shut dwn sequences fr the system. Theretical analysis, simulatin and experimental results are prvided t verify its effectiveness in the paper. I. INTRODUCTION The three phase acac cnverter r matrix cnverter, M. Venturini [1] as shwn in fig.1, can prvide high quality input/utput wavefrms and adjustable input pwer factr withut use f a large energy strage cmpnent. Subsequently, it has becme an alternative candidate fr threephase AC/AC pwer cnversin. Hwever, it has nt yet fund much acceptance in industry. The main reasn is that it needs cmplicated cmmutatin scheme fr the idea switches t prevent input side shrt circuits and utput side pen circuits. Several slutins have been published t slve this issue [][6]. In papers [][], vltage and current cmmutatin schemes are prpsed respectively. The main cncept f these tw papers is t intrduce a multistep vltage r current dependant switching prcedure that can prevent false cmmutatins. Hwever, since the accuracy f these tw methds is based upn the sign f either input line vltage r utput lad current, when these values are near zer, false cmmutatins can still be generated and ultimately damage the pwer switches. Papers [4][5] prpsed a rbust vltage cmmutatin scheme. It detects the magnitude f line side vltage dynamically, when the system perates at sme critical regin where tw input phase vltages are nearly equal t each ther, it creates new PWM sequences t prevent the cmmutatin between these tw phases. The advantage f this methd is that the cnverter can perate safely. Hwever, since the switching sequences are changed, the line side current is als distrted. References [6][7] prpsed anther intelligent cmmutatin methd. Its main principle is t build an intelligent circuit within the gate driver bard t imprve the accuracy f sign detectin. Hwever, a rather cmplicated circuit has t be added t the system. This paper develps a rbust vltage cmmutatin scheme fr the cnventinal matrix cnverter. One advantage f this scheme is that it prvides rbust vltage cmmutatins fr the cnverter withut sacrificing the line side current wavefrm quality. The secnd advantage is that it needs nly minimal infrmatin frm the system. It nly need detect the line side synchrnizatin angle which can have detectin errrs within ±π/6 radians under unity input pwer factr peratin. The final advantage f this scheme is that it can prvide easier shut dwn sequences fr the system. ~ ~ ~ V sa V sb L s i sa i sb i sc C f V a V b i a i b i c S aup Sbup Scup Saun Sbun Scun Vsu Savp Sbvp Scvp Savn Sbvn Scvn i sv Vsv Fig. 1. Cnfiguratin f matrix cnverter system The implementatin f this scheme is based n the space vectr PWM cntrl f cnventinal matrix cnverter. By detecting the synchrnizatin angle f line side vltage, six intervals are identified. In each interval, each switching cycle is subdivided int tw prtins. In each prtin, the switches f the cnverter are classified int three types, named nswitch, ffswitch, and mdulatedswitch. With this three switch types, the cnverter can be regarded as a DC/AC inverter. Finally, by applying apprpriate vltage vectrs in each prtin, a rbust vltage cmmutatin scheme can be established. This paper is rganized int fllwing steps. After a brief presentatin f the input/utput transfrming equatins f the circuit, the new vltage cmmutatin scheme is prpsed. S awp S bwp S cwp S awn Sbwn Scwn i sw Vsw

3 Meanwhile, the three switch types and equivalent circuit f the cnverter is demnstrated and the shut dwn f the cnverter is discussed. The paper then demnstrates the space vectr PWM methd f the matrix cnverter and prpses a crrespnding PWM sequence fr ne switching cycle. Finally, simulatin and experimental result n a clamp less matrix cnverter are prvided t prve its feasibility. II. CIRCUIT AND SYSTEM CONFIGURATION A simplified pwer circuit f matrix cnverter is shwn in Fig.1. In this figure, each f the bilateral switches S jk cnsists f tw antiseries IGBTs (named S jxp, S jxn ) and tw antiseries dides. The symbl j {a, b, c} represents the phases at line side, x {u, v, w} represents the phases n the lad side, p designates the switches whse current flws frm line side t lad side, and n indicates the switches whse current flws frm the lad side t line side. T simplify the analysis, it is assumed that there is n input filter n the line side. Hence, frm Fig.1, the fllwing equatins can be btained: L s = ; C f = ; V sj = Vj ; i sj = i j (1) where V j and i j is the line side phase vltage and current at the cnverter side in phase j, L s is the value f line side filter inductance, and C f is the value f line side filter capacitr. It is assumed that the line side vltage is a three phase balanced vltage surce dented as the input and utput f the cnverter. Thus, in each switching cycle, bth the input vltage and utput current can be cnsidered as cnstant. II. CIRCUIT AND SYSTEM CONFIGURATION T simplify the analysis, it is assumed initially that the line side pwer factr is unity, thus the line side vltage and current has the same phase angle. The cmmutatins while the line side pwer factr is nt unity will be discussed later in this paper. A. The six intervals Six intervals are identified based n detectin f the input current synchrnizatin angle as shwn in fig.. Because f unity pwer factr, during each interval, nly ne f the threephase input vltages has the largest abslute value. Fr example, V sa has the largest abslute vltage in interval 1, has the largest abslute vltage in interval, and s frth. B. Tw prtins and three switch types Each switching cycle is split int tw prtins and the switches in the cnverter are classified as three types, including nswitch, ffswitch and mdulated switch. In each prtin, the nswitches and ffswitches remain turn n and ff respectively; the mdulated switches cmmutate like the traditinal DC/AC inverter. Vsa csθa cs( ωit) csθb cs( ωit ) csθc cs( ωit ) and the lad side is a three phase balanced current surce described as () i i i su sv sw csθ i cs( ω t ϕ cs( ω t ϕ cs( ω t ϕ ) ) ) In () and (), ω i, ω are the input and utput angular frequencies; ϕ is the initia l electrical angle f the phase current; V m, I are the amplitudes f input vltage and utput current respectively; θ a, θ b, and θ c are electrical angles f three phase input vltage. Fr purpses f analysis, it is assumed that the switching frequency is far greater than fundamental frequencies f bth () Fig.. Six intervals f the system Fr example, in interval has the largest abslute vltage and the tw largest psitive input line vltages are V sa and V sb ;. Then, the line side switching states in each prtin can be determined by the fllwing steps: In prtin 1, defining S bxp and S cxn as mdulatedswitches and cmmutate in cmplimentary fashin, S axp and S axn as ffswitches, and S bxn and S cxp as nswitches. With this definitin, the matrix cnverter can be simplified as a DC/AC inverter as shwn in fig. (a). In the inverter, the DC side vltage V dc equals t line vltage V sb ; the DC side current equals t input phase current i sb and i sc, and

4 input current i sa is zer. The duty cycle f this prtin is defined as d bc. In prtin, defining S axp and S cxn as mdulatedswitches, S bxp and S bxn as ffswitches; and S axn and S cxp as nswitches. Again, the matrix cnverter can be simplified as a DC/AC inverter as illustrated in fig. (b). In this inverter, the DC side vltage V dc equals t V sa ; the DC side current equals t input phase current i sa and i sc ; and input current i sb is zer. The duty cycle f this prtin is defined as d ac. S bup Sbvp V sb Scun S cvn Sbwp S cwn i sv isw Saup S avp V sa Scun Scvn Sawp Scwn i su i sv isw (a) Prtin 1 (b) Prtin Fig.. Equivalent circuit in regin Similarly, in interval 5, has the highest vltage and the tw abslute psitive line vltages are V sa and V sb respectively. In this situatin, the three switch types are defined in each prtin thrugh fllwing steps: In prtin 1, defining S axn and S cxp as mdulatedswitches, S bxp and S bxn as ffswitches, and S axp and S cxn as nswitches. The cnverter is simplified as the third DC/AC inverter as shwn in fig.4 (a). In this inverter, the DC side vltage V dc equals t V sa, the DC side current equals t input current i sc and i sa ; the input phase current i sb equals zer. The duty cycle f this prtin is defined as d ac. In prtin, defin ing S bxn and S cxp as mdulatedswitches, S axp and S axn as alwaysff switches, and S bxp and S cxn as alwaysn switches. The furth DC/AC inverter can be derived as illustrated in fig.4 (b). In this inverter, the DC side vltage V dc equals t V sb, the DC side current equals input phase current i sc and i sb, and i sa equals t zer. The duty cycle f this prtin is defined as d bc. Using the same methd, when the system perates at ther intervals, the same DC/AC inverter with different DC vltages can be btained. C. Vltage cmmutatin scheme With the six intervals and three switch types analyzed abve, the cmmutatin f the cnverter can be established by fllwing plicies. In each prtin, dead time is applied between each pair f mdulated switches as shwn in fig. and fig. 4. The cmmutatins f these mdulated switches are the same as that f the cnventinal DC/AC inverter. In each interval, the same zer vectr which cnnects all utputs t the same input phase that has the highest abslute value is applied at bth the beginning and ending f each prtins. This implies that the same zer vectr is utilized in bth the beginning and ending f each prtins in each interval. As a result, prtin 1 and can transit t each ther autmatically and the cmmutatins f the nswitch and ffswitch within each interval are all sft switching, thus multistep cmmutatin is nt needed. The transitin f different intervals invlves the transitin f different zer vectrs. This can be achieved by utilizing the furstep vltage cmmutatin scheme mentined in [4]. Fr instance, if the system transits frm interval 6 t interval 1, the matrix cnverter has t transit frm zer vectrs BBB t AAA. Since the sign f these tw vltages are very easy t decide and n cmmutatin errrs will be generated. III. CONVERTER SHUT DOWN It can be shwn that the shut dwn prcedure fr the matrix cnverter is als simplified. When the cnverter starts t shut dwn, all the mdulated switches in each prtin are turned ff; the nswitches and ffswitches perate similarly as in the running mde. Then, the matrix cnverter perates like an uncntrlled dide bridge with the utput lad as its input side. Fig.5 shws the equivalent circuit in each prtin at interval during shut dwn. V sb i sb = i dc V sa i sa = i dc S cup S cvp Scwp Scup Scvp Scwp V dc D bup Dbvp D bwp V dc D aup D avp D awp Saun Savn Sawn Sbun Sbvn Sbwn Dcun Dcvn D cwn Dcun Dcvn D cwn Vsa i su i sv i sw i su isv isw isc = i dc i sv i sw isc = i dc i sv i sw (a) Prtin 1 (b) Prtin Fig. 4. Equivalent circuit in regin 5 (a) Prtin 1 (b) Prtin Fig. 5. Equivalent circuit in regin while the cnverter shut dwn

5 Frm fig.5, since the energy nly flws frm the lad side t the line side, all the pwer at lad side feeds back t the line side autmatically. Finally, while all the energy f the lad flws back t the surce and utput phase current reduces t zer, the system can turn ff all ther switches. Fig. 6 shws the gating signals f S aup and S aun at unity input pwer factr while the cnverter shuts dwn. 11 V v,t v Vm V = k θ 111 V m V v 1, t 1 1 Fig. 7. Space vectr PWM fr inverter while < θ < π Because there are tw prtins during each switching cycle, the duty cycles V 1, V, and V are als distributed t each prtin. In the first prtin, they are: Fig. 6. Gating signal f switch S aup, S aun and the line vltage f the cnventinal matrix cnverter during shut dwn IV. SVPWM AND THE CORRESPONDING PWM SEQUENCE It is useful t initially cnsider the matrix cnverter as a cnventinal VSI inverter supplying utput vltage V su, V sv, and V sw by a dc vltage surce V dc = V m /. In cmplex frm, the space vectr f the desired utput vltages is v j j V V m ref = Vsu Vsv e Vsw e _ = k θ Where < k < is a cnstant. Suppsing (4) < θ < π and that the system perates in interval, this vectr can be apprximated by its tw adjacent vltage vectrs (V 1 and V ) and the zer vltage vectr V as shwn in Fig. 6. The duty ratis f these vectrs are k π k d1 = sin( θ ) ; d = sin( θ ) ; d = 1 d1 d (5) The average DC current f the inverter with the abve duty cycles is determined as i dc = k I cs( θ θi ) im (6) d1 bc = d1 cs θb ; d bc = d cs θb d bc = d / ; d bc = d1 bc d bc d bc (7) In the secnd prtin, they are d1 ac = d1 cs θ a ; d ac = d cs θ a d ac = d / ; d ac = d1 ac dac dac (8) Cmbining Eqs. (5) t (8), the actual average utput vltage vectr and the input current can finally be derived as v V V m = k θ (9) isa im cs θa (1) isb im cs θb (11) isc im cs θc (1) This result verifies that the prpsed space vectr PWM cntrl methd generates the same actual utput vltage as the reference vltage and the line side pwer factr can inherently remain at unity. Figure 8 shws the PWM sequence f ne switching cycle f the cnverter in interval. It shws that the rules specified in previus paragraph are strictly fllwed. When the system perates at the ther intervals r when θ > π, the crrespnding duty cycle f vltage vectrs, crrespnding PWM sequences, and the same results like eqs (4) ~ (1) can als be btained.

6 d bc d bc Vsu Vsv Vsw isa isb isc d bc d1bc isw isw dbct s t s Vsa d ac ts Vsa Vsa isw isw Vsa Fig. 8. PWM sequences in each switching cycle f interval d ac d ac d1ac d ac Frm the abve analysis, the prpsed PWM cntrl methd has the fllwing characteristics: Under unity input pwer factr, all cmmutatins during the peratin ccur between the input phase with highest abslute vltage value and ne f the ther tw phases. Since the cmmutatin vltage is never less than.866v m, accurate cmmutatin can be guaranteed even the synchrnizatin angle f input vltage is nt accurate. In fact, this value can have detectin errrs between π 6 t π 6 withut cmmutatin errrs. The input current is pure sine waves with nly high rder harmnics arund the switching frequency. Its magnitude under unity pwer factr is I im. The utput vltage remains pure sinusidal with nly high rder harmnics arund switching frequency. The magnitude f the utput phase vltage is kv m (<k<.866). Since the cmmutatin vltage can never be less than.866, the switching lsses f the cnverter cannt be ptimized. Mrever, because sme zer vectrs has t be utilized in each prtin t make transitins, the highest vltage transfer ratin is slightly smaller than.866. When the input pwer factr f the system is nt unity, the same cmmutatin can be applied. It can be demnstrated that the cnverter cmmutates safely if the line side pwer factr is grater than.866. If it is lwer than the.866, this cmmutatin scheme is nt applicable. Frtunately, because the matrix cnverter generally perates near unity pwer factr, this cmmutatin scheme can still be utilized. Fig. 9 shws the simulatin results f the cnventinal matrix cnverter under unity pwer factr peratin. The wavefrms prvided are line side phase vltage V sa and current i sa, lad side vltage V suv and lad side phase current i su. In fig. 1, the same wavefrms f experimental results are prvided. In fig.11, the experimental results f switch vltage and switch current are presented. Fllwing cnclusins can be bserved: Frm fig. 9 and fig. 1, the simulatin and experimental result agrees well with each ther; In fig. 9. and fig. 1, bth line side and lad side currents are essentially sinusidal, which prves that the prpsed PWM methd can prvide high quality input current and utput vltage; Because f the existence f line side filter, the pwer factr f line side vltage surce has leading pwer factr. This is verified by bth the simulatin and experimental results; Since the prpsed space vectr PWM methd can perate safely under nrmal peratin withut any clamp circuit, the rbustness f the vltage cmmutatin scheme and the effectiveness f the shut dwn scheme are verified. VI. CONCLUSION In this paper, a rbust vltage cmmutatin scheme is applied t the space vectr PWM cntrl f cnventinal matrix cnverter. With this methd, the cnverter can prvide rbust vltage cmmutatins with nly the synchrnizatin angle f line side vltage; thus it is pssible t further reduce the cst f the cnventinal matrix cnverter. Mrever, the shut dwn sequence f the cnverter is als simplified. Analysis shws that the methd can prvide high quality input/utput wavefrms withut degrading the input current wavefrms. Finally, simulatin and experimental results n a clamp less matrix cnverter are bth presented t demnstrate its effectiveness. V. SIMULATION AND EXPERIMENTAL RESULTS The prpsed PWM cntrl methd has been studied extensively with MATLAB/SIMULINK n the cnventinal matrix cnverter with RL lad. A clamp less cnventinal matrix cnverter was als cnstructed in the lab. Bth the simulatin and experimental results are prvided in this chapter t verify its effectiveness. Fig. 9. Simulatin result f the matrix cnverter

7 Fig. 1. Experimental result f the matrix cnverter [4] Mahlein J., Igney J., Braun M, Simn Olaf ; Rbust matrix cnverter cmmutatin withut explicit sign measurement, EPE Graz 1, CD ROM Paper 19. [5] Jchen Mahlein, Jens Igney, Jrg Weigld, and et al, " Matrix cnverter cmmutatin strategies with and withut explicit input vltage sign measurement", IEEE Trans. n Industrial Electrnics, vl. 49, N.,, pp [6] J. Chang, T. Sun and A. Wang, "Medium pwer ACAC cnverter based n integrated bidirectinal pwer mdules, adaptive cmmutatin and DSP cntrl", In Prc. IEEE IAS 99, pp [7] Patrick W.Wheeler, Jn C. Clare, Lee Empringham and et al, " Gate drive level intelligence and current sensing fr matrix cnverter current cmmutatin", IEEE Trans. n Industrial Electrnics, vl. 49, N.,, pp [8] Vlakt Vlatkvic, and Dusan Brjevic, " Digitalsignalprcessrbased cntrl f threephase vectr mdulated cnverters", IEEE Trans.n Industrial Electrnics, vl. 41, N., 1994, pp. 6. Fig. 11. Experimental result f switch vltage and switch current ( Sau ) VII. ACKNOWLEDGEMENT This wrk is supprted by the Center fr Pwer Electrnics Systems. CPES is a Natinal Science Fundatin ERC under Award Number EEC The authrs als shw their special thanks t Mtrla Cmpany fr its dnatin f a DSP 56F85 EVM bard and sftware develpment kit Cde Warrir 4. t this prject. VIII. REFERENCES [1] M. Venturini, "A new sine wave in, sine wave ut, cnversin technique eliminates reactive cmpnent", in Prc. POWERCON 7, 198, pp. E1E15. [] M. Ziegler, W. Hfmann, "SEMI natural tw steps cmmutatin strategy fr matrix cnverters", in Prc IEEE PESC 98, pp [] JangHyun Yum, and BngHwan Kwn, "Switching technique fr currentcntrller ACtAC cnverters", IEEE Trans. n Industrial Electrnics, vl. 46, N., 1999, pp. 918.