EE380: Exp. 2. Measurement of Op-Amp Parameters and Design/ Verification of an Integrator

Transcription

1 EE380: Exp. 2 Measurement Op-Amp Parameters and Design/ Veriicatin an Integratr Intrductin: An Opamp is a basic building blck a wide range analg circuits. T carry ut design circuits cnsisting ne r mre pamps, a gd knwledge pamp characteristics is essential. Any element, including an pamp can be mdeled in many dierent ways. The cmplexity (and therere accuracy) the mdel required depends n the nature the design task at hand. In the initial stages the design prcess, when a new circuit structure is being cnceptualized, it is best t use the simplest mdel that captures the essence the circuit element. Fr example, r an p-amp, an ideal p-amp mdel which assumes the llwing characteristics is cmmnly used: Vltage gain ( A V ) Bandwidth ( T ) Input resistance ( i ) Output resistance ( ) 0 And thers such as ininite cmmn-mde rejectin rati, n limits n input and utput vltages and currents, zer nise etc. In negative eedback the ideal Op-amp has a very cnvenient prperty virtual grund which prvides us with an element that has shrtckt and pen ckt simultaneusly between its input terminals. Many interesting circuits can be designed based n this useul prperty including an Integratr shwn in Fig. V IN +V -V Fig. Once a circuit such as the Integratr has been cnceptualized, the next step is t prceed with the design using a mre realistic mdel that apprximates clsely the behavir

2 real p-amps. Sme the imprtant eatures the mdel r a real p-amp are discussed in the next sectin. Op-Amp Mdel : A practical pamp has neither ininite gain and bandwidth nr zer utput resistance. Besides the act that all these parameters have inite values, there are several ther new parameters which can have a signiicant impact n the circuit perrmance. These include : Input set vltage ( V IO ): This parameter highlights a shrtcming in all practical pamps namely that even i V V 0, the utput vltage is nt zer. It arises due imperect matching cmpnents within the p-amp circuit. Its eect is mdeled by cnnecting a dc vltage surce value V IO t the nn-inverting terminal as shwn in Fig. 2. V IO Fig. 2 Input bias current ( I IB ): This represents the base current the input transistrs inside the p-amp circuit. It is mdeled by cnnecting dc current surces t the inverting and nn-inverting terminals as shwn in Fig. 3. The dierence the tw bias currents is called the Input set current I IO. I IB - I IB + Fig. 3 Bandwidth ( T ) : As mentined earlier, the bandwidth a real p-amp is inite. The pen lp vltage gain the ampliier can be described by the relatin 2

3 A L ( ) A L () ja L (0) (0) T where T is called the unity gain requency the p-amp because the vltage gain drps t unity at this requency. Eq. () can be used t determine the requency characteristics any p-amp circuit. Fr example, r an inverting ampliier, the vltage gain can be shwn t have the llwing relatinship with requency where A V 2 ( ) j T 2 (2) It is imprtant t remember that virtual grund assumptins are nt true whenever requency respnse p-amp is cnsidered imprtant. Slew ate (S): This parameter is a characteristics the large signal transient respnse an p-amp. Nrmally the transient behavir is gverned by the requency respnse characteristics Eq. () but because internal current limitatins there is a limit t the maximum rate at which the utput vltage can change with time. The dv maximum value r is called the slew rate. It is typically measured r an p-amp dt in the unity gain mde. Besides the parameters mentined abve there are several thers including limits n the max. utput vltage swing and max. utput current which are likely t be imprtant r Integratr design. The ull range p-amp parameters and their typical values can be btained rm the data sheets prvided by the manuacturer. Data sheet r 74 pamp is given in the end. Measurement p-amp parameters: Design suitable experiments t measure the parameters mentined in the previus sectin r a 74 p-amp prvided t yu in the labratry. Althugh values r these parameters is prvided by the manuacturer, an ert t design experiments that selects ne parameter at a time and magniies its eect s that it is measurable at the utput besides deepening the understanding als prvides us with a eel r cnditins under which these parameters becme signiicant. 3

4 Design a Practical Integratr: The circuit Fig. has t be mdiied in light the new inrmatin abut p-amps mentined in sectin 2. In particular, the eect set vltage and bias currents is t rce the p-amp in circuit t saturatin. This can be avided by cnnecting a resistr acrss the capacitr as shwn in Fig. 4. Design this circuit r the llwing speciicatins: Specs.: The Integratr is t be used r cnverting a square wave int a triangular wave is shwn in Fig. 4. F V V IN +V -V Fig. 4 VO The nnlinearity in the triangle wave ( 00 ) 5% VO Input requency 00 Hz. Input vltage = 5V. dc set 5 % peak utput vltage Design the Integratr s as t maximize the upper limit n the requency peratin. The nnlinearity mentined abve reers t the max. deviatin (%) the integratr utput rm the value btained rm an ideal Integratr. The design requires equatins that describe the behavir the Integratr can be btained thrugh the well knwn methds p-amp ckt. analysis. These are listed at the end. 4

5 Veriicatin : veriy yur design thrugh SPIE simulatins and thrugh experimental measurements in the labratry. Explain any discrepancy bserved. The specs. cncerning nnlinearity will be diicult t measure in the lab. Use yur subjective judgement t decide when nnlinearity becmes just visible n the scillscpe. Appendix Design equatins V F (D) 2 Vi j T (D2) F (D3) ( F ) T F Vset VIO ( ) I IB F (D4) V V 2 (D5) Frm the equatins given abve, derive an expressin r nnlinearity s as t carry ut the design. 5

6 The circuits given belw can be used r the measurement dierent pamp parameters: 2 Fr measurement Input Oset Vltage Fr measurement Input bias current 5 0 V IN Adjust Input requency such that the required utput is abtained Fr Measurement Input Bias urrent Fr Measurement Slew ate 6

7 Simpliied Datasheet 74 Opamp A74A and A74E Electrical haracteristics Vs=5V,Ta=25 unless therwise speciied A74A/E haracteristics nditin Mi Ty Ma Unit n p x Input set vltage mv Average input set vltage drit 5 V/ Input set current na Average input set current Drit 0.5 na/ Input Bias urrent na Pwer Supply ejectin ati VS=+0,- 20;Vs=+20V 5 50 V/ V,-0V,s=50 Output Shrt ircuit urrent ma Pwer nsumptin Vs=20V mw Input Impedance Vs=20V M Large Signal Vltage Gain Vs=20V,l=2k Vut=5V V/m V Transient espnse ise s Time 5 20 (Unity Gain) 6.0 Oversht Bandwidth 43.5 MHz 7 Slew ate(unity Gain) Vin=0V V/s eerence: (i) (ii) Analysis and Design Analg Integrated ircuits, Gray, Hurst, Lewis and Meyer, pp. 404, Jhn Wiley,200. Understanding Operatinal Ampliier Speciicatins 7